Post on 21-Jan-2016
description
On the development of the final optical On the development of the final optical multiplexer board prototype for the multiplexer board prototype for the
TileCal experimentTileCal experiment
V. GonzálezV. González
Dep. of Electronic EngineeringDep. of Electronic Engineering
University of Valencia, SpainUniversity of Valencia, Spain
OutlineOutline
IntroductionIntroduction
Previous work OMB 6UPrevious work OMB 6U
Final prototype OMB 9UFinal prototype OMB 9U
Present statusPresent status
IntroductionIntroduction
RODs interface LVL1 and LVL2 at each RODs interface LVL1 and LVL2 at each detectordetector– Some preprocessing available if neededSome preprocessing available if needed
For TileCal, radiation issues changed front For TileCal, radiation issues changed front end connection to RODsend connection to RODs– Two fibers with same data output each Two fibers with same data output each
FrontEnd boardFrontEnd board– Need to select the fiber with good data in Need to select the fiber with good data in
case of errors (OMB aka PreROD)case of errors (OMB aka PreROD)
Previous work OMB 6UPrevious work OMB 6U
SpecificationsSpecifications– VME 6U Board formatVME 6U Board format– 2 input channels (4 input 2 input channels (4 input
fibers) @ 640 Mbit/sfibers) @ 640 Mbit/s– 2 output channels (2 output 2 output channels (2 output
fibers)fibers)– Digital data analysis (CRC Digital data analysis (CRC
computation)computation)– Trigger and Busy inputsTrigger and Busy inputs
Previous work OMB 6UPrevious work OMB 6U
FunctionalityFunctionality– Error detection Error detection
(multiplexing)(multiplexing)– Data injectionData injection
Preconfigured event Preconfigured event (counter)(counter)Configurable event Configurable event loadable through VMEloadable through VME
– Different trigger optionsDifferent trigger optionsExternal (NIM or LVTTL)External (NIM or LVTTL)Internal. Variable Internal. Variable frequencyfrequency
– SingleSingle– LoopLoop– Non-stopNon-stop
Previous work OMB 6UPrevious work OMB 6U
Designed with Cadence PSD 15.0 and Altera Designed with Cadence PSD 15.0 and Altera Quartus II for FPGA programsQuartus II for FPGA programs
Technical detailsTechnical details– 2 Cyclone EP1C12 and 1 ACEX EP1K100 FPGAs2 Cyclone EP1C12 and 1 ACEX EP1K100 FPGAs– 12 copper layers, 35 μm thick 12 copper layers, 35 μm thick – > 2000 routes 0.15 mm width> 2000 routes 0.15 mm width– > 2000 vias 0.2 mm > 2000 vias 0.2 mm – SMD components widely usedSMD components widely used
Previous work OMB 6UPrevious work OMB 6U
TEST at Valencia LABTEST at Valencia LAB– Firmware adjustmentFirmware adjustment– Integration with ROD Integration with ROD
motherboardmotherboard– Development of control Development of control
software (XTestROD)software (XTestROD)
TEST at CERN (USA15)TEST at CERN (USA15)– During commissioningDuring commissioning– Integration with 8 TileCal Integration with 8 TileCal
RODROD– Used now for ROD Used now for ROD
production tasksproduction tasks
Final prototype OMB 9UFinal prototype OMB 9U
Same basic functionalitySame basic functionality– CRC checkingCRC checking– Data injectionData injection– 40 MHz clock40 MHz clock
DifferencesDifferences– 8 channels8 channels
16 input fibers16 input fibers
8 output fibers8 output fibers
– TTCrxTTCrx– Mezzanine connectors: more processing power?Mezzanine connectors: more processing power?
Final prototype OMB 9UFinal prototype OMB 9U
Technical detailsTechnical details– 9U VME slave board9U VME slave board– Dual optoelectronic transmitter/receiver (Stratos) Dual optoelectronic transmitter/receiver (Stratos) – GLINK chipsGLINK chips
8 HDMP-1032: transmitter8 HDMP-1032: transmitter16 HDMP-1034: receiver16 HDMP-1034: receiver
– 8 Cyclone EP1C12 (CRC FPGA)8 Cyclone EP1C12 (CRC FPGA)One for each channel (2 input fibers and 1 output fiber)One for each channel (2 input fibers and 1 output fiber)
– 1 Cyclone EP1C20 (VME FPGA)1 Cyclone EP1C20 (VME FPGA)Changed from ACEX in 6U version for more logic resourcesChanged from ACEX in 6U version for more logic resourcesIncludes TTCrx control firmwareIncludes TTCrx control firmware
Final prototype OMB 9UFinal prototype OMB 9U
P2
(160
pin)
P1
(160
pin)
O / E
O / E
O / E
O / E
E / O
E / O
O / E
O / E
O / E
O / E
E / O
E / O
O / E
O / E
O / E
O / E
E / O
E / O
O / E
O / E
O / E
O / E
E / O
E / O
VMECONTROL
FPGA
VoltageDC/DC
converter
P0
Drawer_1
Drawer_1'
ROD Controller VMEacces functions:- CSR read/write- Reset board (e.g. incase of sychronizationerrors)- Configure for “16 to 8”or “16 to 4”
G-LINK TX
HDMP1032/1022
G-LINK RX
HDMP1034
CRCFPGA
G-LINK RX
HDMP1034
G-LINK RX
HDMP1034
G-LINK RX
HDMP1034
G-LINK TX
HDMP1032/1022
2 diff
2 diff
2 diff
2 diff
16@40MHz
16@40MHz
16@40MHz
16@40MHz
16@40MHz
16@40MHz
2 diff
2 diff
PECL LVTTL
CRCFPGA
G-LINK TX
HDMP1032/1022
G-LINK RX
HDMP1034
CRCFPGA
G-LINK RX
HDMP1034
G-LINK RX
HDMP1034
G-LINK RX
HDMP1034
G-LINK TX
HDMP1032/1022
2 diff
2 diff
2 diff
2 diff
16@40MHz
16@40MHz
16@40MHz
16@40MHz
16@40MHz
16@40MHz
2 diff
2 diff
PECL LVTTL
CRCFPGA
Drawer_2
Drawer_2'
Drawer_2
Drawer_2'
G-LINK TX
HDMP1032/1022
G-LINK RX
HDMP1034
CRCFPGA
G-LINK RX
HDMP1034
G-LINK RX
HDMP1034
G-LINK RX
HDMP1034
G-LINK TX
HDMP1032/1022
2 diff
2 diff
2 diff
2 diff
16@40MHz
16@40MHz
16@40MHz
16@40MHz
16@40MHz
16@40MHz
2 diff
2 diff
PECL LVTTL
CRCFPGADrawer_2
Drawer_2'
Drawer_2
Drawer_2'
RODx_1
RODx_2
G-LINK TX
HDMP1032/1022
G-LINK RX
HDMP1034
CRCFPGA
G-LINK RX
HDMP1034
G-LINK RX
HDMP1034
G-LINK RX
HDMP1034
G-LINK TX
HDMP1032/1022
2 diff
2 diff
2 diff
2 diff
16@40MHz
16@40MHz
16@40MHz
16@40MHz
16@40MHz
16@40MHz
2 diff
2 diff
PECL LVTTL
CRCFPGA
Drawer_1
Drawer_1'
RODx_1
RODx_2
Drawer_1
Drawer_1'
RODx_1
RODx_2
Drawer_1
Drawer_1'
RODx_1
RODx_2
2
PU
CON
PU
CON
PU
CON
PU
CON
4@40MHZ
Clock circuit
40MHzcrystal
oscillator
Zero delayClockBuffer
40MHz
TTCrx
P3
(160
pin)
Final prototype OMB 9UFinal prototype OMB 9U
PCB detailsPCB details– Input/output signals Input/output signals
designed for operation designed for operation at 80 MHzat 80 MHz
– 10 copper layers10 copper layersSignal layers between Signal layers between power/gnd planespower/gnd planes
Adjacent layers routed Adjacent layers routed orthogonally for orthogonally for minimum couplingminimum coupling
Final prototype OMB 9UFinal prototype OMB 9U
Signal integrity issuesSignal integrity issues– Big area, not too much populatedBig area, not too much populated
Long distance traces (high coupling)Long distance traces (high coupling)
Clock distributionClock distribution
JTAG chain distributionJTAG chain distribution
VME-CRC FPGA serial busVME-CRC FPGA serial bus
– Different voltage suppliesDifferent voltage supplies+3.3 Volt for FPGA I/O and some logic +3.3 Volt for FPGA I/O and some logic
+1.5 Volt for FPGA cores (island)+1.5 Volt for FPGA cores (island)
+5 Volt for logic+5 Volt for logic
+12 Volt for NIM/TTL conversion (ext. trigger input)+12 Volt for NIM/TTL conversion (ext. trigger input)
Final prototype OMB 9UFinal prototype OMB 9U
Example of SI analysis: VME to CRC Example of SI analysis: VME to CRC serial BUSserial BUS– Connected between the VME FPGA and all Connected between the VME FPGA and all
CRC FPGAsCRC FPGAs– For control, communication, configuration, etc.For control, communication, configuration, etc.– 4 lines: CLK, DATA0, DATA1, DATA2, DATA34 lines: CLK, DATA0, DATA1, DATA2, DATA3– Frequency of operation 40 MHzFrequency of operation 40 MHz
Final prototype OMB 9UFinal prototype OMB 9U
First attemptFirst attempt– Manual placement and Manual placement and
routing of bus linesrouting of bus lines– Keep stubs shortKeep stubs short– Keep same routing layer as Keep same routing layer as
much as possiblemuch as possible– R, RC terminationR, RC termination
ProblemProblem– Characteristic impedance Characteristic impedance
change at T junctionchange at T junction– Reflections at first FPGA Reflections at first FPGA
creates InterSymbol creates InterSymbol Interference (ISI)Interference (ISI)
CRCFPGA VME
CONTROLFPGA
CRCFPGA
CRCFPGA
CRCFPGA
Termination
Final prototype OMB 9UFinal prototype OMB 9U
PostLayout simulationPostLayout simulation
Final prototype OMB 9UFinal prototype OMB 9U
Second attemptSecond attempt– Manual placement and Manual placement and
routing of bus linesrouting of bus lines– Keep stubs shortKeep stubs short– Keep same routing Keep same routing
layer as much as layer as much as possiblepossible
ProblemProblem– Reflections with Reflections with
different termination different termination schemesschemes
CRCFPGA
VMECONTROL
FPGA
CRCFPGA
CRCFPGA
CRCFPGA
Termination
Final prototype OMB 9UFinal prototype OMB 9U
PostLayout simulationPostLayout simulation
Final prototype OMB 9UFinal prototype OMB 9U
Final attemptFinal attempt– Manual placement and Manual placement and
routing of bus linesrouting of bus lines– Keep stubs shortKeep stubs short– Keep same routing Keep same routing
layer as much as layer as much as possiblepossible
SolutionSolution– Resistive termination Resistive termination
at both endsat both ends
CRCFPGA
VMECONTROL
FPGA
CRCFPGA
CRCFPGA
CRCFPGA
Termination
Termination
Final prototype OMB 9UFinal prototype OMB 9U
PostLayout simulationPostLayout simulation
Present statusPresent status
Stratos change connectors to be RoHS Stratos change connectors to be RoHS compliantcompliant– Need to test new connectorsNeed to test new connectors
Board routing on the wayBoard routing on the way– SI analysis still undergoing: JTAG chain, clock SI analysis still undergoing: JTAG chain, clock
distribution and power distributiondistribution and power distribution
FPGA firmware adaptationFPGA firmware adaptation
THANK YOU FOR THANK YOU FOR YOUR YOUR
ATTENTIONATTENTION