Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is...

Notes on Elmore Delay Calculations for Gate

Simple Assumptions: Source/Drain/Gate Capacitance is proportional to gate width. Transistors in series share source/drains.Transistors in parallel do not share source/drains.

If layout was available, actual capacitances would be extracted from layout.

Three-input Nand Gate

Gate Delay: 3-input NAND Driving 4X Inverter

Gate Delay: Worst case TPHL (fall time), TPLH (rise time)

Gate Delay: Best case TPHL (fall time), TPLH (rise time)

Best Case TPLH = R/3*(9C+12C) = R/3 * 21C = 7RC

Best Case TPHL = Worst Case TPHL because all transistors in series.

Compute Elmore Delay for the following gate, best/worst TPLH/TPHL

Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is...

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