Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is...

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Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is proportional to gate width. Transistors in series share source/drains. Transistors in parallel do not share source/drains. If layout was available, actual capacitances would be extracted from layout. Three-input Nand Gate

Transcript of Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is...

Page 1: Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is proportional to gate width. Transistors in series share.

Notes on Elmore Delay Calculations for Gate

Simple Assumptions: Source/Drain/Gate Capacitance is proportional to gate width. Transistors in series share source/drains.Transistors in parallel do not share source/drains.

If layout was available, actual capacitances would be extracted from layout.

Three-input Nand Gate

Page 2: Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is proportional to gate width. Transistors in series share.

Gate Delay: 3-input NAND Driving 4X Inverter

Page 3: Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is proportional to gate width. Transistors in series share.

Gate Delay: Worst case TPHL (fall time), TPLH (rise time)

TPHL

TPLH

Page 4: Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is proportional to gate width. Transistors in series share.

Gate Delay: Best case TPHL (fall time), TPLH (rise time)

Best Case TPLH = R/3*(9C+12C) = R/3 * 21C = 7RC

Best Case TPHL = Worst Case TPHL because all transistors in series.

Page 5: Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is proportional to gate width. Transistors in series share.

Compute Elmore Delay for the following gate, best/worst TPLH/TPHL


6.5.8 Equivalent circuit for the MOSFET. Capacitance The gate capacitance C i is the sum of the distributed capacitance from the gate to the source end.

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