Post on 19-Aug-2020
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Multi-Layer Prototyping: Hardware and Software
Ben Coffin
Software Defined Radio Product Manager
National Instruments
ni.com/5g
NI equips engineers and scientists with systems that
accelerate productivity, innovation, and discovery.
Mission Statement
NI SERVICES AND SUPPORT
NI MODULAR HARDWARE
ONE-PLATFORM APPROACH
Support 700+ Field Engineers
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Open Connectivity10,000+ Instrument and Device Drivers
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9,000+ Code Examples
Partners1,000+ Alliance Partner Companies
Industry-Leading Technology Partners
Academia8,000+ Classrooms Worldwide
TH
IRD
-PA
RT
Y S
OF
TW
AR
ET
HIR
D-P
AR
TY
HA
RD
WA
RE
NI PRODUCTIVE
DEVELOPMENT SOFTWARE
NI E
CO
SY
ST
EM
NI
EC
OS
YS
TE
M
National Instruments Research Focus
Improve bandwidth
utilization through
evolving PHY Level and
flexible numerology
Multi Radio Access
Technologies (RAT)
Utilize potential of
extremely wide bandwidths
at frequency ranges once
thought impractical for
commercial wireless.
mmWave
Dramatically increased
number of antenna elements
on base station enabling
beamforming.
Massive MIMO
Consistent connectivity
meeting the 1000x
traffic demand for 5G
Wireless Networks
▪Densification
▪ SDN
▪ NFV
▪ CRAN
NI Software Defined Radio PlatformConcept to Fully Streaming, Real-Time, Over-the-Air Prototype to Deployment
Hardware Software
Algorithm Design and Validation
PHY layer
Fully Integrated LTE, 802.11, MIMO
Modular, Open, Real-Time IP
MAC layer
ni.com
Hardware
USRP-2974 – Stand-Alone USRP-RIO
Features at a Glance
▪ 10 MHz – 6 GHz frequency range
▪ 160 MHz instantaneous bandwidth per channel
▪ Intel i7 processor with 8GB of RAM
▪ Kintex-7 410T FPGA
▪ GPS Disciplined Clock
▪ 2X2 MIMO
▪ Hardware control over 1G/10G Ethernet
▪ PCIe expansion port to connect to additional USRP RIO
▪ 2U Form Factor
▪ LabVIEW Communications System Design Suite and 802.11
and LTE Application Frameworks support for programming
Real-Time and FPGA
High performance SDR for compute intensive applications
Applications
• Algorithm Engineering
• MAC/PHY Prototyping
• Stand-Alone SDR Applications
• LTE, WiFi, and MIMO Research
• UE Emulation
RIO Heterogenous Architecture
I/O
I/O
I/O
I/O
Processor FPGA
High-Speed Bus
USRP-2974 Block Diagram
Integrated Intel Processor USRP-RIO
Platform
USRP-RIO MotherboardSystem-On-Module
PCIe Int/Ext
options
PCIe Intel
NIC
JTAGUSB Int/Ext
optionsIntel
Quad
Core
i7Inte
l
PC
H-
H
10GbEInt/Ext
options
Daughterboard
160 MHz BW10 MHz – 6 GHz
RF Front
End
Daughterboard
160 MHz BW10 MHz – 6 GHz
RF Front
End
DAC
DAC
ADC
ADC
DAC
DAC
ADC
ADC
Xilinx
Kintex
7
410T
SS
D
USB 3
DDR4
SODIM
M
Display
Port
1G/10G
Ethernet
PCIe
ni.com
Software
Software Defined Radio Architecture
CPU
GPP
FPGA
DSP
D/A
D/A
A/D
A/D
VCO
PLL
VCO
PLL
90
0
90
0
Host ConnectionDetermines Streaming
Bandwidth Ex. Gigabit
E-net, PCIe
Multi-Processor SubsystemReal-time signal processor
• Physical Layer (PHY)
• ex FPGA, DSP
Host processor
• Medium Access Control (MAC)
–Rx/Txcontrol
• ex. Host GPP, multi-core CPU
Baseband
Converters
RF Front End• General Purpose
RF
• Dual LOs
• Contiguous
Frequency Range
Software is the Challenge with Software Defined Radios
• SDR development requires multiple, disparate software tools
• Parallel processing increases system complexity
• Software tools don’t address system integration
Tools
• Math (.m files)
• Simulation (Hybrid)
• User Interface (HTML)
• FPGA (VHDL, Verilog)
• Host Control (C, C++, .NET)
• DSP (Fixed Point C, Assembly)
• H/W Driver (C, Assembly)
• System Debug
• Long learning curves
• Limited reuse
• Need for “specialists”
• Increased costs
• Increased time-to-result
Targets
FPGAsMulticore
Processors
DAC
Clocking
DRAM, SRAM,
EEPROM
Clocking structure
(MMCM’s, constraints)
AD
C/D
AC
In
terf
ace
s
(I/O
Tim
ing
, F
IFO
s)
DM
A a
nd
Re
gis
ters
(I/O
Tim
ing
, F
IFO
s)
DRAM Interface
(I/O Timing, FIFOs)Front End
Configuration
PCI ExpressADC
Dig
ita
l I/
O
IP / Algorithms
Typical FPGA Prototyping Requires Significant System Integration
User Implemented
• 50% of work is system
integration
• Little value in customizing
hardware interfaces
DAC
Clocking
DRAM, SRAM,
EEPROM
Clocking structure
(MMCM’s, constraints)
AD
C/D
AC
In
terf
ace
s
(I/O
Tim
ing
, F
IFO
s)
DM
A a
nd
Re
gis
ters
(I/O
Tim
ing
, F
IFO
s)
DRAM Interface
(I/O Timing, FIFOs)
Front End
Configuration
PCI ExpressADC
Dig
ita
l I/
O
Focus on IP/Algorithms with LabVIEW Communications
LabVIEW Communications
User Implemented
• Hardware interfaces work
out-of-the box
• Focus on algorithms
LabVIEW Communications VHDL
Abstraction to the Pin
USRP-2974 Software Experience
LabVIEW FPGA
LabVIEW Real-Time
Dev Environment/Host
LabVIEW Communications 802.11 Application Framework
Features
▪ SISO configuration
▪ Full bi-directional communication
▪ 20 MHz bandwidth (802.11a)
▪ 20/40 MHz bandwidth (802.11ac)
▪ OFDM modulation and demodulation
▪ QPSK, 16/64/256-QAM
▪ Over-the-air synchronization
▪ Channel encoding and decoding
▪ Lower MAC supports multinode addressing,
CRC and frame type check
▪ Video streaming example
▪ Linux Real-Time operating system
▪ SDR hardware support for USRP RIO and FlexRIO/FAM
Supporting both PHY and MAC Layers
Ready-to-Run, modifiable host and FPGA-based
IEEE 802.11 a/ac PHY and MAC
New Features
• 80 MHz BW (up to MCS 4)
• Lower MAC support
• CSMA/CA
• RTS, CTS, NAV
• Retransmission
• Random backoff
• L1/L2 API
• FPGA simulation mode
Feb
2018
802.11a/ac OFDM Signal Specifications
Parameter 20 MHz (11a) 20 MHz (11ac) 40 MHz (11ac) 80 MHz (11ac)
FFT Size 64 64 128 256
Subcarrier Spacing 312.5 kHz
OFDM Symbol Period 3.2 us
Occupied Subcarriers 52 56 114 242
Data Subcarriers 48 52 108 234
Pilot Subcarriers 4 4 6 8
Null Subcarriers 12 8 14 14
Maximum MCS MCS 7
(64-QAM, ¾)
MCS 8
(256-QAM, ¾)
MCS 9
(256-QAM, 5/6)
MCS 4
(16-QAM, ¾)
IEEE 802.11 Specification: https://standards.ieee.org/findstds/standard/802.11-2016.html
NEW
New
MAC/PHY Separation & Hardware Partitioning
PHY TX• TX frame processing
PHY RX• CCA energy detection
• Synchronization
• RX frame processing
PHY SAP TX PHY SAP RX
DCF Control• Maintains interframe spacing counters
• Controls backoff timers
• Maintains NAV
• Maintains CTS/ACK timeout counters
• Controls transmission rights and timing
• Handles medium state information
MAC RX Middle• Duplicate detection
MAC TX Middle• Assign & maintain sequence
numbers
MAC TX Low• Frame sequence selection
• Retransmission control
• Frame sequence TX control
• MPDU generation
• A-MPDU aggregation
MAC RX Low• MPDU filtering
• MPDU disassembly & FCS
check
• A-MPDU de-aggregation
MAC
PHYFPGA
CPU
ni.com
Multi-layer Prototyping
NI CONFIDENTIAL
Prototype Wireless Networks
RF HW
LTE AFW
PHY/L1
< 6GHz
MIMO AFW
PHY/L1
< 6GHz
5G/NR
PHY/L1
> 6G
5G SC
PHY/L1
> 6G
RF HW
RF HW
RF HW
RF HW
RF HW
RF HW
RF HW
LabVIEW based
MAC/L2
LV L2-L3 API
3rd party L3
3rd party L2
(from customer)
3rd party
protocol
stack
(e.g. NS3)
L1-L2 API
NI’s Vision for Future Wireless Network Prototyping
802.11 AFW
MAC low + PHY
802.11 MAC high
functionality
(LabVIEW)
3rd party
802.11
protocol
stack
(e.g. ns-3)
WiFi
L1-L2 API
Aligned on concepts,
mechanisms, general
structure, …
Cellular / 5G NR
RF HW
LTE L1
< 6GHz
5G NR L1
< 6GHz
5G NRL1
> 6G
3rd party
L1
RF HW RF HW RF HW
LabVIEW based
MAC/L2
LV L2-L3 API
3rd party L3
3rd party L2
(e.g.
proprietary)
3rd party
protocol
stack
(e.g. ns-3,
OAI)
L1-L2 API
RF HW
API
Network Simulator NS-3
✓ Open source (GNU GPLv2) discrete-event network simulator in C++
✓ Allows for simulating IP networks including routing algorithms
✓ Provides various wireless/IP simulation models including LTE, Wi-Fi, ...
Source: www.nsnam.org
NI CONFIDENTIAL
General ns-3 Architecture
NS3 Application
• UDP & TCP server / client
• Echo applications
NS3 Node
NS3 Protocol Handler
• Transport layer / UDP
• Network layer / IP
• Network routing / adressing
NS3 NetDevice
• CSMA (ETH)
• Point2Point
• LTE
• WiFi
• TapBridge
Channel
NI CONFIDENTIAL
ns-3 Wi-Fi NetDevice
NS3 Application
• UDP & TCP server / client
• Echo applications
NS3 Node
NS3 Protocol Handler
• Transport layer / UDP
• Network layer / IP
• Network routing / adressing
NS3 NetDevice
• CSMA (ETH)
• Point2Point
• LTE
• WiFi
• TapBridge
Channel
NI CONFIDENTIAL
Modifications on ns-3 Wi-Fi Module
Wifi NetDevice Architecture (https://www.nsnam.org/docs/release/3.17/models/html/wifi.html)
NS3 Application
• UDP & TCP server / client
• Echo applications
NS3 Node
NS3 Protocol Handler
• Transport layer / UDP
• Network layer / IP
• Network routing / addressing
NS3 NetDevice
• CSMA (ETH)
• Point2Point
• LTE
• Wi-Fi
• TapBridge
ChannelPHY
MAC Low
MAC Middle
MAC High
NI CONFIDENTIAL
Modifications on ns-3 Wi-Fi Module
Separate ns-3 MAC High right here from lower
MAC and PHY functionality
Wifi NetDevice Architecture (https://www.nsnam.org/docs/release/3.17/models/html/wifi.html)
NI CONFIDENTIAL
802.11 AFW
Modifications on ns-3 Wi-Fi Module
NI L1-L2 API
FPGA PHY
Host MAC Low
Enqueue (packet) Receive
via UDP
Functional extension of ns-3 MAC High:
- Generation of messages in certain format that works
for 802.11 AFW
- Enabling UDP based communication with 802.11
AFW Host (Open/Send to/Receive from socket)
ni.com
Applications
S.E.A.
V2X Test
Validation
Texas A&M
Advanced 802.11
MAC Research
Seoul National
University
802.11 MAC for
Efficient BW
Management
University of Notre
Dame
Uplink MU-MIMO
for 802.11ax
How Customers are Leveraging the 802.11 Application Frameworksfor their Success
Trigger fram e
U L M U PPD U
A P
S TA 1
Acknowledge fram e
U L M U PPD US TA 2
U L M U PPD US TA 3
U L M U PPD US TA 4
Frequ
en
cy/
Spa
tia
l d
om
ain
Case Study: 802.11 Network Research
▪ Multi-node 802.11 MAC design test bed
▪ Hardware: USRP-RIO
▪ Software: LabVIEW Communications + 802.11 Application Framework
▪ Challenges
▪ Setup and management
▪ Portability, Code deployment, Cabling
▪ Linux Real-Time requires PXI form factor
Case Study: 802.11 Network Research
▪ Multi-node 802.11 MAC design test bed
▪ Hardware: USRP-RIO
▪ Software: LabVIEW Communications + 802.11 Application Framework
▪ USRP-2974 solution for:
▪ Simplified form factor
▪ Easy system management and maintenance
Host PC
Ethernet
Router
Sta
1Sta
2
Sta
3Sta
4
Sta
5Sta
6
Sta
7Sta
8