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MOSFETs - 1Copyright © by John Wiley & Sons 2003
Power MOSFETs
Lecture Notes
Outline
• Construction of power MOSFETs
• Physical operations of MOSFETs
• Power MOSFET switching Characteristics
• Factors limiting operating specfications of MOSFETs
• COOLMOS
• PSPICE and other simulation models for MOSFETs
MOSFETs - 2Copyright © by John Wiley & Sons 2003
Multi-cell Vertical Diffused Power MOSFET (VDMOS)
N +N +N + N +
N-
N+
PP
gate oxide
gate conductor
field oxide
source conductor
contact to source diffusion
gate width
MOSFETs - 3Copyright © by John Wiley & Sons 2003
Important Structural Features of VDMOS
1. Parasitic BJT. Held in cutoff by body-source short
2. Integral anti-parallel diode. Formed from parasitic BJT.
3. Extension of gate metallization over drain drift region. Field plate and accumulation layer functions.
4. Division of source into many small areas connected electrically in parallel. Maximizes gate width-to-channel length ratio in order to increase gain.
5. Lightly doped drain drift region. Determines blocking voltage rating.
N+
N+N+N+N+
N-
source
drain
gate conductor
gate oxide
field oxidebody-source short
P (body)
(drift region)channel length
iD
parasitic BJT
integral diode
P (body)
MOSFETs - 4Copyright © by John Wiley & Sons 2003
N+
N-
P P
N+ N+
Drain
Source
Gate conductor
Oxide
Integral diode
Parasitic BJT
Channel length
boddy-source short
IDID
Alternative Power MOSFET Geometries
• Trench-gate MOSFET
• Newest geometry. Lowest on-state resistance.
P
N
N+N+
N+
P
iD
drain
gate sourcegate oxide
• V-groove MOSFET.
• First practical power MOSFET.
• Higher on-state resistance.
MOSFETs - 5Copyright © by John Wiley & Sons 2003
MOSFET I-V Characteristics and Circuit Symbols
G
S
D
S
G
D
N-channel MOSFET
P-channel MOSFET
iD
vGSV
GS(th)
actual
linearized
active
ohmic
iD
vDS
BVDSS
VGS1
GS2V
GS3V
GS4V
GS5V
[v - V = v ]GS GS(th) DS
VGS(th)
V <GS
MOSFETs - 6Copyright © by John Wiley & Sons 2003
N
N
P
+
++++++++++ +
VGG1+
depletion layer boundary
ionized acceptors
N
N
P
+
++++++++++ +
VGG2+
depletion layer boundary
ionized acceptors
free electrons
SiO2
SiO2
N
N
P+
++++++++++ +
VGG3+
depletion layer boundary
ionized acceptors
inversion layer with free electrons
SiO2
The Field Effect - Basis of MOSFET Operation
Threshold Voltage V GS(th)
• VGS where strong inversion layer has formed.
Typical values 2- 5 volts in power MOSFETs
• Value determined by several factors1. Type of material used for gate conductor2. Doping density of body region directly
beneath gate3. Impurit ies/ bound charges in oxide
4. Oxide capacitance per unit area Cox = oxtox
tox = oxide thickness
• Adjust threshold voltage during device fabrication via an ion implantation of impurit ies into body region just beneath gate oxide.
MOSFETs - 7Copyright © by John Wiley & Sons 2003
Drift Velocity Saturation
electron drift velocity
electric field1.5x10 V/cm
4
8x10 cm/sec
6
• In MOSFET channel, J = q µn n E
= q n vn ; velocity vn = µn E
• Velocity saturation means that the mobility µn inversely proportional to
electric field E.
• Mobility also decreases because large values of VGS increase free electron
density.
• At larger carrier densities, free carriers collide with each other (carrier-carrier scattering) more often than with lattice andmobility decreases as a result.
• Mobilty decreases, especially via carrier-carrier scattering leead to linear transfer curve in power devices instead of square law transfer curve of logic level MOSFETs.
MOSFETs - 8Copyright © by John Wiley & Sons 2003
N
N
P
+
VGG
+
depletion
N +
VDD1
+
V (x)CS
V (x)ox
x
inversion
ID1
Channel-to-Source Voltage Drop
• VGS = VGG = Vox + VCS(x) ;
VCS(x) = ID1RCS(x)
• Larger x value corresponds be being closer to the drain and to a smaller Vox.
• Smaller Vox corresponds to a smaller
channel thickness. Hence reduction in channel thickness as drain is approached from the source.
MOSFETs - 9Copyright © by John Wiley & Sons 2003
N
N
P
+
VGG
+
depletion
N +
VDD2+
V (x)CS
V (x)ox
x
inversion
ID2
velocity saturation region
Channel Pinch-off at Large Drain Current
• ID2 > ID1 so VCS2(x) > VCS1(x) and thus channel
narrower at an given point.
• Total channel resistance from drain to source increasing and curve of ID vs VDS for a fixed VGSflattens out.
• Apparent dilemma of channel disappearing at drain end for large ID
avoided.
1. Large electric field at drain end oriented parallel to drain current flow. Arises from large current flow in channel constrict ion at drain.
2. This electric field takes over maintenance of minimum inversion layer thickness at drain end.
• Larger gate- source bias VGG postpones flattening
of ID vs VDS until larger
values of drain current are reached.
MOSFETs - 10Copyright © by John Wiley & Sons 2003
MOSFET Switching Models for Buck Converter
DF
RG
VGG
+
Vd
I o
D
S
G
Cgs
Cgd
r DS(on)
I = f(V )D GS
D
G
S
C
C
gs
gd
• Buck converter using power MOSFET.
• MOSFET equivalent circuit valid for off-state (cutoff) and active region operation.
• MOSFET equivalent circuit valid for on-state (triode) region operation.
MOSFETs - 11Copyright © by John Wiley & Sons 2003
MOSFET Capacitances Determining Switching Speed
C gs
Cgd
N
N
N
P
P +
+
+ N
sourcegate
drain
Cds
drain-body depletion layer
Cgd2
C gd1
vDSv = v
GS DS
Cgd
actual
idealization
200 V
• Gate-source capacitance Cgs approximately constant and independent of applied voltages.
• Gate-drain capacitance Cgd varies with applied
voltage. Variation due to growth of depletion layer thickness until inversion layer is formed.
MOSFETs - 12Copyright © by John Wiley & Sons 2003
Internal Capacitances Vs Spec Sheet Capacitances
G D
S
Cgd
gsCdsC
issC
G D
S
issC = gsC + Cgd
ossC
G D
S
Cgd dsCossC = +
MOSFET internal capacitances
Input capacitance
Output capacitance
Reverse transfer or feedback capacitance
Cgd
Cbridge
+ -
rssCBridge balanced (Vb=0) Cbridge = Cgd =
Vb
MOSFETs - 13Copyright © by John Wiley & Sons 2003
iG
G
Cgs C gd2
I o
Vin
VGG
+
RrDS(on)
Turn-on Equivalent Circuits for MOSFET Buck Converter
G
Cgs
C gd1
DF I o
Vin
VGG
+
R
CDC
iG
G
Cgs
C gd1
DF I o
Vin
VGG
+
R
CDC
iG
GCgd1
I o
Vin
VGG
+
R
iG
• Equivalent cir cuitdur ing td(on).
• Equivalent cir cuit dur ing tr i.
• Equivalent cir cuitdur ing tfv1.
• Equivalent cir cuit dur ing tfv2.
MOSFETs - 14Copyright © by John Wiley & Sons 2003
MOSFET-based Buck Converter Turn-on Waveforms
VGS,Io
VGS(th)
VGG+
= R (C + C )gd2 gsG
= R (C + C )gsgd1G
v (t)GS
i (t)G
td(on)
tfv2
tri
t fv1
V in
i (t)D
v (t)DS
I o
t
tVDS(on)
Charge on CgdCharge on C + C
gs gd
• Free-wheeling diode assumed to be ideal. (no reverse recovery current).
MOSFETs - 15Copyright © by John Wiley & Sons 2003
Turn-on Gate Charge Characteristic
Qon =
Vgs,off
(Vt+ID1/gm)
[Cgs(Vgs) + Cgd(Vgs)] Vgs dVgs
Qp =
Vd
Vds,on
Cgd(Vds) Vds dVds
QT = Qon + Qp +
(Vt+ID1/gm)
Vgs,on [Cgs(Vgs) + Cgd(Vgs)] Vgs dVgs
Vd
ID1
Vgs Vds
+
-
+
-
Cgs Cds
Cgd
g (V - V )m gs t
ID1
Vd
Vgs,off gs,onV
Vgs
Vt
V + I /g mt D1
t
t
t
Vds,on
I d
Vds
Qon
VgsVgs,on
Qp
QT1
Qgate
Specified I D1
Vt
I
gmo+
D1
d1V
d3V
Vd2
MOSFETs - 16Copyright © by John Wiley & Sons 2003
Turn-on Waveforms with Non-ideal Free-wheeling Diode
G
C gs
C gd1
Vin
VGG
+
R
iG
I + I o rr
• Equivalent circuit for estimating effect of free-wheeling diode reverse recovery.
tri
I ot rr
I rr
I rr
Ioi (t)DF
i (t)D
t
t
t
VGS(th)
VGS,I
o
t
v (t)DS
Vin
MOSFETs - 17Copyright © by John Wiley & Sons 2003
t
t
i (t)G
v (t)GS
VGG V
GS,Io
= R (C + C )gd2 gsG
= R (C + C )
gd1 gsG1
2
Vin
td(off)
t rv1trv2 t fi
I o
v (t)DS
i (t)D
V GS(th)
MOSFET-based Buck Converter Turn-off Waveforms
• Assume ideal free-wheeling diode.
• Essentially the inverse of the turn- onprocess.
• Model quanitatively using the same equivalent cir cuits as for turn- on. Simply use cor rect dr iving voltages and initial conditions
MOSFETs - 18Copyright © by John Wiley & Sons 2003
• Turn-on of T+ and reverse recovery of Df- will
produce large positive Cgd dvDS
dt in bridge circuit.
• Parasitic BJ T in T- likely to have been in reverse
active mode when Df- was carrying current. Thus
stored charge already in base which will increase
likeyhood of BJ T turn-on when positive Cgd dvDS
dt is
generated.
D
G
S
Cgdparasitic BJT
DF+
T+
T-
I o
DL-
DL+
F-D
dV/dt Limits to Prevent Parasitic BJT Turn-on
N
N
P P
+
+ +N
N
sourcegate
drain
Cgd
• Large positive Cgd dVDS
dtcould turn on parasitic BJ T.
MOSFETs - 19Copyright © by John Wiley & Sons 2003
• VGS(max) = maximum permissible gate-
source voltage.
• If VGS >VGS(max) rupture of gate oxide by
large electr ic fields possible.
• EBD(oxide) 5- 10 million V/ cm
• Gate oxide typically 1000 anstroms thick
• VGS(max) < [5x106] [10- 5] = 50 V
• Typical VGS(max) 20 - 30 V
• Static charge on gate conductor can rupture gate oxide• Handle MOSFETs with care (ground
yourself before handling device)• Place anti- parallel connected Zener diodes
between gate and source as a protective measure
Maximum Gate-Source Voltage
MOSFETs - 20Copyright © by John Wiley & Sons 2003
N+
N+N
+
P P
N
depletion layer boundary without field plate action of gate electrode
depletion layer boundary with field plate action of gate electrode
• BVDSS = drain-source breakdown
voltage with VGS = 0
• Caused by avalanche breakdown of drain-body junction
• Achieve large values by
1.Avoidance of drain-source reach-through by heavy doping of body and light doping of drain drift region
2. Appropriate length of drain drift region
3. Field plate action of gate conductor overlap of drain region
4. Prevent turn-on of parasitic BJ T with body-source short (otherwise BVDSS
= BVCEO instead of BVCBO)
MOSFET Breakdown Voltage
MOSFETs - 21Copyright © by John Wiley & Sons 2003
N
N
PP
+
+
+N
N
source gate
drain
ID
drift region resistance
accumulation layer resistance
channel resistance
drain region resistance
source region resistance
• On-state power dissipation Pon =
Io2 rDS(on)
• Large VGS minimizes accumulation
layer resistance and channelresistance
• rDS(on) dominated by drain drift resistance
for BVDSS > few 100 V
• rDS(on) = Vd ID
3x10-7 BVDSS
2
A
• rDS(on) increases as temperature increases.
Due to decrease in carrier mobility with increasing temperature.
MOSFET On-state Losses
MOSFETs - 22Copyright © by John Wiley & Sons 2003
Rd
G
D
S
Q1
Paralleling of MOSFETs
• MOSFETs can be easily paralleled because of positive temperature coefficient of rDS(on).
• Positive temperature coefficient leads to thermal stabilization effect.
• If rDS(on)1 > rDS(on)2 then more current and thus
higher power dissipation in Q2.
• Temperature of Q2 thus increases more than
temperature of Q1 and rDS(on) values become
equalized.
MOSFETs - 23Copyright © by John Wiley & Sons 2003
DC
10 sec-3
10 sec-4
10 sec-5
IDM
BVDSS
Tj,max
iD
log ( )
v DSlog ( )
MOSFET Safe Operating Area (SOA)
• No distinction between FBSOA and RBSOA. SOAis square.
• FB = forward bias. VGS 0.
• RB = reverse bias.VGS Š 0.
• No second breakdown.
MOSFETs - 24Copyright © by John Wiley & Sons 2003
N+
N+N+N+N+
source
drain
gate conductor
N-
P+
P+
• Conventional vertically oriented power MOSFET
• COOLMOS™ structure (composite buffer structure,super-junction MOSFET, super multi-resurf MOSFET)
• Vertical P and N regions of width b doped at same
density (Na = Nd)
Structural Comparison: VDMOS Versus COOLMOS™
N+
N+N+N+N+
source
drain
gate conductor
N
b
W
b b
Pb P
b
P P
MOSFETs - 25Copyright © by John Wiley & Sons 2003
COOLMOS™ Operation in Blocking State
• COOLMOS™ structure partially depleted.
• Arrows indicate direction of depletion layer growth as device turns off.
• Note n-type drift region and adjacent p-type stripes deplete uniformly along entire vertical length.
• COOLMOS™ structure at edge of full depletion with applied voltage Vc. Depletion layer reaches to middle of vertical P and N regions at b/2.
• Using step junction formalism, Vc = (q b2 Nd)/(4 ) = b Ec,max/2
• Keep Ec,max ≤ EBD/2. ThusNd ≤ ( EBD)/(q b)
N+
N+N+N+N+
source
drain
gate conductor
P
N
+
-
Vc
Ec Ec
Pb
Pb
P
N+
N+N+N+N+
source
drain
gate conductor
PP
N
+
-
V1
PbP
b
MOSFETs - 26Copyright © by John Wiley & Sons 2003
COOLMOS™ Operation in Blocking State (cont.)
• For applied voltages V > Vc, vertically oriented electric field Ev begins to grow in depletion region.
• Ev spatially uniform since space charge compensated for by Ec. Ev ≈ V/W for V >> Vc.
• Doping level Nd in n-type drift region can be much greater than in drift region of conventional VDMOS drift region of similar BVBD capability.
• At breakdown Ev = EBD ≈ 300 kV/cm ; V = BVBD = EBDW
N+
N+N+N+N+
source
drain
gate conductor
P
PN
+
-
Ec Ec
VcV >
V
Ev E vEv
P
PbP
b
MOSFETs - 27Copyright © by John Wiley & Sons 2003
COOLMOS™ Operation in ON-State
• On-state specific resistance ARon [Ω-cm2] much less than comparable VDMOS because of higher drift region doping.
• COOLMOS™ conduction losses much less than comparable VDMOS.
• Ron A = W/(q µnNd) ; Recall that Nd = (EBD)/(q b)
• Breakdown voltage requirements set W = BVBD/ EBD.
• Substituting for W and Nd yields Ron A = (b BVBD)/( µn EBD2)
N+
N+N+N+N+
source
drain
gate conductor
P
N+
-
V1
RLID
Ron Pb
Pb
P
MOSFETs - 28Copyright © by John Wiley & Sons 2003
Ron A Comparison: VDMOS versus COOLMOS™
• COOLMOS at BVBD = 1000 V. Assume b ≈ 10 µm. Use EBD = 300 kV/cm.
• Ron A = (10-3 cm) (1000 V)/[ (9x10-14 F/cm)(12)(1500 cm2 -V-sec)(300 kV/cm)2]
Ron A = 0.014 Ω-cm . Corresponds to Nd = 4x1015 cm-3
• Typical VDMOS, Ron A = 3x10-7 (BVBD)2
• Ron A = 3x10-7 (1000)2 = 0.3 Ω-cm ; Corresponding Nd= 1014 cm3
• Ratio COOLMOS to VDMOS specific resistance = 0.007/0.3 = 0.023 or approximately 1/40
• At BVBD = 600 V, ratio = 1/26.
• Experimentally at BVBD = 600 V, ratio is 1/5.
• For more complete analysis see: Antonio G.M. Strollo and Ettore Napoli, “Optimal ON-Resistance Versus Breakdown Voltage Tradeoff in Superjunction Power Device: A Novel Analytical Model”, IEEE Trans. On Electron Devices,Vol. 48, No. 9, pp 2161-2167, (Sept., 2001)
MOSFETs - 29Copyright © by John Wiley & Sons 2003
COOLMOS™ Switching Behavior
• Larger blocking voltages Vds > depletion voltage Vc, COOLMOS has smaller Cgs, Cgd, and Cds than comparable (same Ron and BVDSS) VDMOS.
• Small blocking voltages Vds < depletion
voltage Vc, COOLMOS has larger Cgs, Cgd,
and Cds than comparable (same Ron and
BVDSS) VDMOS.
• Effect on COOLMOS switching times relative to VDMOS switching times.
• Turn-on delay time - shorter
• Current rise time - shorter
• Voltage fall time1 - shorter
• Voltage fall time2 - longer
• Turn-off delay time - longer
• Voltage rise time1 - longer
• Voltage rise time2 - shorter
• Current fall time - shorter
VGS,Io
VGS(th)
td(on)tfv2
tri tfv1
i (t)D
v (t)DS
Io
t
t
VDS(on)V
d
v (t)GS
t
td(off)trv1
trv2
tfi
• MOSFET witching waveforms for clamped inductive load.
MOSFETs - 30Copyright © by John Wiley & Sons 2003
Bulk
Source
Gate
Drain
RGRDS
RD
RB
RS
Cgs Cbs
Cbd
Cgd
Cgb
Idrain
PSPICE Built-in MOSFET Model
Circuit components
• RG, RDS, RS, RB, and RD = parasiticohmic resistances
• Cgs Cgd, and Cgb = constant voltage-independent capacitors
• Cbs and Cbd = nonlinear voltage-dependent capacitors (depletion layercapacitances)
• Idrain = f(Vgs, Vds) accounts for dccharacteristics of MOSFET
• Model developed for lateral (signal level)MOSFETs
MOSFETs - 31Copyright © by John Wiley & Sons 2003
N+
P
N+
S
G
D
Drain-body depletion layer
Body-source short Cgs Cgd
Cbs
Cbg
Cbd
BSource-body depletion layer
• Cgs, Cbg, Cgd due to electrostatic
capacitance of gate oxide. Independentof applied voltage
• Cbs and Cbd due to depletion layers.
Capacitance varies with junction voltage.
• Body-source short keeps Cbs constant.
• Body-source short puts Cbd between drain and
source.
• Variations in drain-source voltage relativelysmall, so changes in Cbd also relatively small.
• Capacitances relatively independent of terminalvoltages
• Consequently PSPICE MOSFET model hasvoltage-independent capacitances.
Lateral (Signal level) MOSFET
MOSFETs - 32Copyright © by John Wiley & Sons 2003
Cgs
Cgd
N
N
N
PP
+
+
+ N
source gate
draindrain-body depletion layer
Cbd
Cbs
Cbg
Body-sourceshort
• Drain-drift region and large drain-sourcevoltage variations cause large variations indrain-body depletion layer thickness
• Large changes in Cgd with changes in drain-source
voltage. 10 to 100:1 changes in Cgd measured in high
voltage MOSFETs.
• Moderate changes in Cgb and Cbs.
• MOSFET circuit simulation models must take this variation into account.
Vertical Power MOSFET
MOSFETs - 33Copyright © by John Wiley & Sons 2003
10V 20V 30V
0V0
2
4
[nF]SPICE model
Motorola subcircuit model
Cgd
VDS
V = 0GS
MTP3055E
100ns 200ns 300nsTime
40V
20V
60V
0V0s
VDS
SPICE model
Motorola subcircuit model
MTP3055E
• Cgs and Cgd in PSPICE model are
constant independent of terminal voltages
• In vertical power MOSFETs, Cgd varies
substantially with terminal voltages.
• Comparison of transient response of drain-source voltage using PSPICE model andan improved subcircuit model. Bothmodels used in same step-down convertercircuit.
Inadequacies of PSPICE MOSFET Model
MOSFETs - 34Copyright © by John Wiley & Sons 2003
Example of an Improved MOSFET Model
RSOURCE
RGATE
RDRAIN1
RDRAIN2
LDRAIN
LGATE
LSOURCE
DGDCGDMAX
RGDMAX
RDBODYCGS
M1
Drain
Gate
Source
DBODY
• Developed by Motorola for their TMOS line of power MOSFETs
• M1 uses built-in PSPICE models to describedc MOSFET characteristics. Space charge capacitances of intrinsic model set to zero.
• Space charge capacitance of DGD models voltage-dependent gate-drain capacitance.
• CGDMAX insures that gate-drain capacitance does not get unrealistically large at very low drain voltages.
• DBODY models built-in anti-parallel diode inherent in the MOSFET structure.
• CGS models gate-source capacitance of MOSFET. Voltage dependence of this capacitance ignored in this model.
• Resistances and inductances model parasitic components due to packaging.
• Many other models described in literature. Too numerous to list here.
MOSFETs - 35Copyright © by John Wiley & Sons 2003
+-
Drain
Gate
Source
R GL G
R S
Rd
L D
L S
Dsub
M1
M2 M3
V offset Q1
• M2 and M3 are SPICE level 2MOSFETs used along with Voffset to
model voltage dependent behavior ofCgd.
• JFET Q1 and Rd account for voltage drop
in N- drain drift region
• Dsub is built-in SPICE diode model used
to account for parasitic anti-parallel diodein MOSFET structure.
• Reference - "An Accurate Model forPower DMOSFETs Including Inter-electrode Capacitances", Robert Scott,Gerhard A. Frantz, and Jennifer L.Johnson, IEEE Trans. on PowerElectronics, Vol. 6, No. 2, pp. 192-198,(April, 1991)
• LG, RG, LS RS, LD, RD - parasitic
inductances and resistances
• M1= intrinsic SPICE level 2 MOSFET with noparasitic resistances or capacitances.
Another Improved MOSFET Simulation Model