Post on 17-Dec-2015
Mixed Signal Design Space Exploration through Analog Platforms
F. De Bernardinis, P. Nuzzo, A. Sangiovanni Vincentelli
UC Berkeley University of Pisa, Italy
3
Outline
Introduction
Analog Platforms
definition
design flow
Performance Models
definition
optimization of approximation process
Mixed-Signal Case Studypipeline ADC design with platforms
optimization and results
Conclusions
4
Introduction
Mixed-Signal Design:heterogeneous problem to be coped at system level
most remunerative tradeoffs across A/D interface
scant attention in the past
Platform Based Designoriginates as an answer to engineering and economic issues
widely accepted in the design community
moves design focus to composition of library elements
Analog Design Flowslimited synthesis capabilities
struggle with device and circuit complexity
5
Platform Based Design
PBD is a meet-in-the-middle recursive process
Application
Architecture
mappingmappingtools
performancemodels
level l+1
level l
6
Analog Platforms : Definitions
An Analog Platform is a library of components
Platform Component Abstraction:input/output domains
behavioral model
feasible performance model
validity laws
The set of feasible performance models is described as
abstract configuration parameters
0,,, κxyu κφ ,uy
0,,, κxyu
,,,
uuyuy y ,)(,1 κφκ
7
Analog Platforms : Definitions
Example: level 0 OTA
0 is the set of Vin(t)
|Vin| < 100 mV, fmax= 2 MHz
0is the set of MOS sizings
0is the set of internal V and I
0is the set of {Vout(t), gain, IIP3, rout}
0is the solution of device equations
e.g. Spectre simulation
0is obtained from Kirchhoff laws andmaximum device ratings
8
Analog Platforms : Definitions
Example: level 1 OTA1 = 0
1= {x1, x2, x3 }
1is the set of {Vout(t)}
1is given by
1is empty
1is the set {a1, a3, f-3dB, noise, rout}
1 and 0 are strongly relatedin this case, 1 is a simple projection of 0
331 aa thtudBf 3
tnoiseout
tu ty1x 2x
3x
outf noisethtuatuaydB
3
331
9
Analog Platforms : Definitions
Platform InstanceComposition of plat-form components
Defined byh , υ Υ
ξ Ξ, ζ behavioral model composition constraints
0,,, ζξυh
th tυ
1ξ
2ξ
3ξ
4ξ5ξ
6ξ 7ξ
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Analog Platforms : Definitions
Platform InstanceComposition of plat-form components
Defined byh , υ Υ
ξ Ξ, ζ behavioral model composition constraints
Example
0,,, ζξυh
Cap. array+ SwitchOTA
th tυ
FB C
1ξ
2ξ
3ξ
4ξ5ξ
6ξ 7ξ
Sub-DAC
FB Network 010 pFCOTA
load
11
Analog Platforms : Design Flow
Successive refinement/abstraction steps
Bottom-Up phase: define an abstraction ψl that maps l into l+1
ψl has to be conservativeproceed tolower levelswithout iterations
Simulation based performance generation can be conservative
level l+1
level l
lψ
1lψ
*
*
12
Analog Platforms : Design Flow
Successive refinement/abstraction process
Top-down phase: optimization problemcost function (ytop)
application constraints
platform constraints
(ytop) has to be minimizedin
Result:then, propagate down the stack
mapping space
toptop toptopyg 0
toptop ˆopttopy
opttopy
13
Performance Models
Analog Platforms need a general and accurate scheme to represent performance models
exploit a sampling scheme to approximate Image(φy())
use a classifier to generate
uyy y ,imageˆ1 * κφ
W
Ibias
Gain
IIP3
Simulation
14
Performance Models
The approach applies at all platform levelsonly requires of platform instances () and φy()
Support Vector Machine classifiers [DAC03]:
hyperplane classifiers in Hilbert spaces
is a Gaussian RBF kernel is the kernel parameter
i are a set of weights
xi, yi are variable and function values
is a bias term
heuristics to determine #samples and false positives vs. false negatives
i
xxii
ieyxf2
sgn)(
2ixxe
Gain
IIP3
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Refining the Configuration Space
Sampling is exponentially dependent on the size of At platform levels>0 we have
is constrained by
At level 0, configuration spaces consist of physical parameters
κ = {Ibias, Vbias, W1, L1, …}
Circuit functionality limits through:topological constraints
physical constraints
performance constraints
Constraints effectively define
1l
1y
ˆ
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Configuration Constraints
Constraints can be represented asimplicitly define
Constraint relaxationf() cannot be expressed exactly
analytical approximations to device behavior
relax equalities to avoid configuration biasing
has to be estimated bounding analytical expression errors
Configuration sampler in generate random solution to constraint system
0,,
0,,
0,,
0,,
1
11
1
11
mq
m
mp
m
g
g
f
f
κκ
κκ
κκ
κκ
imimi ff εκκκκ ,,ˆ0,, 11
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Analog Constraint Graphs
Exploit bipartite graph representation [Donald]
An ACG is an undirected bipartite graph (, , ), where are the design variables
are equations on design variables
ACGs represent under-constrained systems of equations with a set of inequalities
A scheduling operation can be defined to provide efficient executable samplers in
0
1
2
LVVTGS
DS TGS
VV
L
WkI
M=WM/LMB=WB/LB
0
1
2
LVVTGS
DS TGS
VV
L
WkI
IB
W2L2
VGS2
2
W1 L1
VGS1
1
( )( )
710<size
ˆsize -
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Case Study: Pipeline ADC
AD
C
DA
C
-
AD
C
DA
C
-
AD
C
DA
C
-
AD
C
Digital Correction Logic
80 MS/s, 14 bit pipelined ADC, digitally calibrated, 0.13 m CMOS, STMicroelectronics
Focus on first pipeline stageassume following stages ideal
Mixed signal case study:first stage residue amplifier
digital correction logic
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Level 1 Analog Platform
Generate a Continuous Time Platformis the set of MOS sizings and Ibias
={Vout(t), gain, HD3, noise, SR, f-3dB, Power}
is is a Continuous Time behavioral model
requires Cload to be 32pF
Constraints on [ISCAS05]based on approximate IDS, gm equations
relaxed constraint formulation
constraints on bias current, output range, stability, …
tuβα tanh thtudBf 3
tnoiseout
tu tySR
OTA CTmodel
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Level 1 Analog Platform
Folded Cascode topologydefined similarly to telescopic
same behavioral model
Performance Model Generationexploit custom developed tools
Client approximation process (Windows)
Server simulation process (Linux)
Parameter Num. Sim. Time
Telescopic 16 6 2,134 9h
Folded Cascode 17 6 2,838 12h
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Characterization Results
Performance Ranges
Parameter Telescopic Folded Casc.
Gain 26 920 490 3100
Bandwidth (MHz) 1.5 8.9 0.29 2.7
RMS noise (mV) 1.4 6.2 2.8 29
Power (mW) 38 170 56 180
Slew Rate (V/s) 400 2,400 840 3,800
3D Space projections
Complex tradeoffgainbandwidthnoise
Model Accuracy4% maximum relative error of AP models WRT Spectre
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Level 1 Analog Platform
Platform instance provides a Discrete Time (DT) model for the first pipeline stage
Cap. array+ SwitchOTA
FB C
OTA model spans performance space of 2 topologies
good accuracymaximum error WRT Spectre 5%
24
Level 1 Digital Platform
Digital post-process [Murmann03]:adjust gainlinearize system
Transfer Characteristic Estimationy = a1x+a3x3
Characterization as a componentbounds on accuracy of â1 and â3
simulate the algorithm: (a1, a3) (â1, â3)
(P, a1, a3 , â1, â3)=1
Polynomial Inversioncomputepredictor/corrector implementation schemeperformance model for accuracy: (P, â1, â3)=1
-0.05 0 0.05-0.4
0
0.4
Vin (V)
V res
(V
)
1 1st Stage: LSB = 0.1 V FSR = 0.8 V
AB
3211
3ˆ,ˆ,ˆ,ˆ aaayPx
2
LSB
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Level 1 Digital Platform
1
13P
2
13P
3
13P
4
13P
-0.05 0 0.05-0.4
0
0.4
Vin (V)
V res (V
)
1 1st Stage: LSB = 0.1 V FSR = 0.8 V
AB
PolyInv
PolyEstim
μ1
μ2
x
â1
â3
y
Platform library for digital enhancementsimulation based characterization
performance model(P, a1, a3)=1
Same flow for Analog and Digital
Platforms
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Level 2 Mixed Signal Platform
AD
C
ADC
AD
C
- tVin
GDEC
Cap. array+ SwitchOTA
FB C
1
13P
2
13P
3
13P
4
13P
-0.05 0 0.05-0.4
0
0.4
Vin (V)
V res (V
)
1 1st Stage: LSB = 0.1 V FSR = 0.8 V
AB
PolyInv
PolyEstim
μ1
μ2x
â1
â3
y
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System Optimization
Top-down optimization problem:minimize power consumption given
linearity requirements
minimum SNR
Exploit simulated annealingstochastic global optimizer
efficient behavioral and performance models
dB 84LSB 9LSB
11
to subject
)( )( min
GDECSHA
21
SNR 0. INL 0.7 DNL
yy
INLDNLNP
GDECSHA
outy
ψφθθ
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Results
Optimization performed in 18hbased on simulation of ADC performance
Results
PerformanceOptimal
(Telescopic)Mapped
Folded Cascode
Reference
DNL (LSB) 0.4 0.6 0.44 0.68
INL (LSB) 0.1 0.21 0.15 0.26
SNR (dB) 86.3 86.4 84.3 84.3
PowerSHA (mW) 52.5 52.6 102 146
PowerOTA (mW) 47.7 47.9 97 146
AV0 220 214 1,186 1,492
Bandwidth (MHz) 3.3 3.3 0.79 1.35
Vnoise (mV rms) 2.5 2.61 7.9 8.86
G 7.3 7.27 7.8 7.94
PowerGDEC 4.8 4.8 4.2 -
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Conclusions
A mixed signal design exploration methodology has been presented
Analog platforms have been formally defined
Simulation based performance models have been exploited:conservative approximations of feasible spaces
approximated with SVMs
A challenging ADC design has been presentedanalog and digital platforms
the mixed signal design exploration has been solved with SA
Results demonstrate the effectiveness of the approachautomatic topology selection
power reduced by 64% WRT reference design
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Thanks.