Edited and presented by Alberto Sangiovanni-Vincentelli UC ...Alberto Sangiovanni-Vincentelli UC...

Chess ReviewOctober 4, 2006Alexandria, VA

Edited and presented by

Experimental Research

Alberto Sangiovanni-VincentelliUC Berkeley

ITR Review, Oct. 4, 2006"Experimental Research", ASV 2

Overview

• Experimental research is an essential component of CHESS– Feedback on approach– Inspiration for new theory– Impact

• Wide range– Industrial and Government test cases

• Automotive (safety-critical distributed systems) to be covered in the afternoon (GM, Toyota)

• System-on-Chip (high-complexity platforms; Intel, Infineon, Xilinx)

• Avionics• Wireless Sensor Networks (COMAU, Pirelli)

– Internal experimental test benches• UAVs (complex control, sensor integration)

– New domains:• Hybrid Systems in Systems Biology to be covered in the

afternoon


Overarching Criteria

• An application should exercise – Theory: hybrid models, Models of Computation,

control algorithms– Tools and Environments– Path to implementation

• An application should be relevant for industry or for government agencies


Some Applications Addressed

Automotive

Avionics: UAVs

Networked Embedded Systems

Systems Biology

Automotive


Outline

• Industrial Test Cases– Automotive (safety-critical distributed systems) to be

covered in the afternoon (GM, Toyota)– System-on-Chip (high-complexity platforms; Intel,

Infineon, Xilinx)– Avionics– Wireless Sensor Networks (COMAU, Pirelli)

• Internal experimental test benches– UAVs, – Pursuing-Monitoring (complex control, sensor integration)

• New domains:– Hybrid Systems in Systems Biology to be covered in the

afternoon


Intel MXP5800 Architecture

• Designed for Imaging Applications• Highly Heterogeneous Programmable Platform• Top Level: 8 Image Signal Processors with Mesh


Design Space Exploration

• Replication of scenarios from Intel library

• Accurate Performance Modeling

• Easy implementation of additional scenarios

Cycles for different scenarios

0

500

1000

1500

2000

2500

Hardware Balanced OPE emphasis OPE Heavy

Scenario

Cyc

les

Metropolis ScenariosIntel Software Library

[A. Davare, Q. Zhu, J. Moondanos, ASV, “JPEG Encoding on the MXP5800: A Platform-based Design Case Study,” Proceedings of EstiMedia 2005]

Jens Harnisch, CPR ST

2004 2005 2006 2007 2008 2009

Status today:

GSM/UM

TS

Bluetooth

IrDAFM Radio

+ WiFi 802.11b

+ DVB-T/H

+ WiM

ax+ UWB Wireless USB

+ NFC

+ WiFi 802.11g

+ WiFi 802.11n

+ Bluetooth 2.0

+ GPS

+ Galileo

Cognitive Radio

Trend for Cell Phones

Future Cell Phones are Multi-Standard !Cognitive Radio will be part of multi-standard radios !

What is the optimal architecture ?

Jens Harnisch, CPR ST

Wireless Platform Modeling

functionmodeling

• WCDMA, DVB-H, UWB, • WLAN, WIMAX,• CR

Common Research Agenda:• benchmarks• real-time modeling in f&a • systematic design space exploration• connection between function and architecture model• common rules for modeling • synergy in designing code generators • „Future-proof“ framework for Function&Architecture Modeling

(Matlab, Simulink, Metropolis)

architecture modeling• multiple program- reconfigurable DP+IC fpga-inspired

mable processors architecture architectures

front-end for code generators

back-end back-end back-end


Model-based Design of Software Defined Radio

GME-based SCA Modeling Environment

SCA Comp X

CORE

SCA Comp Y

CORE

Component Model

Hardware (Platform) Model

allocation

allocation

Wrapper Gen

import

PerformanceSimulator

(DES)

PowerSimulator

Design SpaceExploration

SynthesisTools

Open Tool Integration Framework

GME-based SCA Modeling Environment

SCA Comp X

CORECORE

SCA Comp Y

CORECORE

Component Model

Hardware (Platform) Model

allocation

allocation

Wrapper Gen

import

PerformanceSimulator

(DES)

PowerSimulator

Design SpaceExploration

SynthesisTools

Open Tool Integration Framework

Goal:Design and Synthesis of Software Defined Radio (SDR) based on the Software Communications Architecture (SCA)

Used by:BAE Systems for design of SCA SDR applications

•SCA Component Modeling•Interface Adapter modeling and synthesis

•Automatically synthesize component wrappers for Simulink-RTW generated implementations•Performance Simulation of Software Radio applications


Embedded Microprocessor Performance Modeling

• Single Processor Modeling (2003-2005)– Abstract Performance Modeling of XScale

and StrongARM Microarchitectures– A Visual Language for Retargeting the

Microarchitectural Models

• Modeling a Wireless Multiprocessor (2005-?)– Developed High-Level Abstract System

Model of Architecture, Functionality, and a Mapping

– Definition of Levels of Abstraction (next slide)

– Ongoing Development of Performance Backwards Annotation

etropolis

etropolis

http://www.intel.com/index.htm?iid=HPAGE+header_intellogo&


Wireless Multiprocessor Modeling• Modeling Infineon Wireless SDR

Multiprocessor in Metropolis• Key Problems

– Slow Simulation Speed– Little or No

Design Space Exploration• Solution Criteria

– Abstraction(for Speed)

– Performance Annotation (for Accuracy)

ARMARMProcessing Chain 0Processing Chain 0

aProc1

MACMAC

RxSplitterRxSplitter

PhyMergerPhyMerger

Buses

and

Bus Slaves

SIMD0

sProc0_0

sProc0_1SIMD

0sProc0_0

sProc0_1SIMD

0SIMD

0sProc0_0

sProc0_1

SIMD1

sProc1_0

sProc1_1SIMD

1sProc1_0

sProc1_1SIMD

1SIMD

1sProc1_0

sProc1_1

SIMD2

sProc2_0

sProc2_1SIMD

2sProc2_0

sProc2_1SIMD

2SIMD

2sProc2_0

sProc2_1

SIMD3

sProc3_0

sProc3_1SIMD

3sProc3_0

sProc3_1SIMD

3SIMD

3sProc3_0

sProc3_1

Processing Chain 4Processing Chain 4





BusBridge0

BusBridge0

RFInterface1

RFInterface0-1

RFInterface1

RFInterface1

RFInterface0-1

RFInterface0-1

FIRProcess

ARMμP

ARMμP

ARMμP

ARMμP

…

CODECProcess

Turbo/Viterbi

CODECProcessCODECProcess

Turbo/ViterbiTurbo/Viterbi

BusBridge1

BusBridge1

SystemBus 3

SystemBus 3

SIMDCore1SharedMem0-3

SIMDCore1SharedMem0-3SharedMem0-3

ARMScheduler

ARMScheduler

SIMD0 Scheduler

SIMD0 Scheduler

System Bus 5Scheduler


FIRFilterFIR

Filter

Shared Mem0-3Schedulers

Shared Mem0-3Schedulers RF Interface0-1

SchedulersRF Interface0-1

Schedulers

SystemBus 0

SystemBus 0

SIMD3 Scheduler

SIMD3 Scheduler

SystemBus 4

SystemBus 4

SystemBus 5

SystemBus 5

AMBABus0AMBABus0

AMBABus1AMBABus1

…

…

…



ARMProcesses

SIMDCore1SIMD

Core 3

…

SIMD3Processes

SIMDCore1SIMD

Core 3SIMDCore1SIMD

Core 3SIMD

Core 3

…

SIMD3Processes

…

SIMD3Processes

SIMDCore1SIMD

Core 0

…

SIMD0Processes

SIMDCore1SIMD

Core 0SIMDCore1SIMD

Core 0SIMD

Core 0

…

SIMD0Processes

…

SIMD0Processes

Rx_Splitter

Processingchain0

Processingchain5

… PHY Merger

Processingchain1MAC … …

Mapping

Architecture Function


Wireless Multiprocessor Modeling: Levels of Abstraction

Level Speed / Accuracy

Function / Architecture

Algorithmic Excellent / None

Concurrent / None

Annotated Algorithmic

Excellent / OK

Concurrent + Delays / None

Abstract (TLM) Model Good / Poor Concurrent / Timed Resources

Annotated Abstract Model

Good / Good Concurrent + Delays /Timed Resources

Cycle-Level OK / Cycle Level

ASM / SystemC

RTL-level Horrible / Signal Level

ASM / SystemC

Our Focus

Annotations


Recent work (I): Algorithms for mapping applications to chip multiprocessor systems

Application description

Application task graph

Micro-architecture configuration

Task assignmentCommunication

assignmentData layout

Performance analysis on target platform

Application deployment from domain specific languages on to chip multiprocessor systems

FromDevice(0)Discard

ToDevice(0)

FromDevice(1)

FromDevice(2)

FromDevice(3)

Discard

ToDevice(1)

ToDevice(2)

ToDevice(3)

Discard

…

FromDevice(15)

LookupIPRoute

ToDevice(15)

… …

IPVerify DecIPTTL

DiscardDiscard

IPVerifyDecIPTTL

Discard

DiscardIPVerify

DecIPTTL

…

Discard

DecIPTTL

Discard

DecIPTTL

S1

R1 L1 T1

R2 L2 T2

S2

P1 P2

M1

R1 L1 T1

R2 L2 T2

S1 S2

MicroBlaze(soft)

FSL

OPB

PLB

Hardware acceleration

Ethernet

Off-chip SDRAM

On-chip BRAM

PECo-PE PECo-PEMEM MEM

MEM PECo-PEMEM

PERIPHERALMEM

Mapping challenge:

Map parallel tasks in the application to the processors, memories and communication links on the multiprocessor platform

Domain specific language such as Click, Simulink

Intermediate representation of parallel tasks and dependencies

Our approaches for task allocation and resource constrained scheduling:

List scheduling heuristicsConstraint optimization using ILP, SAT


Recent work (II): Exploration tool for FPGA-based soft multiprocessor systems

MicroBlaze soft processor

Pack

et R

ecep

tion

Pack

et

Tran

smis

sion

Lookup TransmitVerify



FSL

BRAM BRAMRS232 Timer

LEDs

Lookup

Lookup

Lookup

Lookup TransmitVerify Lookup

BRAM BRAM

OPB

From0) To(0)

From(1) To(1)

LookupIPRoute

• How do we use reconfigurable platforms?– Conventional approach: HDL onto LUTs– Alternatively, program a multiprocessor

• Craft network of “soft” processors in reconfigurable logic

• Device memory and communication schemes

• Advantages of soft multiprocessors– Combine software productivity and platform

reconfigurability– Open FPGAs to world of software designers

• Experimental study– IPv4 packet forwarding application

• 1.8 Gbps throughput on 16 processor system– Fast extension to Network Address Translation

• Tomahawk– our automated tool for design space exploration

of soft multiprocessor systems

IPv4 Packet Forwarding

Soft Multiprocessor System on an FPGA

Application deployment: Software program on a multiprocessor system


Outline






afternoon


Current projects

• Real time strategies for aircraft conflict resolution

• Mixed initiative control in critical aviation systems– Civil Autoland study

• NSF/NCO National Workshop in Critical Aviation Systems– October 5/6, Alexandria VA


Design and verification of hybrid and embedded systems

1. Model inference2. Offline to online

verification/testing3. Mixed initiative

control4. Online optimization

for competing, distributed entities

5. Embedded software

altitude

headingchange

flight levelchange

velocity


Real time model checking for aircraft collision avoidance


Application to Autoland Interface• Controllable flight envelopes for landing and Take Off / Go

Around (TOGA) maneuvers may not be the same• Pilot’s cockpit display may not contain sufficient information

to distinguish whether TOGA can be initiated

flareflaps extendedminimum thrust

rolloutflaps extendedreverse thrust

slow TOGAflaps extended

maximum thrust

TOGAflaps retracted

maximum thrust

flareflaps extendedminimum thrust

rolloutflaps extendedreverse thrust

TOGAflaps retracted

maximum thrust

revised interface

existing interface

controllable flare envelope

controllable TOGA envelopeintersection


Test bedsTestbed of Autonomous Rotorcraft for Multi-Agent Control– Quadrotor Design– Autonomous Control– Wireless– Full Onboard Sensing

• IMU, GPS, SODAR


Outline






afternoon


Multiple Targets: Pursuing and Monitoring

• Objectives– Developing algorithms for decentralized, coordinated group

pursuit and tracking of moving targets• Decision making of each pursuer

– each pursuer should be able to make decisions on their own• Whether to follow an evader

– Reachability computation : When an evader is in reachable set, a pursuer can reach to the evader with appropriate control even though the evader tries to escape from the pursuer with its best effort

Evader

PursuerReachable set

Begin to follow Ev

x1x2

x3


Reachability computation

• The reachable sets are computed offline using Ian Mitchell’s toolbox of level set method and stored for rapid lookup at run-time

• Reachable set used in simulations – Evader : speed = 2m/s,

maneuvering rate = 0.1rad/s– Pursuer : speed = 1m/s,

maneuvering rate = 1.0rad/s– X1 : longitudinal distance between

an evader and a pursuer– X2 : lateral distance between an

evader and a pursuer– X2 : relative angle between an

evader and a pursuer


Multiple targets/evaders for a pursuer

• One pursuer may have more than two evaders in its reachable sets, i.e. one pursuer is capable of intercepting more than two evaders– Each pursuer uses proximity to decide which

evader to follow

– The above pursuer decides to follow evader1

Evader1

PursuerReachable sets

Evader2

d1

d2


Collision avoidance

• Pursuers in monitoring mode are penalized when they are too close to each other so that they can avoid collision

Pursuer1

Reachable sets

Evader

Pursuer2


Outline






afternoon


Platforms & Design Flow

SNSP

SNAPP

SNIP

ZigBee Bluetooth

MICA TELOS

…

E2E requirements

…

Nodes performance

QoSClass

SelectProtocol Optimize

parametersExecute Service

ApplicationAbstraction Layers Mapping Flow

SelectResources

Serv.1 Serv.2 Serv.3

FlexRand

Invoke Services

RFID

Automatic Real-TimeMapper


Example: Industrial Plants (COMAU)

Monitoring:Vibrations, Temperature, Humidity, Position, Logistics

Control and Actuation:Robot movements, Temperature, Storage

Current solution:Wired Infrastructure

Future solution:WIRELESS

Wireless advantages:Reduce cablingEnhance flexibilityEasy to deploy Higher safety Decreased maintenance costs


Heterogeneous Embedded Systems: Industrial Automation, Building Automation

• Control and Diagnostics of a Manufacturing Cell– deployment of vibration sensors on the robots

• High safety critical standards and security requirements in a harsh environment– interesting design driver for distributed (networked) control (possibly with

wireless sensor/actuator networks)


Wireless Embedded Networks for Ubiquitous Control

Control

PRODUCTIONLINE

PRODUCTUNDER

DEVELOPMENT

ROBOT

PLC

PRODUCTIONLINE

PRODUCTIONLINE

PRODUCTUNDER

DEVELOPMENT

ROBOT

PLC

PRODUCTIONLINE

PRODUCTIONLINE

PRODUCTUNDER

DEVELOPMENT

ROBOT

PLC

PRODUCTIONLINE

HeterogeneousNetwork

Support SNSPSupport Different RF interfacesAbstraction of lower layerReal Time Mapper

Hierarchical SystemRemote access


Outline






afternoon


Antibiotic biosynthesis in Bacillus subtilis(Hu, Wu, Abate, Sastry)

SpaI

signaltransduction

spaK

spaR

spaG

spaE

spaF

spaI

spaS

spaC

spaT

spaB

subtilinprecursor

SpaK

SpaR~p

SpaT

SpaE+SpaG

SpaF

SpaB

SpaC

p

mature subtilin

modificationtransportcleavage

immunitySigH

SigH

spaRK SpaRK SpaSspaSS1 S2

= discrete states (with randomness) = continuous states

modeling with stochastic hybrid systemInput(food)

Output(subtilin)

actual production network


Antibiotic biosynthesis in Bacillus subtilis(Hu, Wu, Abate, Sastry)

• Provided Stochastic Hybrid System Model for the generation of subtilin by B. Subtilis;

• ‘Controlled’ the network through food (input) and observed subtilin evolution (output);

• Analyzed dynamical properties, motivated importance of the ‘hybrid’ and ‘stochastic’ behaviors; proposed biological interpretations;

• Suggested extensions, according to data from Literature in Biology;

• More recently:– Extension of the model; – Investigation of issues of modularity/scalability/data

decentralization in large population environments;– Survival Analysis: use of models from ‘probabilistic safety’ and

arguments from ‘stochastic optimal control’ (see research on SHS by Abate-Amin) to justify evolutionary traits in B. Subtilis.


Planar cell polarity in Drosophila (Claire’s group)

phenotype

cell model proteins feedback network

•Simulations•Parametersestimation

•Study of mutants


Box Invariance for biological reactions systems(Abate, Sastry)

• Concept of “Set Invariance” around the system equilibrium/a• Naturally prone to describe biological systems (modeled via rate equations)• More flexible than classical notion of (Lyapunov) stability• Yields itself to describe robustness properties• Closely related to lots of concepts from linear algebra (Perron-Frobenius theory) and systems theory (practical stability, positive systems, compartmental models)

• Can specify logical conditions for verification purposes (model checking approach)

Claim : most of the stable biological reactionssystems are indeed “box invariant”

Very descriptive concept. Currently extensions are investigated.

In Collaboration with the A. Tiwari

A dynamical system is said to be box invariant if there exist a box-shaped invariance set around its equilibrium point(s)

, SRI International


Box Invariance for biological reactions systems:A simpleExample


Quantitative and Probabilistic Extensions of Pathway Logic (Abate)

Pathway Logic (SRI International): tool for symbolic modeling of biological pathways

based on formal methods and rewriting logic

• Protein functional domains and their interactions

• Queries performed through formal methods• Info exchanged is logic-based

Extensions:1. reasoning with quantitative data2. probabilistic interactions between different domains

In Collaboration with the PL team, SRI International

Results:1. Implemented software trial;2. Exploited ideas from Gillespie’s simulation algorithm and other methods;3. Embedded ideas in PMaude (rewrite-logic standard).

Edited and presented by Alberto Sangiovanni-Vincentelli UC ...Alberto Sangiovanni-Vincentelli UC...

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