Post on 13-Jan-2016
Marc Weber Rutherford Appleton LaboratoryBob Ely, Sergio Zimmermann, Paul Lujan LBNLRong-Shyang Lu Academia Sinica Taiwan
Shielding and Electrical Performance of Silicon Sensor Supermodules
developed for the CDF Run IIb detector upgrade
What is a supermodule ?highly integrated mechanical, electrical and thermal structure;
single-sided silicon strip sensors on top and bottom; 66 cm long; 3072 channels; low mass: 150 g; 1.7% of a radiation length
4-chip hybridssilicon sensors
front side
back side
How to use a supermodule ?
supermodules supported by bulkheads only => minimizes material services at one end only => 1.2 m long 2-barrel construction
Interesting design also for future hadron colliders
Supermodules or staves
BarrelBulkhead
2 barrels with 192 supermodules around beampipe (+ Layer 0)
for CDF Run IIb:
Services
A closer look: schematic side view
“simple” layer structure: SVX4 chip on BeO hybrid on single-sided sensor on bus cable on carbon fiber/foam core
hybrid is wire-bonded to bus cable through 3 mm gap between pairs of sensors
bus cable copper traces stop after reaching 3. hybrid 25/50 μm thick aluminum shields under each sensor pair,
connected to hybrid ground (AG=DG=HG)
top and bottom side nearly symmetric, but typically axial strips on top
and 1.2 stereo strips on bottom
Advantages
compact, light weight, radiation hard components “easy” to build => fast construction, cheap, reliable ideal for assembly: integrated services, modular detector
proximity of sensors and bus cable can cause systematic pedestal shifts (“pick-up”) => “fake hits”, noise occupancy, etc.
CDF runs in deadtime-less mode (data acquisition during “noisy” digitize and readout) to increase trigger bandwidth
requires understanding and suppression of conductive and capacitive interference mechanisms
(see IEEE Trans. Sci., vol. 51, no. 3, pp. 987-993, June 2004)
Challenges
single 18 μm thick copper layer (minimize material)
25 μm or 50 μm thick aluminum shield between copper and silicon sensors
wide power traces; joint digital grounds; etc. to minimize IR drops
Layout of a low-tech component crucial for system performance
Bus cable layout
Electrical Performance
plot shows pedestal of arbitrary channels as a function of time/ chip mode
every channel with “signal” above average pedestal by “2-3” x noise will be read out and used in tracking algorithms
BE_CLK :______________________________COMP_RST:XXXXXXXXXXXXXXXX___________RREF_SEL:XXXXXXXXXXXXXXXXXXX________FE_MODE :87XXXXXXXXXXXXXXXXXXX90XXXFE_CLK :T______T______T______T______T_L1A :XXXXXXXXXXXXXXXXXXXXXXXXXXPRD1 :_____XXXXX________________XXXX
Excellent performance !
but one puzzle remained …
a bucket
bits of a control pattern
Noise: ~2ADC counts/1000 e
Electrical Performance
plot shows pedestal of all channels at arbitrary time (front-side, 25 μm shield, 3 hybrids superimposed)
every channel with “signal” above average pedestal by “2-3” x noise will be read out and used in tracking algorithms
What is this
structure ? ( 50 ADC = 1 MIP)
Pick-up above FE clock line !
Different experimental setups
plot shows pedestal of all channels at an arbitrary time
no pick-up if: 1.2 stereo strips (at supermodule bottom side)
no clock lines
under sensor (at 3. sensor pair)
50 μm thick aluminum shield (final layout)
=> CDF supermodule design OK, but What is the interference mechanism ?
( 50 ADC = 1 MIP)
Transverse supermodule X-section
(strips and clock traces run into slide plane, not to scale !)
layer thicknesses:
Sensor: 320 μmAdhesive: 25 μmKapton: 25 μmAdhesive: 25 μmAluminum: 25/50 μmAdhesive: 25 μmCopper: 18 μmKapton: 25 μm…
Would like to understand width and size of pick-up
CLOCK CLOCK_B
Sensor
p-implants, AC coupling, ~40 μm pitch, every 2. strip is read out
75 μm width/ 100 μm space
front-end clock signal => time-dependent magnetic fields => Eddy currents in aluminum shield => current produces magnetic field seen by the
silicon strips
adjacent strips form loop (through preamplifier ground and interstrip capacitance) => time-dependent magnetic flux perpendicular to loop
leads to emf => net current into preamplifier: “pick-up”
Interference mechanism
L/2
Strip
Strip
Strip
Z axis
X Axis
- L/2
Interstrip capacitance
Calculation of B
Analytical approach
following Smythe: Eddy currents in infinite plane sheet by image method x is coordinate perpendicular to shield and strips; z is coordinate along strips z
Numerical approach
using Maxwell 2D program from Ansoft: decent agreement of results
Various approximations: only 10 Fourier harmonics to parameterize time-
dependence of fields; consider only 19 adjacent strips; use only dominant
pole to describe SVX4 preamp rise times; >10% uncertainty in clock
driver currents; 2D model; ignored carbon fiber at supermodule core; etc.
x
us
iti
xdu
yu
uyee
IB
222
2
Comparison with simulation
data averaged over 180 events, excellent data quality here “extreme” scenario chosen to maximize effect: thin aluminum shield ( 25 μm); max. driver current ( ~20 mA); min. rise time
width and size of simulation ~30% too small (in our approximations) , but
Main effect reproduced by simulation
"Pick-up due to clock lines
-20
-15
-10
-5
0
5
10
15
20
Strip number
AD
C c
ou
nts
Series1
Series2D
Data
Simulation
What influences size of interference ?
Clock driver currents: pick-up proportional to driver current;
reduction by factor 2 for minimum current Aluminum shield thickness (50 μm and 25 μm) : Simulation: reduction by factor ~5 with 50 μm shield Data: no pick-up for thick shield (in standard clock pattern)
Preamp bandwidth/rise times: pick-up reduced with increasing preamp rise time in data and simulation (by > factor 2)
[ Clock frequencies: little variation in data when reducing clock frequency from 50 MHz by factor 4.5 ]
Huge collection of data, so far always consistent with simulation
Given a quantitative model of typical interference effects:
less prototyping needed
can optimize system components ( transceivers, readout chips, bus cable) at early design stages
simple design choices can have big effect:
e.g. small 1.2 angle
between strips and clock traces (rotate strips or rotate traces !)
Summary/Conclusions local pedestal fluctuations in strips above a clock trace observed in prototype
supermodules
Time-dependent magnetic fields, associated with clock signals, induce an emf
in adjacent strips, which leads to a net charge flow into preamp
Numerical and analytical calculations of this effect agree with the data
the fields can be suppressed efficiently by a thin aluminum shield
Quantitative estimate of interference effects possible, gives
superior system design
Electrical performance of CDF Run IIb supermodules is
excellent
Compact packaging can be combined with deadtime-less
operation
Electrical Performance: prototype
plot shows pedestal of arbitrary channel as a function of time/ chip mode
every channel with “signal” above average pedestal by “2-3” x noise will be read out and used in tracking algorithms
BE_CLK :______________________________COMP_RST:XXXXXXXXXXXXXXXX___________RREF_SEL:XXXXXXXXXXXXXXXXXXX________FE_MODE :87XXXXXXXXXXXXXXXXXXX90XXXFE_CLK :T______T______T______T______T_L1A :XXXXXXXXXXXXXXXXXXXXXXXXXXPRD1 :_____XXXXX________________XXXX
Fair performance (if RTPS) , but final design is much better !
a bucket
bits of a control pattern
Interstrip capacitance
L/2
Strip
Strip
Strip
Z axis
X Axis
- L/2