Logical Effort

Section 6.5-6.6.1

Problems:

• P6.2 Compute the oscillation frequency of a seven-stage ring oscillator using 0.18 micron technology. Does the size of the inverters make any difference in the result?

Problem

• P6.4 Determine the self-capacitance at the output assuming step changes at the inputs shown.

Sizing Issues

Proper Formulation of a Delay Problem

Reformulate a Delay Problem

Key Concepts:Intrinsic Time ConstantFanout Ratio

Optimal Sizing of Inverter Chain

Stage Fanout

Delay Versus Fanout

Examples

• Examples 6.8• Examples 6.9

Series of Mixed Gates

Example

• Example 6.10

Derivation of Logic Effort

Obtain Logic Effort of a Gate

• From definition of intrinsic time constant

Determine LE by taking the ratio of Input Capacitances

Determine LE by taking the Delay Ratio

Determine the Parasitic Term

• 2 input-NAND• 2 input-NOR• Subtleties of Table 6.2

NAND2

NMOS in series PMOS in parallel

NAND3

NMOS in series PMOS in parallel

NAND4

NOR2