Lab 1: To generate layout for CMOS Inverter circuit and simulate it for verification.

VLSI Lab

VLSI LABORATORY

FRONT END DESIGN(CAD)

BACK END DESIGN(CAD)

TECHNOLOGY(TCAD)

Proper hardwareProper softwareFoundry or link up with some fab labTest facilityPurpose

DESIGN STEPS

• SCHEMATIC• LAYOUT DESIGN• DRC• LAYOUT Vs SCHEMATIC• PARASITIC EXTRACTION• POST LAYOUT SIMULTION

List of Experiments1. To generate layout for CMOS Inverter circuit and simulate it for verification.2. To prepare layout for given logic function and verify it with simulations.3. Introduction to programmable devices (FPGA, CPLD), Hardware Description

Language (VHDL), and the use programming tool.4. Implementation of basic logic gates and its testing.5. Implementation of adder circuits and its testing.6. Implementation of J-K and D Flip Flops and its testing.7. Implementation 4 to 1 multiplexer and its testing.8. Implementation of 3 to 8 decoder and its testing.9. Implementation of sequential adder and its testing.10. Implementation of BCD counter and its testing.11. Simulation of CMOS Inverter using SPICE for transfer characteristic.12. Simulation and verification of two input CMOS NOR gate using SPICE.13. Introduction to Block Diagram Mathod14. Design of digital Logic using block diagram.

Project

• Mini Project: VHDL/Verilog based mini project with emphasis on design and implementation into the group of maximum 3 students.

Design Abstraction Levels

n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

Microwind

• Microwind is a tool for designing and simulating circuits at layout level. The tool features full editing facilities (copy, cut, past, duplicate, move), various views (MOS characteristics, 2D cross section, 3D process viewer), and an analog simulator

Tools from Microwind

• Microwind• DSCH• Microwind3 Editor• Microwind 2D viewer• Microwind 3D viewer• Microwind analog simulator• Microwind tutorial on MOS devices• View of Silicon Atoms

Getting Microwind

• Go to the websitehttp://www.microwind.net/document

• Download the freeware version of the microwind

• Unzip the files in a Folder

Microwind Downloads

INTRODUCTION THE TOOLUser-friendly and intuitive design tool for educational use.

The student draws the masks of the circuit layout and performs analog simulation

The tool displays the layout in 2D, static 3D and animated 3D

Editing window

One dot on the grid is 5 lambda, or 0.175 µm

Editing icons

Access to simulation

2D, 3D views

Simulation properties

Layout library

Active technology

Palette of layers

Ion current

Voltage cursors

List of model parameters for BSIM4

Memory effect due to source capacitance

Threshold voltage effect

Our Approach1.

2.

3.4.

MOS DEVICETraditional teaching : in-depth

explanation of the potentials, fields, threshold voltage, and eventually the expression of the current Ids

Our approach : step-by-step illustration of the most important relationships between layout and

performance. 1. Design of the MOS2. I/V Simulation3. 2D view4. Time domain analysis

Feature Size

• Chips are specified with set of masks• Minimum dimensions of masks determine transistor

size (and hence speed, cost, and power)• Feature size f = distance between source and drain• Set by minimum width of polysilicon• Feature size improves 30% every 3 years or so• Normalize for feature size when describing design

Rules• E.g. λ = 0.090 μm in 0.180 μm process

Layout design rules:For complex processes, it becomes difficult to understand the intricacies of the fabrication process and interpret different photo masks.They act as interface between the circuit designer and the process engineer.

Editing Icons

Access to Simulation

2D 3D Views

Layout Library

Simulation Properties

Palette of Layers

Active Layers

Current Technology

Work Area

One dot on the grid is 5 lambda or

0.30 µm

Menu Command

Microwind Environment

Design Rules

N- Well

r101 Minimum width 12λr102 Between wells 12 λr110 Minimum well Area 144 λ2

r 102r 101

N - Well

r201 Minimum N+ and P+ diffusion width 4λ

r 201

r 201

N - Well

P+ Diff

N+ Diff

r202 Between two P+ and N+ diffusions 4λ

N - Well

P+ Diff

N+ Diff

r 202

r 202

r203 Extra N-well after P+ diffusion 6λ

N - Well

P+ Diff

N+ Diff

r 203

r 203

r204 Between N+ diffusion and n-well 6 λ

r 204

N - Well

P+ Diff

N+ Diff

r210 Minimum diffusion area 16λ2

r 210

r 210

N - Well

P+ Diff

N+ Diff

r301 Polysilicon Width 2λ

N - Well

P+ Diff

N+ Diff

Polysilicon r 301

r 301

Polysilicon

r302 Polysilicon gate on Diffusion 2λ

N - Well

P+ Diff

N+ Diff

Polysilicon

r 302

r 302

Polysilicon

r307 Extra Polysilicon surrounding Diffusion 3λ

N - Well

P+ Diff

N+ Diff

Polysilicon

r 307

r 307

r 307

r 307

Polysilicon

r304 Between two Polysilicon boxes 3λ

N - Well

P+ Diff

N+ Diff

Polysilicon

Polysilicon

r 304

r 304

r307 Diffusion after Polysilicon 4λ

N - Well

P+ Diff

N+ Diff

Polysilicon

Polysilicon

r 307

r 307

r 307

r 307

r401 Contact width 2λ

Contact

Polysilicon Contact

Metal/Polysilicon Contact

r 401

r404 Extra Poly surrounding contact 1λ

Contact

Polysilicon Contact

Metal/Polysilicon Contact

r 404 r 404

r405 Extra metal surrounding contact 1λ

Contact

Polysilicon Contact

Metal/Polysilicon Contact

r 405 r 405

N - Well

P+ Diff

N+ Diff

Polysilicon

Polysilicon

r403 Extra diffusion surrounding contact 1λ

r 403

r 403

Metal 1

Metal 2

Metal 3

Metal 4

Metal 5

Metal 6

r 501

r 501

r501 Between two Metals 4λ

r510 Minimum Metal area 16λ2

r 510 r 510

r 510r 510

r 510 r 510

Metal 1

Metal 2

Metal 3

Metal 4

Metal 5

Metal 6

Step 1: Select Foundary

Step 2: Select Foundary

Step 3: n+ Diffussion

Step 4: Polysilicon

Step 5: n+diff and Metal Contact

• This Completes nMOS design

• Now go for pMOS Design, and the first need is to construct N Well

Step 6: Create N Well

Step 6: p+ Diffusion

Step 7: Polysilicon

Step 8: Contacts

Final Connections

• pMOS Completed

• Now Interconnection of pMOS and nMOS to complete inverter

• Connect Source of pMOS to VDD and Source of nMOS to VSS.

• Short the Drain of both pMOS and nMOS.

INVERTER: Complete Design

Check DRC

Assign Source

• Assign Signal (Clock) to Gate Terminal

• Add Visible node at Output

Inverter with Source

Run Simulation

VTC Characteristics

Thanks

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