EE141 1

Introduction

Design Rules

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3D Perspective

Polysilicon Aluminum

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Design Rules

Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width

scalable design rules: lambda parameter absolute dimensions (micron rules)

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CMOS Process LayersLayer

Polysilicon

Metal1

Metal2

Contact To Poly

Contact To Diffusion

Via

Well (p,n)

Active Area (n+,p+)

Color Representation

Yellow

Green

Red

Blue

Magenta

Black

Black

Black

Select (p+,n+) Green

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Intra-Layer Design Rules

Metal24

3

10

90

Well

Active3

3

Polysilicon

2

2

Different PotentialSame Potential

Metal13

3

2

Contactor Via

Select

2

or6

2Hole

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Transistor Layout

1

2

5

3

Tra

nsis

tor

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Vias and Contacts

1

2

1

Via

Metal toPoly ContactMetal to

Active Contact

1

2

5

4

3 2

2

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Select Layer

1

3 3

2

2

2

WellSubstrate

Select3

5

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CMOS Inverter Layout

A A’

np-substrate Field

Oxidep+n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A’

A A’

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Layout Editor

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Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.

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Sticks Diagram

1

3

In Out

VDD

GND

Stick diagram of inverter

• Dimensionless layout entities• Only topology is important• Final layout generated by “compaction” program

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Introduction

Packaging

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Bonding Techniques

Lead Frame

Substrate

Die

Pad

Wire Bonding

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Package-to-Board Interconnect

(a) Through-Hole Mounting (b) Surface Mount

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Package Types