Introduction EE1411 Design Rules. EE1412 3D Perspective Polysilicon Aluminum.
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Transcript of Introduction EE1411 Design Rules. EE1412 3D Perspective Polysilicon Aluminum.
EE141 1
Introduction
Design Rules
EE141 2
3D Perspective
Polysilicon Aluminum
EE141 3
Design Rules
Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width
scalable design rules: lambda parameter absolute dimensions (micron rules)
EE141 4
CMOS Process LayersLayer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green
EE141 5
Intra-Layer Design Rules
Metal24
3
10
90
Well
Active3
3
Polysilicon
2
2
Different PotentialSame Potential
Metal13
3
2
Contactor Via
Select
2
or6
2Hole
EE141 6
Transistor Layout
1
2
5
3
Tra
nsis
tor
EE141 7
Vias and Contacts
1
2
1
Via
Metal toPoly ContactMetal to
Active Contact
1
2
5
4
3 2
2
EE141 8
Select Layer
1
3 3
2
2
2
WellSubstrate
Select3
5
EE141 9
CMOS Inverter Layout
A A’
np-substrate Field
Oxidep+n+
In
Out
GND VDD
(a) Layout
(b) Cross-Section along A-A’
A A’
EE141 10
Layout Editor
EE141 11
Design Rule Checker
poly_not_fet to all_diff minimum spacing = 0.14 um.
EE141 12
Sticks Diagram
1
3
In Out
VDD
GND
Stick diagram of inverter
• Dimensionless layout entities• Only topology is important• Final layout generated by “compaction” program
EE141 13
Introduction
Packaging
EE141 14
Bonding Techniques
Lead Frame
Substrate
Die
Pad
Wire Bonding
EE141 15
Package-to-Board Interconnect
(a) Through-Hole Mounting (b) Surface Mount
EE141 16
Package Types
