Input Devices/PowerJeffrey James Valerio

performance per wattIn computing, performance per watt is a measure of the energy efficiency of a particular computer architecture or computer hardware. Literally, it measures the rate of computation that can be delivered by a computer for every watt of power consumed.

System designers building parallel computers, such as Google's hardware, pick CPUs based on their performance per watt of power, because the cost of powering the CPU outweighs the cost of the CPU itself.

FLOPS (Floating Point Operations Per Second) per wattFLOPS (Floating Point Operations Per Second) per watt is a common measure. Like the FLOPS it is based on, the metric is usually applied to scientific computing and simulations involving many floating point calculations.

Instructions per second (IPS) is a measure of a computer's processor speed.The term is commonly used in association with a numeric value such as thousand instructions per second (kIPS), million instructions per second (MIPS), Giga instructions per second (GIPS), or million operations per second (MOPS).

average CPU power (ACP),The average CPU power (ACP), is a scheme to characterize power consumption of new central processing units under "average" daily usage, especially server processors, the rating scheme is defined by Advanced Micro Devices (AMD) for use in its line of processors based on the K10 microarchitecture (Opteron 8300 and 2300 series processors)

thermal design power (TDP),The thermal design power (TDP), sometimes called thermal design point, is the maximum amount of heat generated by the CPU that the cooling system in a computer is required to dissipate in typical operation. Rather than specifying CPU's real power dissipation, TDP serves as the nominal value for designing CPU cooling systems.

CPU power dissipationCentral processing unit power dissipation or CPU power dissipation is the process in which central processing units (CPUs) consume electrical energy, and dissipate this energy both by the action of the switching devices contained in the CPU (such as transistors or vacuum tubes) and by the energy lost in the form of heat due to the impedance of the electronic circuits.

CPU power dissipationThere are several factors contributing to the CPU power consumption; they include dynamic power consumption, short-circuit power consumption, and power loss due to transistor leakage currents:

Pcpu = Pdyn + Psc + Pleak

The dynamic power consumption originates from logic-gate activities in the CPU. When logic gates toggle, energy is flowing as capacities inside the logic gates are charged and discharged. The dynamic power consumed by a CPU is approximately proportional to the CPU frequency, and to the square of the CPU voltage:

P = CV2f

where C is capacitance, f is frequency, and V is voltage.

40 Watt ACP = 60 Watt TDP

55 Watt ACP = 79 Watt TDP

75 Watt ACP = 115 Watt TDP

105 Watt ACP = 137 Watt TDP

Why haven't CPU clock speeds increased in the last 5 years?

Higher performance=better

Narrow pipelining

is easy to speed up

Narrow pipelining

is single threaded with only serial codes.

"Moore's law" is the observation that, over the

history of computing hardware, the number of transistors in a

dense integrated circuit doubles approximately every

two years.

Power Wall

Power Wall

Problems:

Heat (too much of it and too hard to dissipate), power

consumption (too high), and current leakage problems.

Power dissipation in CMOS technology

The first part (addend) of the equation accounts for the dynamic power consumption on the chip (i.e. the

power consumption caused by charging and discharging capacitive loads when transistors are

switched) that represents the useful work performed by the chip. A is the activity factor meaning the

proportion of switching transistors in each cycle (since not all transistors have to switch every clock cycle); C is the capacitive load of the transistor; V is the voltage;

and f is the frequency.

The first part (addend) of the equation accounts for the dynamic power consumption on the chip (i.e. the

power consumption caused by charging and discharging capacitive loads when transistors are

switched) that represents the useful work performed by the chip. A is the activity factor meaning the

proportion of switching transistors in each cycle (since not all transistors have to switch every clock cycle); C is the capacitive load of the transistor; V is the voltage;

and f is the frequency.

If we observe the first term of the equation we can see why power has being increasing only linearly while frequency has been doing it logarithmically. The

reason is the quadratic dependence on the voltage.

Engineers have been able to continuously reduce this voltage from 5V down to below 1V, which has helped them to control dissipated power without losing performance. Unfortunately,

many factors are interdependent and engineers have to make trade-offs constantly. For example, imagine we want to

decrease dynamic power consumption on a chip (consider only first term of the equation) by reducing the supply voltage

initially fixed at 2V. If we are able to reduce it to 1.7V, it is only a 15% decrease in voltage but we get a significant 28% decrease in power. However, reducing supply voltage has a side-effect

on the maximum frequency for the circuit and on the threshold voltage of transistors (the voltage at which a transistor switches

on):

Transistor Scaling

22 nm

Transistor Scaling

The problem is that while transistors are getting smaller, they're NOT getting faster.

The problem is that while transistors are getting smaller, they're NOT getting faster.

Switching speed of transistors depend on the strength of the

electric field.

Strength of the electric field depends on the thickness of

the gate.

As transistors shrink, the area of the gate decreases.

In the past, this means meant that the gate of a transistor could also be made thinner.

"The thinner the separation between two conductive plates, the stronger the electric field is

between them."

As the switching could be faster

transistors could be made thinner without adding load

capacitance.

However, as of 45nm, the gate dielectric is now approximately 0.9nm thick

However, as of 45nm, the gate dielectric is now approximately 0.9nm thick--about the size of a single silicon-dioxide molecule.

It is simply impossible to make this thinner.

Chip Scaling

As transistors get smaller, the wires connecting them get thinner.

Thinner wires mean higher resistance and lower current.

Solution?

Low Power Approaches

1. Clock Gating

Clock-gating inserts a clock-enable before each state

element (register, latch, etc.) such that the element is not

clocked if new data is not going to be written.

Clock-gating inserts a clock-enable

This saves a significant amount of charge/discharge that would be wasted writing the same bit

back to the cell.

2. Power Gating.

This involves putting large, fat transistors at the voltage source for various sections of the chip and powering those sections

off when not used.

T

How much does my laptop consume?

Intel Core 2 Duo 2.0 GHz processor

2 GB RAM

32 GB solid state hard drive

13.3" 1280x800 LED backlit display

NVIDIA GeForce Go 8400M GS video

Windows Vista Ultimate

LCD brightness 7 (max) 20w

LCD brightness 6 19w

LCD brightness 5 18w

LCD brightness 0-4 17w

HDD idle 20w

HDD defragmenting 23w

CPU idle 20w

CPU running one prime95 torture test 50w

CPU running two prime95 torture tests 63w

GPU idle 20w

GPU running rthdribl 55w

GPU running ATITool 3D warmup 40w

DVD idle 20w

DVD spinning with disc inserted 25w

DVD copying 33w

CPU fan off 20w

CPU fan low 21w

CPU fan med/high 22w

CPU fan off 20w

CPU fan low 21w

CPU fan med/high 22w

Tips

1.Don't do anything with 3D graphics (gaming, etc)

2.Avoid using DVDs

3.Turn down the screen brightness 1 or 2 notches

4.Avoid CPU intensive web pages or programs

Intel Core 2 Duo 2.0 GHz processor

2 GB RAM

32 GB solid state hard drive

13.3" 1280x800 LED backlit display

NVIDIA GeForce Go 8400M GS video

Windows Vista Ultimate