INF4420

Switched-Capacitor Circuits

Jørgen Andreas Michaelsen Spring 2014

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Outline

• Introduction (why and how) • Integrators and filters • Gain circuits • Noise and charge injection

Introduction

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Discrete time analog signal processing

Why?

Introduction

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The arrangement of switches and the capacitor approximates a resistor.

Introduction

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Introduction

RC accuracy (matching). Large time constants implies large passive components. With SC the time constant is set by capacitor ratio and clock frequency (both precisely controlled). Spring 2014 Switched-Capacitor Circuits 6

Introduction

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Building blocks

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Integrators

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Discrete integrators

Analyze each clock phase separately

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Discrete integrators

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Discrete integrators

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Discrete time time constant

Discrete integrators

The discrete time equivalent time constant is defined by the capacitor ratio and clock frequency.

• Allows precise time constant definition. • Allows large time constants without excessively

large passive components.

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Integrator parasitic capacitance

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Poorly controlled and non-linear

Parasitic insensitive integrators

Again, we analyze the charge transfer from one clock phase to the next to find the transfer function. Spring 2014 Switched-Capacitor Circuits 15

Critical for performance

Turn off first (bottom plate sampling)

Parasitic insensitive integrators

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Parasitic insensitive integrators

The parasitic capacitors still affect settling, but not the signal charge transfer. Spring 2014 Switched-Capacitor Circuits 17

Delay free integrator

Same circuit as before, but modified clocking of the switches.

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Signal flow graph analysis

• Now we have the fundamental building blocks (discrete time integrators), to realize filters.

• We need a more convenient tool to analyze large systems.

• Signal flow graph (SFG) analysis allows us to graphically analyze SC systems.

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Signal flow graph analysis

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SC filters

A simple design strategy: • Start with a continuous time prototype • Replace resistors with SC resistor equivalents The resulting circuit is similar for input frequencies much lower than the sampling frequency • Use SFG to determine the z-domain transfer

function Accurate description of the transfer function

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First order filters

Filter design example.

Start with the continuous time circuit. In this case:

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First order filters

Replace the resistors with SC elements

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First order filters

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Switch sharing

Some switches are redundant, we use this to simplify the circuit:

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Biquad filters

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Low-Q biquad

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Low-Q biquad

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Low-Q biquad

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High-Q biquad

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High-Q biquad

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Gain

• Resettable gain circuit • Samples offset voltage during reset (reduces

flicker noise)

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Gain

Amplifier slew-rate requirement is high. Spring 2014 Switched-Capacitor Circuits 33

Capacitive-reset gain

Include a capacitor to hold the output during the reset phase. Avoid excessive slewing. Configurable positive or negative gain.

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Noise

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Noise

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Correlated double sampling (CDS)

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Fully differential circuits

Real circuits are almost always fully differential. Coupled noise, power supply noise, substrate noise will mostly affect the common mode, while our signal is in the differential mode. Also, cancels even order harmonics.

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Charge injection

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Bootstrapped switch

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SC amplifier design

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Further reading

Sansen, Analog Design Essentials, Springer, 2006, Ch. 17

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