Importance of the LNA Friis Formula Importance of the LNA Friis Formula Digital Electronics CMOS LNA...

Importance of the LNA

1 ( 1)

111 1 .....

1 .....m

totp p m

NFNFNF NF

Ap A A

Friis’ Formula

1 ( 1)

111 1 .....

1 .....m

totp p m

NFNFNF NF

Ap A A

Friis’ Formula

Digital Electronics CMOS LNA

Low Cost

High Integration

Integration With Digital IC

Larger Parasitic Capisitance

1 ( 1)

111 1 .....

1 .....m

totp p m

NFNFNF NF

Ap A A

Friis’ Formula

Digital Electronics CMOS LNA

Low Cost

High Integration

Integration With Digital IC

Larger Parasitic Capisitance

RF Hexagon

Why Inductive Degenerated LNA?

2-Port Noise Theory

2s n s n

i i Y eF

2-Port Noise Theory

2s n s n

i i Y eF

s u c s n

i i Y Y eF

2-Port Noise Theory

2s n s n

i i Y eF

s u c s n

i i Y Y eF

CMOS small signal equivalent

2-Port Noise Theory

2s n s n

i i Y eF

s u c s n

i i Y Y eF

Thermal Noise Contribution

2-Port Noise Theory

2s n s n

i i Y eF

s u c s n

i i Y Y eF

i i min 1 1

5c gsF Y j C a c

2-Port Noise Theory

2s n s n

i i Y eF

s u c s n

i i Y Y eF

i i min 1 1

5c gsF Y j C a c

X Power Matching

Inductive Degenerated LNA

Bond Wire Inductance

Inductive Source Degeneration

Input Power Matching

Inductive Source Degeneration Small Signal Equivalent

1( ) m s

in g sgs gs

g LZ j L j L

0Re( ( )) sZin R

0Im( ( )) 0Zin Power

Matching

1( ) m s

in g sgs gs

g LZ j L j L

0Re( ( )) sZin R

Matching

m gs s sg C R L

g s s sL Q R L

1( ) m s

in g sgs gs

g LZ j L j L

0Re( ( )) sZin R

Matching

m gs s sg C R L

g s s sL Q R L 1s o gs sQ C R

2 3gs oxC WLC

Definitions

Basic Equation of MOS Drain

n oxD gs t gs t sat

C WI V V V V LE

Definitions

n oxD gs t gs t sat

C WI V V V V LE

sat satv E

od gs tV V V od

1D ox sat sat

pI WLC v E

Definitions

n oxD gs t gs t sat

C WI V V V V LE

sat satv E

od gs tV V V od

1D ox sat sat

pI WLC v E

21 / 2

m ox n odgs

I Wg C V

1D DD D DD ox sat sat

pP V I V WLC v E

Definitions

n oxD gs t gs t sat

C WI V V V V LE

sat satv E

od gs tV V V od

1D ox sat sat

pI WLC v E

21 / 2

m ox n odgs

I Wg C V

( ) 1 ( )s st

2 2 21

( ) (1 ) 25 5 5s s s

Q Q c QQ

pP V I V WLC v E

Definitions

n oxD gs t gs t sat

C WI V V V V LE

sat satv E

od gs tV V V od

1D ox sat sat

pI WLC v E

21 / 2

m ox n odgs

I Wg C V

( ) 1 ( )s st

2 2 21

( ) (1 ) 25 5 5s s s

Q Q c QQ

pP V I V WLC v E

0.395c j1a Long Channel

1a 2 Short Channel

2 / 3 4

4 / 3 150odV mV

Inductive Specified Technique

1st step: Setting the value of Ls

2nd step: Finding the value of ωt.Ls

. /t Ls m gs s sg C R L From Impendance Matching:

3rd step: Finding the optimum Qs

. .( ) 0

s s opt Lss s Q Q

51s opt LsQ

min, . .( ) 1 1.64Ls s opt Lst

4th step: Finding the value of Lg

. .( ) 0

s s opt Lss s Q Q

51s opt LsQ

. . .g Ls s opt Ls s sL Q R L From Impendance Matching:

4th step: Finding the value of Lg

5th step: Finding the optimum Cgs

. .( ) 0

s s opt Lss s Q Q

51s opt LsQ

. . .g Ls s opt Ls s sL Q R L From Impendance Matching:

From Impendance Matching:

1s o gs sQ C R . . . ,1gs opt Ls o s opt Ls sC Q R

6th step: Finding the optimum device’s width Wopt,Ls

2 3gs oxC WLC , . .3 / 2opt Ls o ox s s opt LsW LC R Q

7th step: Finding the optimum device’s transconductance gm.opt.Ls

From Impendance Matching: . . . . /m opt Ls s gs opt Ls Sg R C L

8th step: Finding the optimum ρ and Vod

21 / 2

1m ox n od

Wg C V

1 2 / 3opt Lst satL v

. . . 150od opt Ls opt Ls satV LE mV !

8th step: Finding the optimum ρ and Vod

21 / 2

1m ox n od

Wg C V

1 2 / 3opt Lst satL v

. . . 150od opt Ls opt Ls satV LE mV !

9th step: Finding the current consumption ID.Ls

2. 1D Ls opt ox sat sat opt optI W LC v E

Current Specified Technique

1st step: Setting the current consumption ID

2nd step: Finding the optimum ρ and Vod

1 0.5( ) 3

(1 )sat

( ) 1( )t

( ) ( ) 0opt I

5 31 1 1

opt Io

. . .od opt I opt I satV LE

1 0.5( ) 3

(1 )sat

( ) 1( )t

( ) ( ) 0opt I

5 31 1 1

opt Io

3nd step: Finding the optimum Qs

5 31 1 1

5s opt IQ cc

From 2nd Step:

1 0.5( ) 3

(1 )sat

( ) 1( )t

( ) ( ) 0opt I

5 31 1 1

opt Io

4th step: Finding the optimum device width Wopt,I

5 31 1 1

5s opt IQ cc

From 2nd Step:

From 3rd Step & Impendance Matching: .

2opt Io ox s s opt I

WLC R Q

1 0.5( ) 3

(1 )sat

( ) 1( )t

( ) ( ) 0opt I

5 31 1 1

opt Io

4th step: Finding the optimum device width Wopt,I

5nd step: Finding the value of ωt.I

5 31 1 1

5s opt IQ cc

From 2nd Step:

From 3rd Step & Impendance Matching: .

2opt Io ox s s opt I

WLC R Q

From 2nd Step:

.. . 2

1 0.53

(1 )opt I sat

t I opt Iopt I

6th step: Finding the optimum device transconductance gm.opt.I

From 2nd , 3rd Step & Impendance Matching:

2. . . . . .2 1 / 2 1m opt I opt I ox sat opt I opt I opt Ig W C v

min, ..

( ) 1 1.81I opt It I

min, ..

( ) 1 1.81I opt It I

From 5th , 6th Step : , , , , , ,gs opt I m opt I t opt IC g

min, ..

( ) 1 1.81I opt It I

From 6th , 7th Step & Impendance Matching:

8th step: Finding the optimum Ls

. . . . . .s opt I s gs opt I m opt IL R C g

min, ..

( ) 1 1.81I opt It I

8th step: Finding the optimum Ls

. . . . . .s opt I s gs opt I m opt IL R C g

9th step: Finding the optimum Lg

, , , ,1g I gs opt I s IL C L

Comparison Results

• Inductive Specified Technique

min, 1 1.64Ls ss

Comparison Results

min, 1 1.64Ls ss

0.5 3sL nH

Comparison Results

min, 1 1.64Ls ss

0.5 3sL nH

Parameters:

0.18um process

29.8 /oxC mF m

1.2 / secnv m

55.510 /satE V m

0.5L um

Comparison Results

@ 1.6 GHz Vod=120mVID= 1.7mA

Comparison Results

Vod ≤ 150 mV

Comparison Results

Vod ≤ 150 mV

Comparison Results

Vod ≥ 150 mV

Comparison Results

Vod ≥ 150 mV

Comparison Results

Vod ≥ 150 mV

Comparison Results

Vod ≥ 150 mV

Comparison Results

Vod ≥ 150 mV

Comparison Results

Vod ≥ 150 mV

Comparison Results

Ls = 1.2nH NFmin= 6.1dBID= 0.9mA

Comparison Results

Ls = 1nH NFmin= 5.6dBID= 1.4mA

Comparison Results

Ls = 0.8nH NFmin= 5dBID= 2.2mA

Comparison Results

Ls = 0.6nH NFmin= 4dBID= 4mA

Comparison Results

NFminID

Comparison Results

NFminID

Comparison Results

NFminID

Comparison Results

NFminID IDL LS

Comparison Results

• Current Specified Technique

min,. .

(1 )1 1.81

3 (1 0.5 )opt I

Iopt I opt I sat

Comparison Results

0.25 16DI mA 2

(1 )1 1.81

3 (1 0.5 )opt I

Iopt I opt I sat

0.5 3sL nH

Comparison Results

0.25 16DI mA

Parameters:

0.18um process

29.8 /oxC mF m

1.2 / secnv m

55.510 /satE V m

0.5L um

min,. .

(1 )1 1.81

3 (1 0.5 )opt I

Iopt I opt I sat

0.5 3sL nH

Comparison Results

@ 1.6 GHz Vod=60mVLS=3.1nH

Comparison Results

Vod,opt ≥ 150mV 3nH ≥ LS ≥ 0.5nH

Comparison Results

NFminID

Comparison Results

NFminID

Comparison Results

NFminID IDL LS

Conclusion

Lg Cgs Wopt,Ls gm.opt.Ls ρ ID.Ls

Conclusion

ID p Lg Cgs Wopt,I gm.opt.I LS,opt,I

Conclusion

Same Results for Same Numbers from the two techniques

Conclusion

Noise minimization for different values than those for Power Matching X

Conclusion

Future Work:

Work for Linearity Include all the theory in a toolkit for giving Guidelines

Noise minimization for different values than those for Power Matching X

References

[1] Hashemi, H. and Hajimiri A., “Concurrent multiband low-noise amplifiers-theory, design and applications,” IEEE Trans. Mircrowave theory and techniques,52(1), pp.288–301, 2002.[2] Lee, T.H. The design of CMOS Radio Frequency Integrated Circuits., Cambridge Univ. Press, Cambridge, 1998.[3] Voinigescu, S. P., Maliepaard, M.C., Showell, J.L., Babcock, G.E., Marchesan, D., Schroter, M., Schvan, P. and Harame, D.L. “A scalable high-frequency noise model for bipolar transistors with application optimal transistor sizing for low-noise amplifier design,” IEEE J. Solid-State Circuits,32(9), pp.1430–1439, 1997.[4] Shaeffer, D. K. and Lee, T.H., “A 1.5 V, 1.5 GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits,32(5),745–758,1997.[5] Andreani P. Sjöland H., “Noise optimization of an inductively degenerated CMOS low noise amplifier,” IEEE Trans. Circuits Syst., 48, pp.835–841, Sept. 2001.

Thank you for you attention !

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