Hardware Architecture of Software Defined Radio (SDR)

Tassadaq HussainAssistant Professor: Riphah International University

Research Collaborations: Microsoft Barcelona Supercomputing CenterUniversity of Valenciennes, France (CNRS UMR)

UCERD Pvt Ltd Pakistan

Digital System

What is Software Defined Radio (SDR)

SDR is a general term referring to any radio design that uses a computer and some controlling software to “define” that radio’s operation.

A true SDR has very little hardware and virtually every aspect of its operation is performed by the controlling software.

Software Defined Radio (SDR)

Performs the majority of signal processing in the digital domain using programmable multi-core RISC, GPU, DSPs and hardware accelerator support.

Some signal processing is still done in the analog domain, such as in the RF and IF circuits.

Ideal SDR

The history of SDRThe history of SDR

SPEAKeasy phase I A government program with the following goals: to develop a radio that could function anywhere between

2 Mhz and 2 Ghz:2 Mhz and 2 Ghz: To able to communicate with the radios used by ground

forces as well as air force and naval radios in addition to satellites

To develop a new signal format within 2 weeks with no prior preparation

To use parts and software from multiple contractors at once

SDR: Programming

The ultimate device, where the antenna is connected directly to an A-D/D-A converter and all signal processing is done digitally using fully programmable high speed processor/s.

All functions, modes, applications, etc. can be reconfigured/programmed by the software.

WHY an SDR?

The biggest reason to have an SDR is the flexibility it offers the user. Filtering can easily be changed, depending on the needs Modes of operation can be changed to accommodate new communications technologies All of these functions are controlled in Software, rather than Hardware, making changes simpler (no new filters/hardware demodulators required- the code takes care of it)

Benefits of SDR

Best utilizes the frequency band spectrum Flexible Reduced Obsolescence Enhances Experimentation Brings Analog and Digital World Together Improve Intelligence Quicker time to market

New Breed of Radio

Re-programmable / Reconfigurable Multi-core CPU/GPU/DSP and FPGA Accelerators Multiband/Multimode Networkable Simultaneous voice, data, and video Full convergence of digital networks and radio science.

Block DiagramSoftware Defined Radio

VariableFrequencyOscillator

LocalOscillator

Antenna

BandpassFilter

RF IF Baseband

ADC/DACMulti-core

System

Block DiagramBlock DiagramSoftware Defined RadioSoftware Defined Radio

LocalOscillator(fixed)

Antenna RF IF Baseband

Multi-coreSystem

ADC/DAC

Block DiagramBlock DiagramSoftware RadioSoftware Radio

Antenna RF IF Baseband

Multi-coreSystem

ADC/DAC

Designing an SDR

Antenna

RF

ADC/DAC

Multi-core Processor

High Performance SDR

TR SW(D2)

U1,U2

TR SW(D1)

U4,U5

Synthesizer124.3 to 128.4 MHz

5 kHz Steps

Synthesizer19.680 MHz

TR SW(U11A,U11C)

Q1,U10A

ADC 90o

Arc TangentFM Detector

Sinewave BFO12.5 -17.5 kHz

90o

SW

+ / - AGC

AudioFilters

LMSDenoise

DAC U14

FFT SpectrumAnalyzer

FMSquelch

SSB and CWDetector

Analog Devices EZ-Kit Lite

Speaker

Serial Datato PC

1024 Points

AudioPower Amp

IF Amp

50 dB

ANT orXVRTR

R

T

R

T

143 - 149 MHz

150 MHz

2-PoleLC Filter

Low-PassFilter

40 dB

TransmitRF Amp

ReceiveRF Amp

32 dB143 - 149 MHz 19.665 MHz

FirstMixer(U3)

SecondMixer(U15)

28 kHz

Low-Pass Filter4-PoleCrystal Filter

4-PoleLC Filter

TRSW

(U11B)

U109B,Q5,Q6

IF Driver

TR SW(U12A,U12B)

Microphone

R

T

T

R

R

PTT

CW Key

10 MHzExt. Ref.(Optional)

10-20 kHz

J212

J213

J211

J102

J103

J201

J204

Receiver Second IF10-20 kHz

Conclusions

• Integrates heterogeneous multi-processor cores having RISC, DSP and FPGA architecture that utilize communication system resources efficiently under varying conditions.

• Take advantage of unutilized spectrum. If one application is not using its

spectrum, the hardware can borrow the spectrum until the application starts

using it again.

• Uses wide-band RF transceiver and multi input multi output (MIMO) an-

tennas that adapts to use in a different environment and for multiple appli-

cations.

• A high performance front-end interface having high speed ADC and DAC

which manages high data rate signals.

• Provides C/C++ based programming toolkit to program multi-cores or reprogram hardware accelerators to support the latest communications standards without affecting SDR structure.

• Help to perform future research and development by providing an implementation of many different waveforms for real-time performance analysis.

Looking Ahead

Smart Radios that configure themselves to perform the communications task requested (using different frequency bands, modes, etc.)

Cognitive Radios that learn about their environment (e.g., other users nearby, interference, location, elevation) to optimally configure themselves to maximize efficiency and reduce interference.

Technical Challenges

Reconfigurable RF Hardware

ADC/DAC Speed– Sensor Wall

AI Algorithms