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Logic Design :Verilog FSM in class design example s 1 S. Yoder ND, 2013
CSE 20221: Logic Design
Timers, Frequency Divider Examples
Logic Design :Verilog FSM in class design example s 2 S. Yoder ND, 2013
Timers
• Timer
– time events
– divide clock frequency
– provide delay
• In each case the basic idea is to count clock
pulses
Logic Design :Verilog FSM in class design example s 3 S. Yoder ND, 2013
Verilog Code for Timer
Logic Design :Verilog FSM in class design example s 4 S. Yoder ND, 2013
Verilog Code for Frequency Divider
output reg clkDivOut;
Logic Design :Verilog FSM in class design example s 5 S. Yoder ND, 2013
Design of a Derived Clock
• Design a 1 millisecond clock that is derived from
a 50 MHz system clock.
• Design approach
– Frequency divider
– Divide by 50,000
• Determining size (N) of counter
– given division factor, DF
– N = roundUp(ln DF / ln 2) -1
– Parameter [N:0] countValue;
Logic Design :Verilog FSM in class design example s 6 S. Yoder ND, 2013
Verilog Description
Make sure the size of countValue
is set large enough to represent
the maximum count.
Logic Design :Verilog FSM in class design example s 7 S. Yoder ND, 2013
Test Fixture (See next slide for explanation)
Logic Design :Verilog FSM in class design example s 8 S. Yoder ND, 2013
Testing Circuits With Long Delays
• Testing circuits that require a large number of
clock delays before an event occurs can be done
by modifying the circuit design specifically for
testing.
– In the previous circuit you should check that three
events occur:
• The countValue resets when it equals period – 1
• The clkOut signal = 0 once the countValue resets
• The clkOut signal = 1 when the countValue == halfPeriod
– While testing, set the period to a small value
– In the test fixture insert the line #20 (@posedg clk) as
many times as necessary to see the above events.
9
Finite-State Machines (FSMs)— Alternate Verilog
Model
Logic Design :Verilog FSM in class design example s 9 S. Yoder ND, 2013
`10
Finite-State Machines (FSMs)— Review
• Finite-state machine (FSM)
– State diagram models behavior
– FSM architecture made of:
• State register
• Next State / Output Decoder
– A hardware description language
(HDL) should be capable of
modeling this architecture
– Previously we showed how Verilog
can model an FSM
– Now we will show another approach
of modeling an FSM with Verilog
Inputs: B; Outputs: X
On2 On1 On3
Off
X=1 X=1 X=1
X=0
B’;
B
Next State /
Output Decoder
State register
State
X B
Clk F
SM
inp
uts
FS
M
ou
tpu
ts
next state
Logic Design :Verilog FSM in class design example s 10 S. Yoder ND, 2013
Logic Design :Verilog FSM in class design example s 11 S. Yoder ND, 2013
Define States
off
on1
on2
on3
reset
State Diagram
x = 1
x = 1
x = 1
b
!b
off = 00
on1 = 01
on2 = 10
on3 = 11
12
Definition of States and Declaration of State Registers
module LaserTimer(
input B,
output X,
input Clk, Rst);
// define the states
parameter S_Off = 0, S_On1 = 1,
S_On2 = 2, S_On3 = 3;
//declare present/next state reg
reg [1:0] State, StateNext;
Inputs: B; Outputs: X
On2 On1 On3
Off
X=1 X=1 X=1
X=0
B’
B
next state
decoder
State register
State
X B
Clk
FS
M
inp
uts
FS
M
outp
uts
next state
Logic Design :Verilog FSM in class design example s 12 S. Yoder ND, 2013
13
Next State Decoder Logic
//next state decoder always @(State, B) begin case (State) S_Off: begin if (B == 0) StateNext <= S_Off; else StateNext <= S_On1; end S_On1: begin StateNext <= S_On2; end S_On2: begin StateNext <= S_On3; end S_On3: begin StateNext <= S_Off; end endcase end
Inputs: B; Outputs: X
On2 On1 On3
Off
X=1 X=1 X=1
X=0
B’
B
next state
decoder
State register
State
X B
Clk
FS
M
inp
uts
FS
M
outp
uts
next state
Sensitivity list is composed of the state variables
and all inputs that control branching.
Verilog for Digital Design
Copyright © 2007
Frank Vahid and Roman Lysecky 14
Procedures with Case Statements
• Procedure may use case statement
– Preferred over if-else-if when just one expression determines which statement to execute
– case (expression)
• Execute statement whose case item expression value matches case expression
– case item expression : statement
– statement is commonly a begin-end block, as in example
– First case item expression that matches executes; remaining case items ignored
– If no item matches, nothing executes
– Last item may be "default : statement"
• Statement executes if none of the previous items matched
// CombLogic
always @(State, B) begin
case (State)
S_Off: begin
if (B == 0)
StateNext <= S_Off;
else
StateNext <= S_On1;
end
S_On1: begin
StateNext <= S_On2;
end
S_On2: begin
StateNext <= S_On3;
end
S_On3: begin
StateNext <= S_Off;
end
endcase
assign X = (State != S_Off);
end
15
Clock Controled State Registers
// set next state
always @(posedge Clk) begin
if (Rst == 1 )
State <= S_Off;
else
State <= StateNext;
end
Inputs: B; Outputs: X
On2 On1 On3
Off
X=1 X=1 X=1
X=0
B’
B
next state
decoder
State register
State
X B
Clk
FS
M
inp
uts
FS
M
outp
uts
next state
Logic Design :Verilog FSM in class design example s 15 S. Yoder ND, 2013
Verilog for Digital Design
Copyright © 2007
Frank Vahid and Roman Lysecky 16
When do the state register inputs get updated?
// CombLogic
always @(State, B) begin
case (State)
S_Off: begin
if (B == 0)
StateNext <= S_Off;
else
StateNext <= S_On1;
end
S_On1: begin
StateNext <= S_On2;
end
S_On2: begin
StateNext <= S_On3;
end
S_On3: begin
StateNext <= S_Off;
end
endcase
end
• The state register inputs, i.e., the D inputs to
the flip-flops, must get updated whenever
the present state changes, and whenever an
external input changes.
• The state register outputs get updated
whenever the clock edge occurs
always @(posedge Clk) begin
if (Rst == 1 )
State <= S_Off;
else
State <= StateNext;
end
17
Output Decoder
//output decoder
assign X = State != S_Off;
Inputs: B; Outputs: X
On2 On1 On3
Off
X=1 X=1 X=1
X=0
B’
B
next state
decoder
State register
State
X B
Clk
FS
M
inp
uts
FS
M
outp
uts
next state
Moore machine means the outputs are a
function of only the present state (see next
slide). //output decoder, alternate equation
assign X = (State == S_On1)|
(State == S_On2)|(State == S_On3);
Logic Design :Verilog FSM in class design example s 17 S. Yoder ND, 2013
Moore and Mealy FSM’s
18
Next State
Decoder Logic
Bistable Memory
Devices
Output Decoder
Logic
External
Inputs
External
Outputs
State Outputs
Next State
Decoder Logic
Bistable Memory
Devices
Output Decoder
Logic
External
Inputs
External
Outputs
State Outputs
Next State
Decoder Logic
Bistable Memory
Devices
Output Decoder
Logic
External
Inputs
External
Outputs
State Outputs
Next State
Decoder Logic
Bistable Memory
Devices
Output Decoder
Logic
External
Inputs
External
Outputs
State Outputs
Moore Type Mealy Type
Logic Design :Verilog FSM in class design example s 18 S. Yoder ND, 2013
19
Complete Verilog Model of FSM
module LaserTimer(
input B,
output X,
input Clk, Rst);
// define the states
parameter S_Off = 0, S_On1 = 1,
S_On2 = 2, S_On3 = 3;
//declare present/next state reg
reg [1:0] State, StateNext;
// CombLogic
//next state decoder
always @(State, B) begin
case (State)
S_Off: begin
if (B == 0)
StateNext <= S_Off;
else
StateNext <= S_On1;
end
S_On1: begin
StateNext <= S_On2;
end
S_On2: begin
StateNext <= S_On3;
end
S_On3: begin
StateNext <= S_Off;
end
endcase
end
// set next state
always @(posedge Clk) begin
if (Rst == 1 )
State <= S_Off;
else
State <= StateNext;
end
//output decoder
assign X = (State != S_Off);
endmodule
Inputs: B; Outputs: X
On2 On1 On3
Off
X=1 X=1 X=1
X=0
B’
B
next state
decoder
State register
State
X B
Clk
FS
M
inp
uts
FS
M
outp
uts
next state
Logic Design :Verilog FSM in class design example s 19 S. Yoder ND, 2013
20
Link Between State Diagram and Verilog Model
reg [1:0] State, StateNext;
// CombLogic
always @(State, B) begin
case (State)
S_Off: begin
if (B == 0)
StateNext <= S_Off;
else
StateNext <= S_On1;
end
S_On1: begin
StateNext <= S_On2;
end
S_On2: begin
StateNext <= S_On3;
end
S_On3: begin
StateNext <= S_Off;
end
endcase
assign X = (State != S_Off);
end
On2 On1 On3
Off
X=1 X=1 X=1
X=0
B'
B
parameter S_Off = 0, S_On1 = 1,
S_On2 = 2, S_On3 = 3;
Logic Design :Verilog FSM in class design example s 20 S. Yoder ND, 2013
Logic Design :Verilog FSM in class design example s 21 S. Yoder ND, 2013
FSM Testbench
//continued from left column
initial begin
B = 0;
reset = 1;
#100;
@ (negedge clk) reset = 0;
@ (negedge clk) B = 1;
#20;
@ (negedge clk) B = 0;
#20;
@ (negedge clk) #20;
@ (negedge clk) #20;
@ (negedge clk) #20;
@ (negedge clk) #20;
@ (negedge clk) #20;
end
endmodule
module testbench;
// Inputs
reg B;
reg clk;
reg reset;
// Outputs
wire X;
wire [1:0] presentState;
// Instantiate the Unit
);always begin
clk = 0;
#50;
clk = 1;
#50;
end
Logic Design :Verilog FSM in class design example s 22 S. Yoder ND, 2013
Simulation Verification
Verilog for Digital Design
Copyright © 2007
Frank Vahid and Roman Lysecky 23
Self-Checking Testbench (optional)
// Vector Procedure
initial begin
Rst_s <= 1;
B_s <= 0;
@(posedge Clk_s);
#5 if (X_s != 0)
$display("%t: Reset failed", $time);
Rst_s <= 0;
@(posedge Clk_s);
#5 B_s <= 1;
@(posedge Clk_s);
#5 B_s <= 0;
if (X_s != 1)
$display("%t: First X=1 failed", $time);
@(posedge Clk_s);
#5 if (X_s != 1)
$display("%t: Second X=1 failed", $time);
@(posedge Clk_s);
#5 if (X_s != 1)
$display("%t: Third X=1 failed", $time);
@(posedge Clk_s);
#5 if (X_s != 0)
$display("%t: Final X=0 failed", $time);
end
B_s
X_s
time (ns)
10 20 30 40
Clk_s
50 70
Rst_s
60 80 90 110 100
• Reading waveforms is error-prone
• Create self-checking testbench
– Use if statements to check for expected values
• If a check fails, print error message
• Ex: if X_s fell to 0 one cycle too early, simulation might output:
– 95: Third X=1 failed
Verilog for Digital Design
Copyright © 2007
Frank Vahid and Roman Lysecky 24
Simulation $Display System Procedure (optional)
// Vector Procedure
initial begin
Rst_s <= 1;
B_s <= 0;
@(posedge Clk_s);
#5 if (X_s != 0)
$display("%t: Reset failed", $time);
Rst_s <= 0;
@(posedge Clk_s);
#5 B_s <= 1;
@(posedge Clk_s);
#5 B_s <= 0;
if (X_s != 1)
$display("%t: First X=1 failed", $time);
@(posedge Clk_s);
#5 if (X_s != 1)
$display("%t: Second X=1 failed", $time);
@(posedge Clk_s);
#5 if (X_s != 1)
$display("%t: Third X=1 failed", $time);
@(posedge Clk_s);
#5 if (X_s != 0)
$display("%t: Final X=0 failed", $time);
end
• $display – built-in Verilog system procedure for printing information to display during simulation – A system procedure interacts with the
simulator and/or host computer system • To write to a display, read a file, get the
current simulation time, etc.
• Starts with $ to distinguish from regular procedures
• String argument is printed literally... – $display("Hello") will print "Hello"
– Automatically adds newline character
• ...except when special sequences appear – %t: Display a time expression
– Time expression must be next argument • $time – Built-in system procedure that
returns the current simulation time – 95: Third X=1 failed
25