Post on 04-Apr-2018
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FPGA System Design with
Verilog
A Workshop Prepared for
Rose-Hulman VenturesEd Doering
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Workshop Goals
Gain familiarity with FPGA devices
Gain familiarity with HDL design methods
Implement basic designs in hardware
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Agenda
FPGA Overview 8:30 - 9:15
Verilog Overview 9:15 - 10:00
Combinational Circuits 10:15 - 11:00
Lab Projects I 11:00 - 12:00
Sequential Circuits 1:15 - 2:00
Lab Projects II 2:00 - 3:00
Lab Projects III 3:15 - 4:00
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FPGA Overview
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What is an FPGA?
Field Programmable Gate Array
Blank slate for your digital hardware system
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FPGA in Context
Microprocessor/microcontroller
Executes a program
Fixed hardware and interconnections
Full-custom IC
Design at the transistor level
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FPGA in Context
Semicustom IC
Standard cell (CBIC, ASIC)
Masked gate array (MGA)
Programmable logic device (PLD)
PLD
Complex PLD (CPLD)
FPGA
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When to Use an FPGA
Design economics
Shortest time to market
Lowest NRE cost
Highest unit cost
Make quick grab for market share, then do
cost reduction with ASICs
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FPGA Pictures
Board
Packages
Wafer
Die photos
FPGA
Pentium II microprocessor
Sources: http://www.xilinx.com/company/press/products/pictures2.htm,
http://micro.magnet.fsu.edu/chipshots/pentium/
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Internal Architecture
Array of Configurable Logic Blocks (CLBs)
User-defined (SRAM-based) interconnect
between CLBs
Dedicated resources
Power distribution
Clock distribution
Programmable I/O blocks (IOBs)
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Configurable Logic Block
Source: Smith, M.J.S., Application-Specific Integrated Circuits,Addison-Wesley, 1997.
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Programmable I/O Block
Source: Smith, M.J.S., Application-Specific Integrated Circuits, ddison-Wesley, 1997.
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Total 1999 PLD Market = $2.6B
Xilinx
35%
Altera
33%
Lattice
16%
Actel
7%
Other
9%
PLD Vendors
Source: Xilinx University Program Workshop Notes
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Xilinx FPGA Product Families
Virtex-II(Platform FPGA, 10M gates)
Virtex (1M gates), Virtex-E (3M gates)
Spartan (low cost ASIC replacement)
XC4000 (first FPGA family, now with
enhancements)
http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?BV_SessionID=@@@@1880845381.0997107580@@@@&BV_EngineID=cccfaclmjfdejllcflgcefndfgldfmi.0&ioid=-8265&isoid=-8901&ipoid=37189&itype=2&iLanguageID=1&iCountryID=1&sSecondaryNavPick=Devices&sGlobalNavPick=PRODhttp://www.xilinx.com/xlnx/xil_prodcat_product.jsp?BV_SessionID=@@@@1880845381.0997107580@@@@&BV_EngineID=cccfaclmjfdejllcflgcefndfgldfmi.0&ioid=-8265&isoid=-8267&ipoid=36996&itype=2&iLanguageID=1&iCountryID=1&sSecondaryNavPick=Devices&sGlobalNavPick=PRODhttp://www.xilinx.com/xlnx/xil_prodcat_product.jsp?BV_SessionID=@@@@1880845381.0997107580@@@@&BV_EngineID=cccfaclmjfdejllcflgcefndfgldfmi.0&ioid=-8265&isoid=-8604&ipoid=19008&itype=2&iLanguageID=1&iCountryID=1&sSecondaryNavPick=Devices&sGlobalNavPick=PRODhttp://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?BV_SessionID=@@@@1880845381.0997107580@@@@&BV_EngineID=cccfaclmjfdejllcflgcefndfgldfmi.0&ioid=-8265&isoid=-8603&itype=2&iLanguageID=1&iCountryID=1&sSecondaryNavPick=Devices&sGlobalNavPick=PRODUCTShttp://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?BV_SessionID=@@@@1880845381.0997107580@@@@&BV_EngineID=cccfaclmjfdejllcflgcefndfgldfmi.0&ioid=-8265&isoid=-8603&itype=2&iLanguageID=1&iCountryID=1&sSecondaryNavPick=Devices&sGlobalNavPick=PRODUCTShttp://www.xilinx.com/xlnx/xil_prodcat_product.jsp?BV_SessionID=@@@@1880845381.0997107580@@@@&BV_EngineID=cccfaclmjfdejllcflgcefndfgldfmi.0&ioid=-8265&isoid=-8604&ipoid=19008&itype=2&iLanguageID=1&iCountryID=1&sSecondaryNavPick=Devices&sGlobalNavPick=PRODhttp://www.xilinx.com/xlnx/xil_prodcat_product.jsp?BV_SessionID=@@@@1880845381.0997107580@@@@&BV_EngineID=cccfaclmjfdejllcflgcefndfgldfmi.0&ioid=-8265&isoid=-8267&ipoid=36996&itype=2&iLanguageID=1&iCountryID=1&sSecondaryNavPick=Devices&sGlobalNavPick=PRODhttp://www.xilinx.com/xlnx/xil_prodcat_product.jsp?BV_SessionID=@@@@1880845381.0997107580@@@@&BV_EngineID=cccfaclmjfdejllcflgcefndfgldfmi.0&ioid=-8265&isoid=-8901&ipoid=37189&itype=2&iLanguageID=1&iCountryID=1&sSecondaryNavPick=Devices&sGlobalNavPick=PRODhttp://www.xilinx.com/xlnx/xil_prodcat_product.jsp?BV_SessionID=@@@@1880845381.0997107580@@@@&BV_EngineID=cccfaclmjfdejllcflgcefndfgldfmi.0&ioid=-8265&isoid=-8901&ipoid=37189&itype=2&iLanguageID=1&iCountryID=1&sSecondaryNavPick=Devices&sGlobalNavPick=PRODhttp://www.xilinx.com/xlnx/xil_prodcat_product.jsp?BV_SessionID=@@@@1880845381.0997107580@@@@&BV_EngineID=cccfaclmjfdejllcflgcefndfgldfmi.0&ioid=-8265&isoid=-8901&ipoid=37189&itype=2&iLanguageID=1&iCountryID=1&sSecondaryNavPick=Devices&sGlobalNavPick=PROD7/29/2019 FPGA System Design With Verilog
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Altera FPGA Product Families
APEX-II (up to 7M gates)
APEX20K(up to 1.5M gates)
Mercury (ASIC replacement, ASSP)
FLEX 10K
http://www.altera.com/products/devices/apex2/ap2-overview.htmlhttp://www.altera.com/products/devices/apex/apx-overview.htmlhttp://www.altera.com/products/devices/mercury/mcy-overview.htmlhttp://www.altera.com/products/devices/flex10k/f10-overview.htmlhttp://www.altera.com/products/devices/flex10k/f10-overview.htmlhttp://www.altera.com/products/devices/mercury/mcy-overview.htmlhttp://www.altera.com/products/devices/apex/apx-overview.htmlhttp://www.altera.com/products/devices/apex2/ap2-overview.htmlhttp://www.altera.com/products/devices/apex2/ap2-overview.htmlhttp://www.altera.com/products/devices/apex2/ap2-overview.html7/29/2019 FPGA System Design With Verilog
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Hybrid FPGA / Microcontroller
Triscend E5 CSoC (configurable system-
on-chip)
8-bit 8051-based microcontroller
40K system gates
Triscend A7 CSoC
32-bit ARM7TDMI processor
40K system gates
http://www.triscend.com/products/indexe5.htmlhttp://www.triscend.com/products/indexA7.htmlhttp://www.triscend.com/products/indexA7.htmlhttp://www.triscend.com/products/indexe5.html7/29/2019 FPGA System Design With Verilog
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Hybrid FPGA / Microcontroller
Atmel FPSLIC (Field Programmable
System-Level Integrated Circuit)
5K to 40K system FPGA gates
8-bit AVR RISC microprocessor core
Microcontroller peripherals
36K program and data RAM
http://www.atmel.com/atmel/products/prod39.htmhttp://www.atmel.com/atmel/products/prod39.htm7/29/2019 FPGA System Design With Verilog
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Choosing CPLD or FPGA
CPLD
Nonvolatile (ROM- or EEPROM-based)
Predictable delays (no routing) Register poor (relatively few FFs)
Low-to-medium density
For simple, fast logic with many inputs Specialized decoders, combinational circuits,
counters
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Choosing CPLD or FPGA
FPGA
Volatile (SRAM-based)
Configuration must be stored externally(serial EEPROM)
Permits field upgrades, reconfigurablecomputing
Variable routing delays Register rich (relatively many FFs)
For arbitrary digital systems, system-on-chip(SoC), medium-to-high density
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Verilog Overview
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Hardware Description Languages
Verilog
Gateway DesignAutomation (1983;
proprietary)
Acquired byCadence 1989
IEEE standard in1995
Similar to C
VHDL
Origins in DoD
VHSIC program(1980s)
IEEE standard in
1987
Similar to ADA
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Verilog vs. VHDL
Verilog is less wordy
Industry is about 50%-50%
VHDL more common in adademe
I think Verilog is easier to learn
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What is HDL?
HDL = Hardware Description Language
A text-based method for describing
hardware to asynthesis tool
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HDL Advantages Over
Schematic Entry Produce correct designs in less time
Produce larger and more complex systems
per unit time
Shifts focus to specifying functionality
Synthesis tools automate details of
connecting gates and devices
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Design Flow Comparison
Schematic
Netlist
Gate-Level
Simulation
Implement
Hardware
Synthesis
Text
HDL Sim
Netlist
Implement
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Key Advantages of HDL-Based
Design Methodology Operate at higher level of abstraction
Can debug earlier (behavioral simulator)
Parameterized design, easy to make
wholesale modifications to a design (e.g.,
bus width)
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Key Advantages of HDL-Based
Design Methodology Can quickly specify desired behavior
Example: Up-counter with reset
if (reset == 1)
count
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Key Advantages of HDL-Based
Design Methodology Can easily target multiple devices (eases
product migration)
HDL
FPGA ASIC
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Key Advantages of HDL-Based
Design Methodology HDL is more universal than schematic tools
Promotes design reuse
Promotes integration of third party designs,
orIP(intellectual property)
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What HDL is NOT
HDL is not a programming language
(HDL is a description language)
HDL is not highly abstract, e.g., implement
the DSP algorithmy(n) = 0.75y(n-1) +
0.3x(n)(HDL is at the RTL level (register transfer))
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Synthesizable Subset
Verilog (and VHDL) began life as
simulation and modelingtools
Hardware synthesis developed during the1990s
Need to use a subset of Verilog and specific
coding styles to allow synthesis tool to infercorrect (and realizable) hardware
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Synthesizable Subset
Synthesizable
Verilog
Verilog
Use this to writetestbenches for
behavioral simulation
Use this to
make hardware
in FPGA
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Most Likely Learning Hurdle
May try to write HDL code as if it will
eventually be executed by some
mysterious processor device in the FPGA Code is written sequentially (like a
program), but you are simply writing
descriptions of the various hardware entitiesin your system
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Verilog:
Combinational
Circuits
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A Gradual Introduction
New concepts in boldface
Verilog keywords in italic
Refer to your handout...
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Do Nothing Circuit
module Gadget;
endmodule
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Do Nothing with I/O
module Gadget (a,b,c);// Port modes
input a,b;output c;
endmodule
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NAND Gate: Continuous
Assignmentmodule Gadget (a,b,c);
/* Port modes */
input a,b;
output c;
// Functionalityassign c = ~(a & b);
endmodule
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Bitwise Operators
~ NOT
& AND
| OR
^ EXOR
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NAND Gate: Procedural
Assignmentmodule Gadget (a,b,c);
// Port modes
input a,b;
output c;
// Registered identifiersregc;
// Functionalityalways @ (a or b)
c
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Two Gates
module Gadget (a,b,c,d);
// Port modesinput a,b;
output c;output d;
// Registered identifiersregc,d;
// Functionalityalways @ (a or b) begin
c
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Two-Input MUX
moduleMux2 (A, // A inputB, // B inputSel, // SelectorY // Output
);
// Port modesinput A,B,Sel;output Y;
// Registered identifiersregY;
// Functionalityalways @ (A or B or Sel)
if(Sel==0)Y
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Relational Operators
== Equal to
!= Not equal< Less than> Greater than
= Greater than or equal&& AND|| OR
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More Operators
>> Shift right
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MUX Again...
// Functionalityalways @ (A or B or Sel)
if(Sel)Y
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... and Again!
// Functionalityalways @ (A or B or Sel)
Y
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4-Input MUX
module Mux4 (Data, // Data inputSel, // SelectorY // Output
);
// Port modesinput
[3:0] Data;input [1:0] Sel;output Y;
// Registered identifiersregY;
// Functionalityalways @ (Data or Sel)
if(Sel == 0)
Y
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4-Input MUX Using case
// Functionalityalways @ (Data or Sel)
case(Sel)0: Y
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Custom MUX
module Mux16 (Data, // Data inputSel, // SelectorY // Output
);
// Port modesinput [15:0] Data;input [3:0] Sel;output Y;
// Registered identifiersregY;
// Functionalityalways @ (Data or Sel)
casez(Sel)4b0000: Y
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Code Translator (Truth Table)
module Code_Translator (Code_In,Code_Out,
);
// Port modesinput [2:0] Code_In;output [2:0] Code_Out;
// Registered identifiersreg[2:0] Code_Out;
// Functionalityalways @ (Code_In)case (Code_In)3b000: Code_Out
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Miscellaneous Techniques
{a,b}
{Data[13:12],a,b,Data[11:0]}
{16{a}}
assignY = (en) ? X : 1bz;
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4-Bit Magnitude Comparator
module Compare4 (A, // Data input AB, // Data input BAltB, // A is less than BAeqB, // A is equal to BAgtB // A is > than B
);
// Port modesinput [3:0] A,B;output AltB,AeqB,AgtB;
// Registered identifiersregAltB,AeqB,AgtB;
// Functionalityalways @ (A or B) begin
AltB
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Parameterized Design
module Compare4 (A, // Data input AB, // Data input BAltB, // A is less than B
AeqB, // A is equal to BAgtB // A is > than B);
// Define bus widthparameter BusWidth = 8;
// Port modesinput [BusWidth-1:0] A,B;
...
...
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Parameterized Design (Using
Compiler Directive)`defineBusWidth = 8;
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Lab Projects I
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Simulating Your Design
See beginning ofFrom Concept to Working
FPGA Chip: Step-by-Step Instructions
Demo:Verilog Boilerplate Generator
Silos 2001 Behavioral Simulator
http://www.rose-hulman.edu/~doering/homepage/verilog.htmhttp://www.rose-hulman.edu/~doering/homepage/verilog.htm7/29/2019 FPGA System Design With Verilog
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Combinational Design Projects
Pick several of the following designs:
3-to-8 decoder with output enable
8-to-3 priority encoder
16-bit three-input adder
10-bit barrel shifter
Enter your design and verify in Silos
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Verilog:
Sequential
Circuits
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A Gradual Introduction
New concepts in boldface
Verilog keywords in italics
Refer to your handout...
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D Flip-Flop
module D_FF (D,Clock,Q);
/* Port modes */input D,Clock;
output Q;
// Registered identifiersregQ;
// Functionality
always @ (posedge Clock)Q
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T Flip-Flop, Falling Edge
module T_FF (T,Clock,Q);
/* Port modes */input T,Clock;
output Q,;
// Registered identifiersregQ;
// Functionality
always @ (negedgeClock)if(T == 1)Q
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T Flip-Flop, Dual Outputs
module T_FF (T,Clock,Q,_Q);
/* Port modes */input T,Clock;output Q,_Q;
// Registered identifiersregQ;
// Functionalityalways @ (negedgeClock)
if(T == 1)Q
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Flip-Flop with Async. Reset
module D_FF (D,Clock,Q,_Q,Reset);
/* Port modes */input D,Clock,Reset;output Q,_Q;
// Registered identifiersregQ;
// Functionalityalways @ (negedge Clock orposedge Reset)
if(Reset == 1)Q
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Flip-Flop with Async. Preset
module D_FF (D,Clock,Q,_Preset);
/* Port modes */input D,Clock,_Preset;output Q;
// Registered identifiersregQ;
// Functionalityalways @ (posedge Clock or
negedge _Preset)if(_Preset == 0)
Q
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Flip-Flop, Synchronous Reset
module D_FF (D,Clock,Q,Reset);
/* Port modes */input D,Clock,Reset;
output Q;
// Registered identifiersregQ;
// Functionality
always @ (posedge Clock)Q
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A Brief Sermon...
NOTE: Avoid the temptation to design arbitrary flip-flop
behavior, e.g., ability to trigger on both edges of the
clock, ability to trigger on multiple clock signals, etc.
The hardware synthesis tool does not magicallycreate new hardware from thin air! You have to write
circuit descriptions that are realizable, that is, can be
mapped onto existing (known) hardware elements
such as standard D flip-flops.
Bottom line: Use the constructs listed above exactly as
shown... dont invent your own!!
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Data Register
module Reg16 (D,Clock,Q,Reset);
/* Port modes */input[15:0] D;input Clock,Reset;output[15:0] Q;
// Registered identifiersreg[15:0] Q;
// Functionalityalways @ (posedge Clock orposedge Reset)
if(Reset == 1)Q
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Up Counter with Async. Reset
module CountUp (Clock,Reset,Q);
// Port modesinput Clock,Reset;output [7:0] Q;
// Registered identifiersreg[7:0] Q;
// Functionalityalways @ (posedge Clock orposedge Reset)
if(Reset == 1)
Q
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Up Counter with Enable
// Functionality
always @ (posedge Clock or
posedge Reset)
if(Reset == 1)
Q
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Down Counter
module CountDown (Clock,Reset,Enable,Init,Q);
// Port modesinput Clock,Reset,Enable,Init;output [7:0] Q;
// Registered identifiersreg[7:0] Q;
// Functionalityalways @ (posedge Clock orposedge Reset)
if(Reset == 1)Q
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Loadable Shift Register
module Shifter (Clock,Reset,Load,D,Q);
// Port modesinput Clock,Reset,Load;input [7:0] D;output [7:0] Q;
// Registered identifiersreg[7:0] Q;
// Functionalityalways @ (posedge Clock orposedge Reset)
if(Reset == 1)Q
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Clock Divider
parameterMaxCount = 12;
always @ (posedge Clock orposedge Reset)
if(Reset) begin
ClockDiv
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Design Rules
Generally speaking, follow good design
practice for digital systems, e.g., avoid
gated clocks In particular, strive to write descriptions that
make all flip-flop clocks connect to the
master clock Use asynchronous reset on all flip-flops
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Design Rules (contd)
Use a systematic naming convention for
identifiers:
i$Identifier Module inputo$Identifier Module output
r$Identifier Registered
p$Identifier Parameter
w$Identifier Wire
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Topics for Future Exploration
Finite State Machines
One-hot encoding
casez (efficient next-state decoder) Data path / controller architecture
Detailed design rules for FPGAs
Timing and performance tuning Instantiation, multi-module systems
Testbench design
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References
http://www.rose-
hulman.edu/~doering/fpga_workshop/refere
nces.htm
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Lab Projects II
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Development Procedure
Introduction to the XS-40 board
Review the step-by-step development
procedure
http://localhost/var/www/apps/conversion/tmp/scratch_1/xs40-manual-v1_4.pdfhttp://localhost/var/www/apps/conversion/tmp/scratch_1/concept_to_chip.htmhttp://localhost/var/www/apps/conversion/tmp/scratch_1/concept_to_chip.htmhttp://localhost/var/www/apps/conversion/tmp/scratch_1/concept_to_chip.htmhttp://localhost/var/www/apps/conversion/tmp/scratch_1/concept_to_chip.htmhttp://localhost/var/www/apps/conversion/tmp/scratch_1/concept_to_chip.htmhttp://localhost/var/www/apps/conversion/tmp/scratch_1/concept_to_chip.htmhttp://localhost/var/www/apps/conversion/tmp/scratch_1/concept_to_chip.htmhttp://localhost/var/www/apps/conversion/tmp/scratch_1/concept_to_chip.htmhttp://localhost/var/www/apps/conversion/tmp/scratch_1/xs40-manual-v1_4.pdfhttp://localhost/var/www/apps/conversion/tmp/scratch_1/xs40-manual-v1_4.pdfhttp://localhost/var/www/apps/conversion/tmp/scratch_1/xs40-manual-v1_4.pdf7/29/2019 FPGA System Design With Verilog
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First Design Project
Implement the following system:
SimpleSystem
A B
C
B = A, C = ~A
(use Pin 44)
(use Pin 19)
(use Pin 25)
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Lab Projects III
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10-Second Count Down Timer
Design and implement a 10 second counter
(9 down to 0) with pause and reset inputs
Display the count value on the 7-segmentdisplay
Use the 100 MHz on-board clock
Use the lower two bits of the PC parallelport for the pause and reset input signals
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FPGA System Design with
VerilogA Workshop Prepared for
Rose-Hulman Ventures
Ed Doering