Post on 18-Jun-2020
© Digital Integrated Circuits2nd Design Methodologies
Evolution in
Microelectronics Technology
INTRODUCTION
© Digital Integrated Circuits2nd Design Methodologies
The First Computer
The BabbageDifference Engine(1832)
25,000 parts
cost: £17,470
© Digital Integrated Circuits2nd Design Methodologies
ENIAC - The first electronic computer (1946)
© Digital Integrated Circuits2nd Design Methodologies
The Transistor Revolution
The Nobel Prize in Physics 1956
"for their researches on semiconductors and their discovery of the transistor effect"
William Bradford Shockley John Bardeen Walter Houser Brattain
© Digital Integrated Circuits2nd Design Methodologies
The Transistor Revolution
First transistor
Bell Labs, 1948
© Digital Integrated Circuits2nd Design Methodologies
The First Integrated Circuits
Bipolar logic
1960’s
ECL 3-input Gate
Motorola 1966
© Digital Integrated Circuits2nd Design Methodologies
Intel 4004 Micro-Processor
1971
1000 transistors
1 MHz operation
© Digital Integrated Circuits2nd Design Methodologies
Intel Pentium (IV) microprocessor
© Digital Integrated Circuits2nd Design Methodologies
Moore’s Law
© Digital Integrated Circuits2nd Design Methodologies
Moore’s Law
• In 1965, Gordon Moore noted that the
number of transistors on a chip
doubled every 18 to 24 months.
• He made a prediction that
semiconductor technology will double
its effectiveness every 18 months
© Digital Integrated Circuits2nd Design Methodologies
Moore’s Law
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
LO
G2 O
F T
HE
NU
MB
ER
OF
CO
MP
ON
EN
TS
PE
R IN
TE
GR
AT
ED
FU
NC
TIO
N
Electronics, April 19, 1965.
© Digital Integrated Circuits2nd Design Methodologies
Evolution in Complexity
© Digital Integrated Circuits2nd Design Methodologies
Moore’s law in Microprocessors
40048008
80808085 8086
286386
486Pentium® proc
P6
0.001
0.01
0.1
1
10
100
1000
1970 1980 1990 2000 2010
Year
Tra
ns
isto
rs (
MT
)
2X growth in 1.96 years!
Transistors on Lead Microprocessors double every 2 years
Courtesy, Intel
© Digital Integrated Circuits2nd Design Methodologies
Die Size Growth
40048008
80808085
8086286
386486Pentium ® proc
P6
1
10
100
1970 1980 1990 2000 2010
Year
Die
siz
e (
mm
)
~7% growth per year
~2X growth in 10 years
Die size grows by 14% to satisfy Moore’s Law
Courtesy, Intel
© Digital Integrated Circuits2nd Design Methodologies
Frequency
P6
Pentium ® proc486
38628680868085
8080
80084004
0.1
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
Fre
qu
en
cy (
Mh
z)
Lead Microprocessors frequency doubles every 2 years
Doubles every
2 years
Courtesy, Intel
© Digital Integrated Circuits2nd Design Methodologies
Power Dissipation
P6Pentium ® proc
486
386
2868086
80858080
80084004
0.1
1
10
100
1971 1974 1978 1985 1992 2000
Year
Po
we
r (W
att
s)
Lead Microprocessors power continues to increase
Courtesy, Intel
© Digital Integrated Circuits2nd Design Methodologies
Power will be a major problem
5KW 18KW
1.5KW
500W
40048008
80808085
8086286
386486
Pentium® proc
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008
Year
Po
we
r (W
att
s)
Power delivery and dissipation will be prohibitive
Courtesy, Intel
© Digital Integrated Circuits2nd Design Methodologies
Power density
40048008
8080
8085
8086
286386
486Pentium® proc
P6
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
Po
we
r D
en
sit
y (
W/c
m2
)
Hot Plate
Nuclear
Reactor
Rocket
Nozzle
Power density too high to keep junctions at low temp
Courtesy, Intel
© Digital Integrated Circuits2nd Design Methodologies
Not Only Microprocessors
Digital Cellular Market
(Phones Shipped)
1996 1997 1998 1999 2000
Units 48M 86M 162M 260M 435MAnalog
Baseband
Digital Baseband
(DSP + MCU)
Power
Management
Small
Signal RFPower
RF
(data from Texas Instruments)
Cell
Phone
© Digital Integrated Circuits2nd Design Methodologies
Challenges in Digital Design
“Microscopic Problems”• Ultra-high speed design
• Interconnect
• Noise, Crosstalk
• Reliability, Manufacturability
• Power Dissipation
• Clock distribution.
Everything Looks a Little Different
“Macroscopic Issues”• Time-to-Market
• Millions of Gates
• High-Level Abstractions
• Reuse & IP: Portability
• Predictability
• etc.
…and There’s a Lot of Them!
?
© Digital Integrated Circuits2nd Design Methodologies
Productivity Trends
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
2003
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2005
2007
2009
10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Logic Tr./Chip
Tr./Staff Month.
xxx
xxx
x
21%/Yr. compoundProductivity growth rate
x
58%/Yr. compoundedComplexity growth rate
10,000
1,000
100
10
1
0.1
0.01
0.001
Lo
gic
Tra
nsis
tor
per
Ch
ip(M
)
0.01
0.1
1
10
100
1,000
10,000
100,000
Pro
du
cti
vit
y
(K)
Tra
ns./S
taff
-M
o.
Source: Sematech
Complexity outpaces design productivity
Co
mp
lexit
y
Courtesy, ITRS Roadmap
© Digital Integrated Circuits2nd Design Methodologies
Design Metrics
How to evaluate performance of a digital circuit (gate, block, …)?
Cost
Reliability
Scalability
Speed (delay, operating frequency)
Power dissipation
Energy to perform a function
© Digital Integrated Circuits2nd Design Methodologies
Cost of Integrated Circuits
NRE (non-recurrent engineering) costs
design time and effort, mask generation
one-time cost factor
Recurrent costs
silicon processing, packaging, test
proportional to volume
proportional to chip area
© Digital Integrated Circuits2nd Design Methodologies
NRE Cost is Increasing
© Digital Integrated Circuits2nd Design Methodologies
Die Cost
Single die
Wafer
From http://www.amd.com
Going up to 12” (30cm)
© Digital Integrated Circuits2nd Design Methodologies
Cost per Transistor
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012
cost: ¢-per-transistor
Fabrication capital cost per transistor (Moore’s law)
© Digital Integrated Circuits2nd Design Methodologies
Yield
%100per wafer chips ofnumber Total
per wafer chips good of No.Y
yield Dieper wafer Dies
costWafer cost Die
area die2
diameterwafer
area die
diameter/2wafer per wafer Dies
2
© Digital Integrated Circuits2nd Design Methodologies
Defects
area dieareaunit per defects1yield die
is approximately 3
4area) (die cost die f
© Digital Integrated Circuits2nd Design Methodologies
Some Examples (1994)
Chip Metal
layers
Line
width
Wafer
cost
Def./
cm2
Area
mm2
Dies/
wafer
Yield Die
cost
386DX 2 0.90 $900 1.0 43 360 71% $4
486 DX2 3 0.80 $1200 1.0 81 181 54% $12
Power PC
6014 0.80 $1700 1.3 121 115 28% $53
HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73
DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149
Super Sparc 3 0.70 $1700 1.6 256 48 13% $272
Pentium 3 0.80 $1500 1.5 296 40 9% $417
© Digital Integrated Circuits2nd Design Methodologies
Problematiche dell’evoluzione
tecnologica
1. METODOLOGIE DI
PROGETTAZIONE
© Digital Integrated Circuits2nd Design Methodologies
Why Scaling?
Technology shrinks by 0.7/generation
With every generation can integrate 2x more functions per chip; chip cost does not increase significantly
Cost of a function decreases by 2x
But … How to design chips with more and more functions?
Design engineering population does not double every two years…
Hence, a need for more efficient design methods Exploit different levels of abstraction
© Digital Integrated Circuits2nd Design Methodologies
Design Abstraction Levels
n+n+
S
GD
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
© Digital Integrated Circuits2nd Design Methodologies
A Simple Processor
MEMORY
DATAPATH
CONTROL
INPUT-OUTPUT
INP
UT
/OU
TP
UT
© Digital Integrated Circuits2nd Design Methodologies
Design at a crossroad
System-on-a-Chip
RAM
500 k Gates FPGA
+ 1 Gbit DRAM
Preprocessing
Multi-
Spectral
Imager
mC
system
+2 Gbit
DRAMRecog-
nition
Anal
og
64 SIMD Processor
Array + SRAM
Image Conditioning
100 GOPS
Embedded applications
where cost, performance,
and energy are the real
issues!
DSP and control intensive
Mixed-mode
Combines programmable
and application-specific
modules
Software plays crucial role
© Digital Integrated Circuits2nd Design Methodologies
A System-on-a-Chip: Example
Courtesy: Philips
© Digital Integrated Circuits2nd Design Methodologies
Impact of Implementation ChoicesE
nerg
y E
ffic
iency
(in M
OP
S/m
W)
Flexibility
(or application scope)
0.1-1
1-10
10-100
100-1000
None Fully
flexible
Somewhat
flexible
Hard
wired c
usto
m
Configura
ble
/Para
mete
rizable
Dom
ain
-specific
pro
cessor
(e.g
. D
SP
)
Em
bedded m
icro
pro
cessor
© Digital Integrated Circuits2nd Design Methodologies
Design Methodologies
Custom
Standard CellsCompiled Cells
Macro Cells
Cell-based
Pre-diffused(Gate Arrays)
Pre-wired(FPGA's)
Array-based
Semicustom
Digital Circuit Implementation Approaches
Implementation Choices
© Digital Integrated Circuits2nd Design Methodologies
The Custom Approach
Intel 4004
Courtesy Intel
© Digital Integrated Circuits2nd Design Methodologies
Transition to Automation and Regular Structures
Intel 4004 (‘71)
Intel 8080 Intel 8085
Intel 8286 Intel 8486
Courtesy Intel
© Digital Integrated Circuits2nd Design Methodologies
Semicustom Design Flow
HDL
Logic Synthesis
Floorplanning
Placement
Routing
Tape-out
Circuit Extraction
Pre-Layout
Simulation
Post-Layout
Simulation
Structural
Physical
BehavioralDesign Capture
De
sig
n Ite
ratio
n
© Digital Integrated Circuits2nd Design Methodologies
Design Methodologies
Custom
Standard CellsCompiled Cells
Macro Cells
Cell-based
Pre-diffused(Gate Arrays)
Pre-wired(FPGA's)
Array-based
Semicustom
Digital Circuit Implementation Approaches
Implementation Choices
© Digital Integrated Circuits2nd Design Methodologies
RAM-based FPGA
Xilinx XC4000ex
Courtesy Xilinx
© Digital Integrated Circuits2nd Design Methodologies
Summary
Digital CMOS Design is kicking and healthy
Some major challenges down the road caused by Deep Sub-micron Super GHz design
Power consumption!!!!
Reliability – making it work
Some new circuit solutions are bound to emerge
Who can afford design in the years to come? Some major design methodology change in the making!
© Digital Integrated Circuits2nd Design Methodologies
Digital Integrated
CircuitsA Design Perspective
Manufacturing
Process
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
July 30, 2002
© Digital Integrated Circuits2nd Design Methodologies
CMOS Process
© Digital Integrated Circuits2nd Design Methodologies
Patterning of SiO2
Si-substrate
Si-substrate Si-substrate
(a) Silicon base material
(b) After oxidation and depositionof negative photoresist
(c) Stepper exposure
Photoresist
SiO2
UV-light
Patternedoptical mask
Exposed resist
SiO2
Si-substrate
Si-substrate
Si-substrate
SiO2
SiO2
(d) After development and etching of resist,chemical or plasma etch of SiO
2
(e) After etching
(f) Final result after removal of resist
Hardened resist
Hardened resist
Chemical or plasmaetch
© Digital Integrated Circuits2nd Design Methodologies
CMOS Process at a Glance
Define active areas
Etch and fill trenches
Implant well regions
Deposit and patternpolysilicon layer
Implant source and drainregions and substrate contacts
Create contact and via windowsDeposit and pattern metal layers
© Digital Integrated Circuits2nd Design Methodologies
oxidation
opticalmask
processstep
photoresist coatingphotoresistremoval (ashing)
spin, rinse, dryacid etch
photoresist
stepper exposure
development
Typical operations in a single
photolithographic cycle (from [Fullman]).
Photo-Lithographic Process
© Digital Integrated Circuits2nd Design Methodologies
A Modern CMOS Process
p-well n-well
p+
p-epi
SiO2
AlCu
poly
n+
SiO2
p+
gate-oxide
Tungsten
TiSi2
Dual-Well Trench-Isolated CMOS Process
© Digital Integrated Circuits2nd Design Methodologies
CMOS Process Walk-Through
p+
p-epi (a) Base material: p+ substrate with p-epi layer
p+
(c) After plasma etch of insulatingtrenches using the inverse of the active area mask
p+
p-epiSiO
2
3SiN
4
(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)
© Digital Integrated Circuits2nd Design Methodologies
CMOS Process Walk-ThroughSiO
2
(d) After trench filling, CMPplanarization, and removal of sacrificial nitride
(e) After n-well and V
Tpadjust implants
n
(f) After p-well andV
Tnadjust implants
p
© Digital Integrated Circuits2nd Design Methodologies
CMOS Process Walk-Through
(g) After polysilicon depositionand etch
poly(silicon)
(h) After n+ source/drain andp+source/drain implants. These
p+n+
steps also dope the polysilicon.
(i) After deposition of SiO2insulator and contact hole etch.
SiO2
© Digital Integrated Circuits2nd Design Methodologies
CMOS Process Walk-Through
(j) After deposition and patterning of first Al layer.
Al
(k) After deposition of SiO2insulator, etching of via’s,
deposition and patterning ofsecond layer of Al.
AlSiO
2
© Digital Integrated Circuits2nd Design Methodologies
© Digital Integrated Circuits2nd Design Methodologies
© Digital Integrated Circuits2nd Design Methodologies
© Digital Integrated Circuits2nd Design Methodologies
© Digital Integrated Circuits2nd Design Methodologies
© Digital Integrated Circuits2nd Design Methodologies
© Digital Integrated Circuits2nd Design Methodologies
© Digital Integrated Circuits2nd Design Methodologies
© Digital Integrated Circuits2nd Design Methodologies
Advanced Metallization
© Digital Integrated Circuits2nd Design Methodologies
Advanced Metallization
© Digital Integrated Circuits2nd Design Methodologies
© Digital Integrated Circuits2nd Design Methodologies