Microelectronics Lab ELCT706 IC Design Lab Session #2

IC Layout

Dr. Eman Azab Eng. Samar Shukry

Design the layout view of an inverter circuit using

automatically generated nmos and pmos devices.

The schematic view of the inverter circuit is as follows:

Launch Layout XL Create a new layout with an automatic

configuration.

Choose the library in which the schematic is saved, choose a

name for your layout cellview and choose both type and view

to be layout.

This window will pop up representing the space in which the

layout design is to be constructed with the help of the LSW to

select the suitable layers.

And now, in order to build the layout, we are going to use the

ready designed layouts for the nmos and pmos devices used in

the schematic view together with the pins generated earlier in

the schematic.

Connectivity Generate All from Source (this option

enables us to generate the layout forms of all devices and pins

in the schematic) if you choose option “ Selected from source”

you can choose from schematic which device or pin to be

generated.

The following window will pop up:

We select the instances and I/O pins to be generated

automatically

We then select the I/O Pins tab:

From this window, we choose the layer used in generating the

pins to be a metal1 layer that is used for the purpose of pins

and hence it is called M1”pin”.

We can also manipulate the label that will be put on the pin

which must be the same as the name you chose for the pin in

the schematic. Create Label as Options.

We can adjust the height and the font of the label as required,

in the Layer name, we choose the name of the layer from

which the pin will be made which is Metal1 “M1” and in the

Layer purpose, we have to define that this layer will be used

for pin.

This window will pop up:

To see the layers of the generated devices in the layout view,

you can press shift + f and the following view will appear.

After generating the devices, we start to connect the devices

as illustrated in the schematic view to build up the inverter

layout view, we start to move the pmos device over the nmos

device and as shown in figure, connection lines will appear

showing us which terminals should be connected and to which

signal.

We start with connecting the two gates together using a

polysilicon “PO” layer and the two drains together using a

metal1 layer.

Note: to draw the drain connection using a metal1 layer, we

can select the M1 layer used for drawing from the LSW and

draw a rectangular shape between both drains or we can

create what is called a “wire” , Create wire and select the

starting point which is the drain of the pmos and select the

end point of the wire which is the drain of the nmos, double

click at the end point, the wire will be created, if you click

once, this segment of the wire will end and the tool will start

another segment.

Now, we are going to generate the bulk terminals of the nmos

and pmos devices as follows:

Select the device nmos or pmos and press “q”, the following

window will appear:

From the parameter tab, we will find a parameter called

“bodytie_typeL” and “bodytie_typeR”, this is the body ”bulk”

contact we need to generate, where bodytie_typeL is used to:

generate the bulk at the side of the source terminal of the

device, while bodytie_typeR is used to: generate the bulk at

the side of the drain terminal of the device.

The option of the bodytie to be “integred” will connect the

bulk terminal to the source/drain terminal of the device using

a metal1 layer while option “detached” will leave it

unconnected.

In our example, we chose bodytie_typeL and hence the bulk

was generated at the source side of the transistor, and we

also chose it to be integred and hence the generated bulk is

connected to the source of the transistor by a metal layer.

The next step is to draw the power rails for the Vdd and Gnd

supplies and connect the bulk of the pmos to the vdd and that

of the nmos to the ground as follows:

From the above figure, we can notice that we have two metal

layers of same type on each other forming a short circuit and

that was intended as we want the signals on both layers to

see each other.

The next step is to route the input signal to the gate of both

transistors, and to do that, we use a metal1 layer for routing

the signal but we need this signal to be seen at the polysilicon

layer therefore to connect two different layers, we use what is

called a via, Create via.

We chose the via definition to be a via between M1 and PO

layers and then place the via over the PO layer as follows.

From the figure, we can notice that when we activate the

option of DRD notify while placing the via, it shows that there

is a minimum spacing that must not be violated between the

Metal1 layer in the via and that used to connect the drains of

both transistors and also that the area of the metal layer in

the via is not fulfilling the design rules, so we drag the via

outwards till the notification disappears and place it then

cover it with a metal layer with an area obeying the design

rules.

This is the final layout after putting the pins, now we check

and save to run the DRC and LVS checks.

To Run the DRC, Calibre Run nmDRC

Extracting the layout to be checked:

Entering the directory of the DRC rules file as follows:

We check that the rules file is mounted correctly and Run

DRC.

To run the LVS check , Calibre Run nmLVS, we use same

directory as DRC except for last step instead of drc folder we

use the lvs one and select the file called calibre.lvs.

Note that in case of LVS check, we export the layout and we

have to export the schematic view file as well so in the inputs

tab we choose the Netlist tab and make sure that the

schematic source file is exported.

If this correct sign and smiley face appeared then your layout

matches with the schematic and hence you checked the

function implemented.

The comparison result shows the matched points and the

mismatches if exist.

Right click on the layout file name view cell, you will see

the gate level/transistor level of the layout file versus that of

the schematic file.

Extras:

Note that: if we want to create a pin:

Create pin

We enter the name of the pin, we choose its I/O type and we

should activate the ‘Display Terminal name” option, from the

options we can manipulate the display of the pin like we did

with the one generated.

We can also create the label of the pin separately Create

Label.