A-7739, and by the Research Foundation of the City Uni-versity of New York PSC-CUNY-16, grant 6-65246.

6 References

1 SWAMY, M.N.S., ROYTMAN, L.M., and DELANSKY, J.F.: 'Finiteword length effect and stability of multidimensional filters', Proc.IEEE, 1981,69, (10), pp. 1370-1372

2 SWAMY, M.N.S., ROYTMAN, L.M., and PLOTKIN, E.I.: 'On sta-bility tests for two-dimensional digital filters', IEE Proc. G, Electron.Circuits & Syst., 1985, 132, (2), pp. 57-59

3 GOODMAN, D.: 'Some stability properties of two-dimensionallinear shift-invariant digital filters', IEEE Trans., 1977, CAS-24,pp.201-208

4 SWAMY, M.N.S., ROYTMAN, L.M., and PLOTKIN, E.I.: 'OnBIBO stability of N-dimensional shift-invariant digital filters', ibid.,1985, CAS-32, pp. 888-892

5 JURY, E.I.: 'Stability of multidimensional scalar and matrix poly-nomials', Proc. IEEE, 1978, 66, pp. 1018-1047

6 BOSE, N.K., and NEWCOMB, R.W.: 'Tellegen's theorem for multi-variable readability theory', Int. J. Electron., 1984, 36, pp. 417-425

7 KAISER, J.F.: 'Some practical considerations in the realization oflinear digital filters'. Proceedings of 3rd Allerton Conference Circuitand System Theory, 1965, pp. 621-633

8 RADER, CM., and GOLD, B.: 'Effects of parameter quantisation onthe poles of a digital filter', Proc. IEEE, 1967, 55, pp. 688-689

9 MITRA, S.K., and SHERWOOD, R.J.: 'Estimation of pole-zero dis-placements of a digital filter due to coefficient quantisation', IEEETrans., 1974, CAS-21, pp. 116-124

10 MARIA, G.A., and FAHMY, M.M.: 'Effect of rounding on the stabil-ity of two-dimensional digital filters', Int. J. Circuit Theory & Appl.,1975, 3, pp. 149-156

11 ROYTMAN, L.M., and SWAMY, M.N.S.: 'An expression for theJacobian of the roots of a polynomial', Proc. IEEE, 1980, 68, pp.737-738

ErratumMOUFTAH, H.T., and GARBA, A.I.: 'VLSI implementa-tion of a 5-trit full adder', IEE Proc. G, Electron. Circuits <£Syst., 1984,131, (5), pp. 214-220

The circuit of the ternary inverse cycling gate, a com-ponent of the ternary full adder, was described wrongly inFig. 7. The ternary inverse cycling gate that was actuallyused in the implementation of the 5-trit full adder is shownin Fig. 1. The ternary operator shown at the input of theternary switch TS, is an earthed negative ternary inverter

TS2

vc

TSi

(ENTI) and not a binary inverter as was shown in Fig. 7 ofthe paper.

H.T. MOUFTAH

4353GDepartment of Electrical EngineeringQueen's UniversityKingston, OntarioCanada K7L3N6

Fig. 1 Ternary inverse cycling gate

38 IEE PROCEEDINGS, Vol. 133, Pt. G, No. I, FEBRUARY 1986