Erratum: VLSI implementation of a 5-trit full adder
Transcript of Erratum: VLSI implementation of a 5-trit full adder
A-7739, and by the Research Foundation of the City Uni-versity of New York PSC-CUNY-16, grant 6-65246.
6 References
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ErratumMOUFTAH, H.T., and GARBA, A.I.: 'VLSI implementa-tion of a 5-trit full adder', IEE Proc. G, Electron. Circuits <£Syst., 1984,131, (5), pp. 214-220
The circuit of the ternary inverse cycling gate, a com-ponent of the ternary full adder, was described wrongly inFig. 7. The ternary inverse cycling gate that was actuallyused in the implementation of the 5-trit full adder is shownin Fig. 1. The ternary operator shown at the input of theternary switch TS, is an earthed negative ternary inverter
TS2
vc
TSi
(ENTI) and not a binary inverter as was shown in Fig. 7 ofthe paper.
H.T. MOUFTAH
4353GDepartment of Electrical EngineeringQueen's UniversityKingston, OntarioCanada K7L3N6
Fig. 1 Ternary inverse cycling gate
38 IEE PROCEEDINGS, Vol. 133, Pt. G, No. I, FEBRUARY 1986