Entegra’s SDR Module1. Dual 14 bit 65Msps A/D converters with a sampling bandwidth of 200MHz. 2. Dual 14 bit 100Msps D/A converters. 3. 2 million equivalent gate Xilinx V2000E FPGA 4. On-board RAM: 1MB Sync Burst SRAM, 128kB dual-port SRAM. 5. On-board high stability 10MHz reference and programmable DDS to support virtually

any clock scheme currently in use. 6. 24/48 bit high speed LVDS or LV-TTL digital interface 7. 2MB FLASH ROM for FPGA configuration, also configurable via JTAG or DSP bus. 8. Omnibus DSP interface compatible with a range of Innovative Integration DSP cards. 9. Compact: 100mm x 160mm mezzanine mounting module.

W-CDMA Downlink Simulator test-bed for experimenting with system partitioning in a user terminal

Internal architecture of the physical channel processor FPGA

The digital down-converter and filters

Digital Up-Converter (DUC)

Rake Receiver

Searcher Receiver Matched Filter

Eight Channel W-CDMA Transmitter

Timing Controller

DSP Software Structure