Electrocardiogram (ECG) application operation – Part A

Performed By: Ran GelerMor Levy

Instructor: Moshe Porian

Project Duration: 2 Semesters

Spring 2012

Final Presentation

ContentsIntroductionTop ArchitectureOverviewData FlowComponentsSimulationsPerformanceProblems in developing processConclusionsPart B schedule

IntroductionThe heart is a muscular organ

that beats in rhythm to pump blood through the body

By analyzing the heart behavior and especially the electrical impulses we can help identify heart diseases and special circumstance that require

close monitoring

Medical TermsECGLead

◦Bipolar leads ◦Unipolar leads ◦Precordial Leads

Project Overview

Project GoalsPortable ECG device based on

FPGAIntegrating Multi Platforms

elements◦ECG DB with FPGA

Interactive GUI with debugger abilities (Part B)

Methodic project

Top Architecture

What we have achieved:Implementing ECG controller

◦ECG FSM◦ Integration with peripheral components.

Examination of the Implemented components◦Creating tests bench◦Mocking TI DB behavior

P& R to projects top architecture by Quartus

Adding Flash memory support

Top Architecture – Data Flow

Top Architecture – FrequencyFrequency requirements for modules

FPGA:

Main frequency: 100MHz

Rx / Tx Modules

@ frequency of 115,200Hz

ADS1928R:

Main frequency: 2.048MHz

SPI-Data Out freq’: >110KHz

MATLAB GUI:

Rx / Tx Via UART interface

@frequency of

115,200Hz

Flash Memory:

Main frequency: 100MHz

Core microarchitecture

512Bytes

Data Rate: 100MHz

Data Rate :

>110KHz

Core Architecture ECG FSMFIFOCommand & Aux RegsWishbone Master & SlaveSPI Core

ECG FSMControls the flow of data between

the host and the DBThree Main chain of actions:

◦Read Data◦Read Registers◦Write Registers

ECG FSM - Graph

FIFO at ECG Controller

1st Command

2nd Command

Additional Data

Operation Commands (ex: RDATAC, Rreg, Wreg, Standby, Reset, ect’..)

Optional: Second Byte for (Rreg, Wreg) and sample interval for RDATAC command.

Data for commands

• FIFO Size: 512 Bytes.• Stores Instruction and Sampled data.• Data structure on Instruction case:

SPIThe SPI Interface frequency:

At 24bit resolution per 8 Electrodes and 500 Samples per Sec:

Active at low. i.e. CS = ‘0’

( 4 ) ( 24)SCLK DR CLK BITS CHANNELSt t t N N

110clockt KHz

1/DRt Sample Rate

Flash Component

FLASH

Flash Controller FlashFSM

RAM

Reset en

WBS

Flash Component

256Byte

Flash Component - FlashOne sample(24bit res. per 8 Electrodes)=

27Byte.Lets assume sample rate of 500

SPSFlash size = 4MBTherefore we can sample for

5min.

Flash Component – Flash client

Technical Demands:•Common FLASH Interface protocol (CFI)•Wishbone Interface•Performs Read, Write, Reset and Erase transactions•Initiative read on power-on•Contains a timeout algorithm•Generic: adaptable to different FLASH sizes and clock frequencies.

BUS

Wishbone

CFI

ADS1298R ECG DBTexas Instruments CardArrived to the High Speed Digital

Systems Lab

ADS1298R ECG DBFuture acquisitions of probes and

electrodesConnection of the DB

to the FPGA

Test MethodologiesOperation of the ECG Controller:

◦Checking that states change are at time◦Checking control signals & data signals

between units◦Non existing commands

NOTE: When a transaction is executed the wishbone “stall” signal is raised to ‘High’, So other requests will remain pending at the Rx Wishbone Master.

ECG Controller TB Data FlowWe have implemented a special closed

component for Testing.

DB mockingWe have implemented a component that is

imitating the TI DB behavior.

ADS1298R ECG DB

Simulations – Read Transaction example

Top Architecture Wave.

Rx Transaction SPI

Flash

Simulations – Read Transaction exampleSPI Transaction

Simulations – Read Transaction exampleFlash transaction

Simulations – Read Transaction exampleFIFO Usage

Quartus SimulationsGeneral Layout

Quartus SimulationsMax Frequency

Quartus SimulationsTop Arc Synthesis summary

Problems in developing process

Meet timings requirements of the TI Evaluation board.

Keep the projects specifications and requirements while adding more logic to the top arch.

Debug and testing of thewhole implemented logic.

Conclusions

We learned a lot about the developing process & the importance of good planning a head

The importance of working organized

How much good documentation of previous project is important

Schedule – Part B

Designing The GUI interface (off line)

Planning the GUI methods

Building GUI using Matlab

Test & Debug

1w

3w

1w

1w

Schedule – Part B Cont.

Project book completion

Semester B -Final Presentation

1w

1w