Post on 17-Nov-2020
EE141
EECS 151/251ASpring2018DigitalDesignandIntegratedCircuitsInstructors:NickWeaver&JohnWawrzynek
Lecture 12
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Wire Models
All-inclusive model Capacitance-only
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Capacitance
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Capacitance: The Parallel Plate Model
❑ Cap scaling (s – process scaling factor) ▪ Local wires
–W, L, tdi all decrease (~s) –Cap decreases linearly with feature size (~s)
▪ Global wires –W, tdi decrease (~s), L constant –Cap ~constant
❑ Permittivity is a property of the dialectric: εdi = 𝜅ε0
Dielectric
Substrate
L
W
H
tdi
Electrical-field lines
Current flow
WLt
cdi
diint
ε=
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Permittivity/Dialectric Constant
❑ Low-k dielectrics used sub-130nm ▪ Carbon-doped oxide ▪ Fabs also looking at air-gaps
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𝜅 (factor of of ε0)
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Fringing Capacitance
❑ Fringe cap per unit length ~const (good rule of thumb 0.2fF/um)
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W - H/2H
+
(a)
(b)
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Fringing versus Parallel Plate
❑ Narrow, tall wires in modern processes ▪ Trying to keep resistance from increasing ▪ Comes at the expense of fringe cap
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(from [Bakoglu89])
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Interwire Capacitance
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fringing parallel
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Impact of Interwire Capacitance
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(from [Bakoglu89])
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Resistance
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Wire Resistance
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W
LH
R = ρH W
L
Sheet ResistanceRo
R1 R2
Units Ω-m
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Interconnect Resistance
12Source: S. Naffziger, AMD, VLSI 2011
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Impact on Delay
13Source: Applied Materials
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Interconnect Modeling
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The Lumped ModelVout
VoutV incwire S
Rdriver
ClumpedDriver
VoutVout
V incwire S
Rdriver
ClumpedDriver
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The Distributed RC-lineDriver Receiverdx
r dx
c dx
r dx
c dx
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❑ Analysis method: ▪ Break the wire up into segments of length dx ▪ Each segment resistance (r dx) ▪ Capacitance (c dx)
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The Distributed RC-line
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2
V Vrc
t x∂ ∂
=∂ ∂
( ) ( )1 1i i i iC
V V V VVI c Lt r L
− +− − −∂= Δ =
∂ Δ
r dx
c dx
r dx
c dx
r dx
c dx
r dx
c dx
r dx
c dx
Vi-1 Vi Vi+1 VoutVin
IC
The diffusion equation
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Intermezzo–DelayofRC-networks:
❑ Idea: Lets approximate things somewhat... ❑ But its a reasonably good approximation
❑ Time delay to fill each capacitor: ❑ Resistance to that capacitor & that
capacitor's capacitance ❑ Total time: Time to fill all capacitors ❑ Its a conservative and easy to calculate
delay estimate ❑ Will overestimate delays
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Delay Model of RC Networks:
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Elmore Delay Example
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Elmore Delay Example❑ Assume: ▪ m2 r is 50 mΩ/□ ▪ m2 c (for a minimum-width line) is 0.2fF/um ▪ m2 minimum width is 90nm ▪ 4x inverter Rpd = 500Ω ▪ 1X inverter input capacitance is 20fF (a standard
load)
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Elmore Delay Example
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BacktoWireDelay
r dx
c dx
r dx
c dx
r dx
c dx
r dx
c dx
r dx
c dx
Vi-1 Vi Vi+1 VoutVin
IC
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Wire Model
Model the wire with N equal-length segments:
For large values of N:
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RC-Models
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CharacteristicImpedence
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When You Get To A Board...❑ We have to fully treat the wires as
transmission lines ❑ Which means inductance also comes
into play ❑ Modeled with "Characteristic impedance"
❑ Measured in Ωs as well❑ Propagation delay also matters even more
❑ Since we are going longer distances❑ ~150 pS/inch
❑ But we don't do the math ourselves...27
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Why Impedance Matters...❑ Low impedance transmits energy better ❑ When you have an impedance mismatch...
❑ Energy gets reflected back... ❑ Which means noise & less efficiency
❑ Devices will specify the trace impedance needed: ❑ EG, WiFi Antenna trace: 50 Ω❑ DDR3 DRAM on Zynq:
40 Ω single, 80 Ω differential pair❑ Fatter wires -> lower impedance❑ Thinner boards -> lower impedance
❑ It ups the capacitance but that lowers the impedance because it lowers the inductance/capacitance ratio
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The Board "Stack-Up"❑ Boards are produced in layers just like
chips ❑ Signal layers with wires ❑ Plane layers with large areas of
conductor for power or ground ❑ Vias to connect between them
❑ In generating the stack-up can also find the characteristic impedance for traces
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An Example Stack-Up
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Customer InputPart Number/ Rev : kest001/ 1PCB Size in X : 2 inches X 3 inches
Number of layers : 10 PCB Thickness :0.047 inches
Material : NP175 Outer Layer :Signal
All MicroVias shown as are STACKED MICROVIASFinished Copper Weight
Finished Thickness
(inches)
SOLDER MASK 0.0005
L1 TOP SIGNAL 1 Oz 0.0014
DIELECTRIC 0.0035
L2 PLANE 0.5 Oz 0.0007
DIELECTRIC 0.0035
L3 SIGNAL 0.5 Oz 0.0007
DIELECTRIC 0.0035
L4 SIGNAL 0.5 Oz 0.0007
DIELECTRIC 0.0035
L5 PLANE 0.5 Oz 0.0007
DIELECTRIC 0.0100
L6 PLANE 0.5 Oz 0.0007
DIELECTRIC 0.0035
L7 SIGNAL 0.5 Oz 0.0007
DIELECTRIC 0.0035
L8 SIGNAL 0.5 Oz 0.0007
DIELECTRIC 0.0035
L9 PLANE 0.5 Oz 0.0007
DIELECTRIC 0.0035
L10 BOTTOM SIGNAL 1 Oz 0.0014
SOLDER MASK 0.0005
Total Thickness0.0474
(inches)
Customer Saved Impedance Results
Layer Impedance Model Impedance (ohms) Trace Width (mils) Space (mils)
Layer 1 Soldermask Coated Microstrip Singleended 51.7 5
Layer 1 Soldermask Coated Microstrip Differential Pair 97.82 5 10
Layer 3 Stripline Singleended 39.32 6
Layer 3 Stripline Differential Pair 82.67 4 4
Stackup Details
Number of LayersNumber of Signal Layers Number of Sequential
Laminations
Number of Plane Layers Maximum Number of Laser Drills Mechanical Drills
10 6 3 4 8 2
Sierra Circuits, Inc. www.protoexpress.com/hdi
HDI Stackup Planner — Detailed Report for HSP-240108 Option E
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Board Return Paths...❑ On a board, it isn't just transmitting a signal...
❑ You also need a return path for the current for the ground plane
❑ In general, the return path should follow the trace ❑ So if you have a break in the ground
plane, the signal should route around the break too
❑ "Bypass capacitors": Read the data sheets ❑ Act as temporary power reservoirs which
can support specific frequency responses31
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Seeing Some Of This In Action...❑ Board With
Routing... ❑ Areas of focus:
❑ DDR: Controlled Impedance & length matching
❑ Power & Ground planes:Low impedance,Lots of Bypassing
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DDR Constraints❑ 40Ω signal, 80Ω
differential❑ Obtained from
Xilinx datasheet ❑ 3 major groups of
signals ❑ 2 data banks:
8 data lines, differential data strobe
❑ 1 group of control & address lines
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This Routing of DDR...❑ Data-sheet's very low impedance
requirement needs fat wires & thin layers ❑ Limits routing to the internal layers:
Can't "escape" the BGA on the top ❑ Length matching
a semi-manualprocess ❑ Target of .025"
❑ Based onmicron'sdata sheet
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Ground and Power❑ Ground: 2 unified
planes ❑ Only exception a
bit of isolation for the WiFi chip
❑ Power: L1: 1.0/3.3/1.5 ❑ L2:
1.5/1.8/3.3 ❑ And a crap-ton® of
bypass capacitors35
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Gates and Wires
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Driving an RC-line
V i n
Rs V o ut(rw,cw,L)
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)2/(69.0 wwwsp CRCRt +=
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The Global Wire Problem
Challenges ❑ No further improvements to be expected after the
introduction of Copper (superconducting, optical?) ❑ Design solutions
▪ Use of fat wires ▪ Efficient chip floorplanning ▪ Insert repeaters
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Td = 0.69(0.5RwCw +RNCin + RNCw + RwCin)
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Reducing RC-delay Using Repeaters
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Repeater
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Repeaters
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⎟⎠
⎞⎜⎝
⎛ ++++= )5.0()(69.0mcLWC
mrLWC
mcLCW
WRmt inininN
p γ
in
Nopt
p
unbufferedpwire
inNopt
rCcR
W
tt
CRrc
Lm
=
=+
=1
)(
)1(2 γ
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Repeater Insertion
For a given technology and a given interconnect layer, there exists an optimal length of the wire segments between repeaters. The delay of these wire segments is independent of the routing layer!
in
Nopt
p
unbufferedpwire
inNopt
rCcR
W
tt
CRrc
Lm
=
=+
=1
)(
)1(2 γ
From Elmore example: rc = 0.1fs/um2, tp1 = 55ps, Lcrit = 1262um (rule of thumb ~ 0.5-1mm) 41
rct
mL
L p
optcrit 69.0
2 1== 1min,
, )1(212 p
opt
pcritp t
mt
t ⎟⎟⎠
⎞⎜⎜⎝
⎛
++==
γ
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Importance of Repeaters
❑ In modern designs the number of repeaters increases dramatically
Source: IBM POWER processors, R. Puri et al SRC Interconnect Forum 2006
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Wire and Gate Delay Scaling
❑ Gate delay gets better, wire delay gets worse
source: ITRS
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Logical Effort
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Question #1
❑ How to best combine logic and drive for a big capacitive load?
CL CL
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Question #2
❑ All of these are “decoders” ▪ Which one is “best”?
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Method to answer both of these questions
❑ Extension of buffer sizing problem
❑ Logical effort
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Complex Gate Sizing
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Complex Gate Sizing: NAND-2 Example
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2
22Cgnand = 4CG = (4/3) Cginv
Cdnand = 6CD = 6γCG =2γCginv
f = CL/Cgnand = (3/4) CL/Cginv
tpNAND = kRN(Cdnand+ CL) = kRN(2γCginv+ CL) = kRNCginv (2γ + CL/Cginv) = tinv (2γ + (4/3)f)
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Logical Effort
❑ Defines ease of gate to drive external capacitance ❑ Inverter has the smallest logical effort and intrinsic delay
of all static CMOS gates ❑ Logical effort LE is defined as:
▪ (Req,gateCin,gate)/(Req,invCin,inv) ▪ Easiest way to calculate (usually):
– Size gate to deliver same current as an inverter, take ratio of gate input capacitance to inverter capacitance
❑ LE increases with gate complexity
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Logical Effort
Measure everything in units of tinv (divide by tinv):
p – intrinsic delay - gate parameter ≠ f(W) LE – logical effort – gate parameter ≠ f(W) f – electrical fanout = CL/Cin = f (W)
Normalize everything to an inverter: LEinv =1, pinv = γ
tpgate = tinv (p + LEf)
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Delay of a Logic Gate
Gate delay:Delay = EF + p (measured in units of tinv)
effective fanout intrinsic delay
Effective fanout:EF = LE f
logical effort electrical fanout = CL/Cin
Logical effort is a function of topology, independent of sizing Effective fanout is a function of load/gate size
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Logical Effort of Gates
Fan-out (f)
Nor
mal
ized
del
ay (d
)
t
1 2 3 4 5 6 7
pINVtpNAND-2
LE= p= d=
LE= p= d=
p = γ·Fan-in (for top input)
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Delay Of NOR-2 Gate
1. Size for same resistance as inverter
2. LE = ratio of input cap of gate versus inverter
Intrinsic capacitance (Cdnor) =
tpint (NOR) =
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Question
Any logic function can be implemented using NOR gates only or NAND gates only!
Which of the two approaches is preferable in CMOS (from a performance perspective)?
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Logical Effort
[From Sutherland, Sproull, Harris]
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