EE194-EE290C28nmSoCforIoT

CMOSVLSIDesignbyNeilH.WesteandDavidMoneyHarrisSynopsys’ICCompiler™ImplementaJonUserGuideSynopsys’TimingConstraintsandOpJmizaJonUserGuide

Tips

•  Thisisbynomeanscomprehensive.

•  Keyistogettothe“goodenough”ASAP.

•  MustdevelopintuiJveunderstandingwhatthetoolistryingtoaccomplish.

DC

ConvertsadesigndescripJonwriWeninaHDL,intoanopJmizedgate-levelnetlistmappedtoaspecificlogiclibrary.WhenthesynthesizeddesignmeetsfuncJonality,Jming,power,andotherdesigngoals,youcanpassthedesigntoICCompilerforphysicalimplementaJon.

LibertyTimingFile(LIB)The.libfileisanASCIIrepresentaJonoftheJmingandpowerparametersassociatedwithanycellinaparJcularsemiconductortechnology.TheJmingandpowerparametersareobtainedbysimulaJngthecellsunderavarietyofcondiJonsandthedataisrepresentedinthe.libformat.The.libfilecontainsJmingmodelsanddatatocalculate:

•  �I/Odelaypaths•  �Timingcheckvalues•  �Interconnectdelays

I/OpathdelaysandJmingcheckvaluesarecomputedonaper-instancebasis.Pathdelaysinacircuitdependupontheelectricalbehaviorofinterconnectsbetweencells.ThisparasiJcinformaJoncanbebasedonthelayoutofthedesign,butmustbeesJmatedwhennolayoutinformaJonisavailable.Alsoitisnotpossibletopredicttheprocess,voltageandtemperaturevariaJonsandderaJngfactorscanbeincludedtocompensateforthesevariaJons.

LibertyTimingFile(LIB)Cell-baseddelaycalculaJonismodeledbycharacterizingcelldelayandoutputtransiJonJme(outputslew)asafuncJonofinputtransiJonJme(inputslew)andthecapaciJveloadontheoutputofthecell.Eachcellhasaspecificnumberofinput-to-outputpaths•  PathdelayscanbedescribedforeachinputsignaltransiJonthataffectsanoutputsignal•  Thepathdelaycanalsodependonsignalsatotherinputs(statedependencies)

A

B

C

Z

LibertyTimingFile(LIB)

Input Slew

Delay,Power, Timing Checks

OutputCapacitance

Lookup-table(non-lineardelay)model.

LibertyTimingFile(LIB)

Input Slew

Delay,Power, Timing Checks

OutputCapacitance

Lookup-table(non-lineardelay)model.

Parameter VariaJonq  Transistors have uncertainty in parameters

Process: Leff, Vt, tox of nMOS and pMOS Vary around typical (T) values

q  Fast (F) Leff: short Vt: low tox: thin

q  Slow (S): opposite q  Not all parameters are independent

for nMOS and pMOS

nMOS

pMOS

fastslow

slow

fast

TT

FF

SSFS

SF

EnvironmentalVariaJonq  VDD and T also vary in time and space q  Fast:

VDD: high T: low

Corner Voltage Temperature F 1.98 0 C T 1.8 70 C S 1.62 125 C

ProcessCornersq  Process corners describe worst case variations

-  If a design works in all corners, it will probably work for any variation. q  Describe corner with four letters (T, F, S)

-  nMOS speed -  pMOS speed -  Voltage -  Temperature

ImportantCorners

Purpose nMOS pMOS VDD Temp

Cycle time S S S S

Power F F F F

Subthreshold leakage

F F F S

q  Some critical simulation corners include

DesignObjects

TopLevelParJJoning

DesignEnvironment

BeforeadesigncanbeopJmized,youmustdefinetheenvironmentinwhichthedesignisexpectedtooperate.YoudefinetheenvironmentbyspecifyingoperaJngcondiJons,systeminterfacecharacterisJcs,andwireloadmodels.OperaJngcondiJonsincludetemperature,voltage,andprocessvariaJons.SysteminterfacecharacterisJcsincludeinputdrivers,inputandoutputloads,andfanoutloads.Theenvironmentmodeldirectlyaffectsdesignsynthesisresults.

DriveCharacterisJcs

TodeterminethedelayandtransiJonJmecharacterisJcsofincomingsignals,DesignCompilerneedsinformaJonabouttheexternaldrivestrengthandtheloadingateachinputport.Drivestrengthisthereciprocaloftheoutputdriveresistance,andthetransiJondelayataninputportistheproductofthedriveresistanceandthecapacitanceloadoftheinputport.DesignCompilerusesdrivestrengthinformaJontobuffernetsappropriatelyinthecaseofaweakdriver.Bydefault,DesignCompilerassumeszerodriveresistanceoninputports,meaninginfinitedrivestrength.

DriveCharacterisJcs

Bydefault,DesignCompilerassumeszerocapaciJveloadoninputandoutputports.

WireLoadModels

WireloadmodelsesJmatetheeffectofwirelengthandfanoutontheresistance,capacitance,andareaofnets.DesignCompilerusesthesephysicalvaluestocalculatewiredelaysandcircuitspeeds.Semiconductorvendorsdevelopwireloadmodels,basedonstaJsJcalinformaJonspecifictothevendors’process.Themodelsincludecoefficientsforarea,capacitance,andresistanceperunitlength,andafanout-to-lengthtableforesJmaJngnetlengths(thenumberoffanoutsdeterminesanominallength).

DesignRuleConstraints

DesignRuleConstraints

MIPSLayout

ICCTheICCompilertoolisasingle,convergentnetlist-to-GDSIIdesigntoolforchipdesignersdevelopingverydeepsubmicrondesigns.Ittakesasinputagate-levelnetlist,adetailedfloorplan,Jmingconstraints,physicalandJminglibraries,andfoundry-processdata,anditgeneratesasoutputaGDSII-formatfileofthelayout.

ICCDesignFlow

Centeredaroundthreecorecommands.

•  Createfloorplanandapowerplan.

•  LegalizedplacementofleafcellsandresolvesJmingclosure.

•  ImprovesclockskewandclockinserJondelay.

•  PerformsglobalrouJng.

•  Fillercells,Antennadiodes,densityfillsetc.

DesignPreparaJonTheICCompilertoolusesaMilkywaydesignlibrarytostoreyourdesignanditsassociatedlibraryinformaJon.TheICCompilertoolrequiresbothlogiclibrariesandphysicallibraries.

LogicLibrariesTheICCompilertooluseslogiclibrariestoprovideJmingandfuncJonalityinformaJonforallstandardcells.InaddiJon,logiclibrariescanprovideJminginformaJonforhardmacros,suchasRAMs.Thetoolsupportslogiclibrariesthatusenonlineardelaymodels(NLDMs)andCompositeCurrentSource(CCS)modelsandautomaJcallyselectstheJmingmodelstouse,basedonthecontentsofthelogiclibraries.

NLDMsdonotcontainenoughinformaJontocharacterizethedelayofagatedrivingacomplexRCinterconnectnetworkwiththeaccuracydesiredbysomeusers.Theyalsolacktheaccuracytofullycharacterizenoiseevents.

PhysicalLibrariesTheICCompilertoolusesMilkywayreferencelibrariesandtechnologyfilestoobtainphysicallibraryinformaJon.TheMilkywayreferencelibrariescontainphysicalinformaJonaboutthestandardcellsandmacrocellsinyourlogiclibrary.TheMilkywaydatabasecancontaindifferentrepresentaJonsofthesamecell,called“views”ofthatcell.ThesearethemaintypesofviewsusedintheICCompilertool:•CELview:Thefulllayoutviewofaphysicalstructuresuchasavia,standardcell,macro,orwholechip;containsplacement,rouJng,pin,andnetlistinformaJonforthecell.•FRAMview:AnabstractrepresentaJonofacellusedforplacementandrouJng;containsonlythemetalblockages,allowedviaareas,andpinsofthecell.•FILLview:Aviewofmetalfill,whichisusedforchipfinishingandhasnologicfuncJon,createdbythesignoff_metal_fillcommandintheICCompilertool.•CONNview:ArepresentaJonofthepowerandgroundnetworksofacell,createdbythePrimeRailorICCompilertoolandusedbyPrimeRailforIRdropandelectromigraJonanalysis.•ERRview:AgraphicalviewofphysicaldesignruleviolaJonsfoundbyverificaJoncommandsintheICCompilertoolsuchasverify_zrt_routeorsignoff_drc.

VerifyLibrariesToachievegoodresults,youmusthavehigh-qualitylibraries.Beforeyouprocessyourdesign,youshouldusethecheck_librarycommandtoensurethatthelogiclibrariesandphysicallibrariesarecorrectandconsistent.check_libraryverifiestheconsistencyofcellnames,pinnames,areavalues,busnamingconvenJons,operaJngcondiJonscaling,antennarules,andsoon.Itgeneratesadetailedreportonanyerrorsorinconsistenciesthatarefound.

DesignPreparaJonReadingthedesignAnnotaJngtheFloorplaninformaJonCreaJngLogicalPowerandGroundconnecJon

•  Aleryoureadinthedesign,youmustensurethattherearelogicalconnecJonsbetweenthepowerandgroundnetsandthepower,ground,andJe-offpinsonthecellsinyourdesign.

LinkingDesign•  WhentheICCompilertoolperformsJminganalysis,eachcellinstanceinthedesignmustbelinkedtoacellinthelinklibraries,whichprovidesitsJminginformaJon.

Placement&OpJmizaJonTherearemanyconfiguraJonsenngsthataffectthebehaviorofplacementandopJmizaJon.

PlacementKeepoutMargin:Akeepoutmarginisaregionaroundtheboundaryoffixedmacrosinyourdesigninwhichnoothercellsareplaced.

Placement&OpJmizaJonGlobalKeepoutMargin

Placement&OpJmizaJonAreabasedplacementblockages

TheICCompilertoolsupportsthefollowingtypesofarea-basedplacementblockages:•HardAhardblockagepreventstheplacementofstandardcellsandhardmacroswithinthespecifiedareaduringcoarseplacement,opJmizaJon,andlegalizaJon.•HardmacroAhardmacroblockagepreventstheplacementofhardmacroswithinthespecifiedareaduringcoarseplacement,opJmizaJon,andlegalizaJon.•SolAsolblockagepreventstheplacementofstandardcellsandhardmacroswithinthespecifiedareaduringcoarseplacement,butallowsopJmizaJonandlegalizaJontoplacecellswithinthespecifiedarea.•ParJalAparJalblockagelimitsthecelldensityinthespecifiedareaduringcoarseplacement,buthasnoeffectduringopJmizaJonandlegalizaJon.•PinApinblockagepreventstheglobalrouterfromrouJnginthespecifiedarea,andthepinplacerfromassigningpinstothearea.

Placement&OpJmizaJonHighfanoutnetsynthesis

DuringplacementandopJmizaJon,theICCompilertooldoesnotbufferclocknetsasdefinedbythecreate_clockcommand,butitdoes,bydefault,bufferotherhigh-fanoutnets,suchasresetsorscanenables,usingabuilt-inhigh-fanoutsynthesisengine.

PlacementAreaUJlizaJonU>liza>on

PlacementareauJlizaJon,orsimply“uJlizaJon,”meansthepercentageofareaavailableforplacementthatisalreadyoccupiedbyplacedcells.Forexample,auJlizaJonof80percentmeansthat80percentoftheavailableareaisoccupiedbycellsand20percentisemptyandcansJllbeusedforaddiJonalcellplacement,formovementofcellsforlegalizaJonandopJmizaJon,orasanallowancetopreventexcessiverouJngcongesJon.