EE194-EE290Cee290c/sp17/lectures/... · 2017. 4. 19. · CMOS VLSI Design by Neil H. Weste and...
Transcript of EE194-EE290Cee290c/sp17/lectures/... · 2017. 4. 19. · CMOS VLSI Design by Neil H. Weste and...
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EE194-EE290C28nmSoCforIoT
CMOSVLSIDesignbyNeilH.WesteandDavidMoneyHarrisSynopsys’ICCompiler™ImplementaJonUserGuideSynopsys’TimingConstraintsandOpJmizaJonUserGuide
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Tips
• Thisisbynomeanscomprehensive.
• Keyistogettothe“goodenough”ASAP.
• MustdevelopintuiJveunderstandingwhatthetoolistryingtoaccomplish.
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DC
ConvertsadesigndescripJonwriWeninaHDL,intoanopJmizedgate-levelnetlistmappedtoaspecificlogiclibrary.WhenthesynthesizeddesignmeetsfuncJonality,Jming,power,andotherdesigngoals,youcanpassthedesigntoICCompilerforphysicalimplementaJon.
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LibertyTimingFile(LIB)The.libfileisanASCIIrepresentaJonoftheJmingandpowerparametersassociatedwithanycellinaparJcularsemiconductortechnology.TheJmingandpowerparametersareobtainedbysimulaJngthecellsunderavarietyofcondiJonsandthedataisrepresentedinthe.libformat.The.libfilecontainsJmingmodelsanddatatocalculate:
• �I/Odelaypaths• �Timingcheckvalues• �Interconnectdelays
I/OpathdelaysandJmingcheckvaluesarecomputedonaper-instancebasis.Pathdelaysinacircuitdependupontheelectricalbehaviorofinterconnectsbetweencells.ThisparasiJcinformaJoncanbebasedonthelayoutofthedesign,butmustbeesJmatedwhennolayoutinformaJonisavailable.Alsoitisnotpossibletopredicttheprocess,voltageandtemperaturevariaJonsandderaJngfactorscanbeincludedtocompensateforthesevariaJons.
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LibertyTimingFile(LIB)Cell-baseddelaycalculaJonismodeledbycharacterizingcelldelayandoutputtransiJonJme(outputslew)asafuncJonofinputtransiJonJme(inputslew)andthecapaciJveloadontheoutputofthecell.Eachcellhasaspecificnumberofinput-to-outputpaths• PathdelayscanbedescribedforeachinputsignaltransiJonthataffectsanoutputsignal• Thepathdelaycanalsodependonsignalsatotherinputs(statedependencies)
A
B
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Z
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LibertyTimingFile(LIB)
Input Slew
Delay,Power, Timing Checks
OutputCapacitance
Lookup-table(non-lineardelay)model.
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LibertyTimingFile(LIB)
Input Slew
Delay,Power, Timing Checks
OutputCapacitance
Lookup-table(non-lineardelay)model.
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Parameter VariaJonq Transistors have uncertainty in parameters
Process: Leff, Vt, tox of nMOS and pMOS Vary around typical (T) values
q Fast (F) Leff: short Vt: low tox: thin
q Slow (S): opposite q Not all parameters are independent
for nMOS and pMOS
nMOS
pMOS
fastslow
slow
fast
TT
FF
SSFS
SF
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EnvironmentalVariaJonq VDD and T also vary in time and space q Fast:
VDD: high T: low
Corner Voltage Temperature F 1.98 0 C T 1.8 70 C S 1.62 125 C
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ProcessCornersq Process corners describe worst case variations
- If a design works in all corners, it will probably work for any variation. q Describe corner with four letters (T, F, S)
- nMOS speed - pMOS speed - Voltage - Temperature
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ImportantCorners
Purpose nMOS pMOS VDD Temp
Cycle time S S S S
Power F F F F
Subthreshold leakage
F F F S
q Some critical simulation corners include
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DesignObjects
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TopLevelParJJoning
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DesignEnvironment
BeforeadesigncanbeopJmized,youmustdefinetheenvironmentinwhichthedesignisexpectedtooperate.YoudefinetheenvironmentbyspecifyingoperaJngcondiJons,systeminterfacecharacterisJcs,andwireloadmodels.OperaJngcondiJonsincludetemperature,voltage,andprocessvariaJons.SysteminterfacecharacterisJcsincludeinputdrivers,inputandoutputloads,andfanoutloads.Theenvironmentmodeldirectlyaffectsdesignsynthesisresults.
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DriveCharacterisJcs
TodeterminethedelayandtransiJonJmecharacterisJcsofincomingsignals,DesignCompilerneedsinformaJonabouttheexternaldrivestrengthandtheloadingateachinputport.Drivestrengthisthereciprocaloftheoutputdriveresistance,andthetransiJondelayataninputportistheproductofthedriveresistanceandthecapacitanceloadoftheinputport.DesignCompilerusesdrivestrengthinformaJontobuffernetsappropriatelyinthecaseofaweakdriver.Bydefault,DesignCompilerassumeszerodriveresistanceoninputports,meaninginfinitedrivestrength.
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DriveCharacterisJcs
Bydefault,DesignCompilerassumeszerocapaciJveloadoninputandoutputports.
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WireLoadModels
WireloadmodelsesJmatetheeffectofwirelengthandfanoutontheresistance,capacitance,andareaofnets.DesignCompilerusesthesephysicalvaluestocalculatewiredelaysandcircuitspeeds.Semiconductorvendorsdevelopwireloadmodels,basedonstaJsJcalinformaJonspecifictothevendors’process.Themodelsincludecoefficientsforarea,capacitance,andresistanceperunitlength,andafanout-to-lengthtableforesJmaJngnetlengths(thenumberoffanoutsdeterminesanominallength).
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DesignRuleConstraints
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DesignRuleConstraints
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MIPSLayout
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ICCTheICCompilertoolisasingle,convergentnetlist-to-GDSIIdesigntoolforchipdesignersdevelopingverydeepsubmicrondesigns.Ittakesasinputagate-levelnetlist,adetailedfloorplan,Jmingconstraints,physicalandJminglibraries,andfoundry-processdata,anditgeneratesasoutputaGDSII-formatfileofthelayout.
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ICCDesignFlow
Centeredaroundthreecorecommands.
• Createfloorplanandapowerplan.
• LegalizedplacementofleafcellsandresolvesJmingclosure.
• ImprovesclockskewandclockinserJondelay.
• PerformsglobalrouJng.
• Fillercells,Antennadiodes,densityfillsetc.
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DesignPreparaJonTheICCompilertoolusesaMilkywaydesignlibrarytostoreyourdesignanditsassociatedlibraryinformaJon.TheICCompilertoolrequiresbothlogiclibrariesandphysicallibraries.
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LogicLibrariesTheICCompilertooluseslogiclibrariestoprovideJmingandfuncJonalityinformaJonforallstandardcells.InaddiJon,logiclibrariescanprovideJminginformaJonforhardmacros,suchasRAMs.Thetoolsupportslogiclibrariesthatusenonlineardelaymodels(NLDMs)andCompositeCurrentSource(CCS)modelsandautomaJcallyselectstheJmingmodelstouse,basedonthecontentsofthelogiclibraries.
NLDMsdonotcontainenoughinformaJontocharacterizethedelayofagatedrivingacomplexRCinterconnectnetworkwiththeaccuracydesiredbysomeusers.Theyalsolacktheaccuracytofullycharacterizenoiseevents.
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PhysicalLibrariesTheICCompilertoolusesMilkywayreferencelibrariesandtechnologyfilestoobtainphysicallibraryinformaJon.TheMilkywayreferencelibrariescontainphysicalinformaJonaboutthestandardcellsandmacrocellsinyourlogiclibrary.TheMilkywaydatabasecancontaindifferentrepresentaJonsofthesamecell,called“views”ofthatcell.ThesearethemaintypesofviewsusedintheICCompilertool:•CELview:Thefulllayoutviewofaphysicalstructuresuchasavia,standardcell,macro,orwholechip;containsplacement,rouJng,pin,andnetlistinformaJonforthecell.•FRAMview:AnabstractrepresentaJonofacellusedforplacementandrouJng;containsonlythemetalblockages,allowedviaareas,andpinsofthecell.•FILLview:Aviewofmetalfill,whichisusedforchipfinishingandhasnologicfuncJon,createdbythesignoff_metal_fillcommandintheICCompilertool.•CONNview:ArepresentaJonofthepowerandgroundnetworksofacell,createdbythePrimeRailorICCompilertoolandusedbyPrimeRailforIRdropandelectromigraJonanalysis.•ERRview:AgraphicalviewofphysicaldesignruleviolaJonsfoundbyverificaJoncommandsintheICCompilertoolsuchasverify_zrt_routeorsignoff_drc.
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VerifyLibrariesToachievegoodresults,youmusthavehigh-qualitylibraries.Beforeyouprocessyourdesign,youshouldusethecheck_librarycommandtoensurethatthelogiclibrariesandphysicallibrariesarecorrectandconsistent.check_libraryverifiestheconsistencyofcellnames,pinnames,areavalues,busnamingconvenJons,operaJngcondiJonscaling,antennarules,andsoon.Itgeneratesadetailedreportonanyerrorsorinconsistenciesthatarefound.
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DesignPreparaJonReadingthedesignAnnotaJngtheFloorplaninformaJonCreaJngLogicalPowerandGroundconnecJon
• Aleryoureadinthedesign,youmustensurethattherearelogicalconnecJonsbetweenthepowerandgroundnetsandthepower,ground,andJe-offpinsonthecellsinyourdesign.
LinkingDesign• WhentheICCompilertoolperformsJminganalysis,eachcellinstanceinthedesignmustbelinkedtoacellinthelinklibraries,whichprovidesitsJminginformaJon.
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Placement&OpJmizaJonTherearemanyconfiguraJonsenngsthataffectthebehaviorofplacementandopJmizaJon.
PlacementKeepoutMargin:Akeepoutmarginisaregionaroundtheboundaryoffixedmacrosinyourdesigninwhichnoothercellsareplaced.
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Placement&OpJmizaJonGlobalKeepoutMargin
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Placement&OpJmizaJonAreabasedplacementblockages
TheICCompilertoolsupportsthefollowingtypesofarea-basedplacementblockages:•HardAhardblockagepreventstheplacementofstandardcellsandhardmacroswithinthespecifiedareaduringcoarseplacement,opJmizaJon,andlegalizaJon.•HardmacroAhardmacroblockagepreventstheplacementofhardmacroswithinthespecifiedareaduringcoarseplacement,opJmizaJon,andlegalizaJon.•SolAsolblockagepreventstheplacementofstandardcellsandhardmacroswithinthespecifiedareaduringcoarseplacement,butallowsopJmizaJonandlegalizaJontoplacecellswithinthespecifiedarea.•ParJalAparJalblockagelimitsthecelldensityinthespecifiedareaduringcoarseplacement,buthasnoeffectduringopJmizaJonandlegalizaJon.•PinApinblockagepreventstheglobalrouterfromrouJnginthespecifiedarea,andthepinplacerfromassigningpinstothearea.
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Placement&OpJmizaJonHighfanoutnetsynthesis
DuringplacementandopJmizaJon,theICCompilertooldoesnotbufferclocknetsasdefinedbythecreate_clockcommand,butitdoes,bydefault,bufferotherhigh-fanoutnets,suchasresetsorscanenables,usingabuilt-inhigh-fanoutsynthesisengine.
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PlacementAreaUJlizaJonU>liza>on
PlacementareauJlizaJon,orsimply“uJlizaJon,”meansthepercentageofareaavailableforplacementthatisalreadyoccupiedbyplacedcells.Forexample,auJlizaJonof80percentmeansthat80percentoftheavailableareaisoccupiedbycellsand20percentisemptyandcansJllbeusedforaddiJonalcellplacement,formovementofcellsforlegalizaJonandopJmizaJon,orasanallowancetopreventexcessiverouJngcongesJon.