Post on 27-Mar-2015
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DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005
2005 updates to the Lithography chapter of the ITRS
Lithography International Technology Working Group
July 2005
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DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005
Lithography ITWG chair persons and co-chair persons for 2005
Region Chair person Co-Chair personTaiwan Burn J. Lin G. C. HungJapan Isamu Hanyu Iwao HigashikawaKorea Han-Ku Cho
Europe Mauro Vasconi Jan-Willem GemminkUSA Scott Hector Maureen Hanratty
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DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005
Summary of 2004 Lithography Chapter Updates
• Defined more specific criteria for evaluating near-term potential solutions
• Stronger emphasis on difficult challenges related to immersion lithography
• Continued emphasis on challenges for implementing cost-effective post-optical lithography solutions
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DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005
Proposed 2005 Lithography Updates• CD control and line edge roughness (LER)
– Agreed along with Design, PIDS and FEP TWGs to increase CD tolerance to 12%
• CD control for MPU gates is still red (red starts at <4 nm 3)
– Agreed with FEP TWG on larger printed CD in resist• 1.6818physical gate length and 75%/25% variance allocation for
lithography and etch, respectively
– Proposed new definition of LWR and LER that better accounts for metrology, transistor and interconnect performance
– Increased bias between size in resist and after etch for contacts
• Significantly tighten overlay tolerances from 35% to 20% of DRAM ½ pitch
• Add lithographic tool field width and length • Update potential solutions• Update colors and values in mask and resist tables
Proposal only; Not for publication
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DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005
2005 ITRS lithography requirements are challenging
Manufacturable solutions exist, and are being optimizedManufacturable solutions are known
Interim solutions are known
Manufacturable solutions are NOT known
Year of Production 2005 2007 2010 2013 2016 2019DRAM ½ Pitch (nm) (contacted) 80 65 45 32 22 16
MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) 90 68 45 32 23 16MPU gate length in resist (nm) 54 42 30 21 15 11MPU Physical Gate Length (nm) 32 25 18 13 9 7Contact diameter in resist (nm) 111 84 56 39 28 20Contact diameter after etch (nm) 101 77 51 36 25 18Gate CD control (3 sigma) (nm) 3.3 2.6 1.9 1.3 0.9 0.7Overlay [A] 16 13 9 6.4 4.4 3.2Mask CD uniformity (nm, 3 sigma) isolated lines (MPU gates), binary mask [H] 3.8 2.6 1.3 1.0 0.7 0.5Line Width Roughness (nm, 3 sigma) <8% of CD ***** 3.6 2.8 2 1.4 1 0.8
Update
Update
Proposal only; Not for publication
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DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005
2005 updates to the chapter text
• Table showing progression of low k1 methods
• DFM section to complement content in Design chapter
• Automatic process control (APC) detail • Cost of ownership factors and throughput
factors described in text• Brief text about number of critical levels
Proposal only; Not for publication
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DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005
Criteria for potential solutions
• All infrastructure (masks, tools, resist,…) needs to be in place to meet the ramp for the specified node
• Technology must be planned to be used by IC makers in at least two geographical regions– For N+3 and later nodes with black coloring, the
requirement to have more than one region support is not applicable
• Technology should be targeting leading edge critical layer needs
• Consideration (not a requirement): 100 tools worldwide over the life of that tool generation (not for each node)
2004 Lithography exposure tool potential solutions
Notes: RET and lithography friendly design rules will be used with all photon projection lithography solutions, including with immersion; therefore, it is not explicitly noted.
Technology Node
2007 2013 20192004 20162010
hp90 hp65 hp32 hp16hp22hp45
Research Required
Development Underway
Qualification/Pre-Production
Continuous Improvement
DRAM Half-pitch(dense lines)
Tec
hn
olo
gy
Op
tio
ns
at T
ech
no
log
y N
od
es(D
RA
M H
alf-
Pit
ch,
nm
)90 193 nm
65193nm 193i with waterPEL? (decision by Sept.)
32
EUV193i with other fluids and lens materialInnovative 193i with waterImprint, ML2
22
16Innovative technology
Innovative EUV, imprint, ML2
45
193i with water193i with other fluids EUV, ML2EPL/PEL? (decision by Sept. 2005)
RET = Resolution enhancement technologyLFD = Lithography friendly design rulesML2 = Maskless lithography
Lithography Potential Lithography Potential Solutions Possible 2005 Solutions Possible 2005 Update from Spring iTWGUpdate from Spring iTWG
EUVInnovative 193 nm immersionImprint,ML2, innovative technology
Proposal only; Not for publication
DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005
90
50
40
30
20
100
80
7060
120140
65@2007
45@2010
32@2013
22@2016
90@2004
130@2001
Acknowledge: Kameyama, Nikon
History of ITRS Litho Potential Solutions
2001 Edition2001 Edition
ML2
EP
LEU
V
IPL PE
L PX
L
Innovatio
n
193n
m+
PS
M2
48
nm
+P
SM
15
7n
m+
PS
M
Imp
rint
2003 Edition2003 Edition
PEL
ML2
EP
L
Innovatio
n
EU
V+
RET
157n
m+
RET+
LFD
+Im
mers
ion
193n
m+
RET+
LFD
+Im
mers
ion
Innovatio
n
2005 Proposal2005 Proposal
19
3n
m
PEL
ML2
EP
L?
EU
VIm
prin
t
193n
m Im
mers
ion
?193i w
/ oth
er fl
uid
s
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DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005
Significant changes to potential solutions in 2005
• 193nm immersion with water and other fluids expected to be primary technology through 45nm and perhaps 32nm ½ pitch with new lens materials
• 157nm no longer seen as potential solution• EUV remains most likely next generation lithography
(NGL) with possible use starting at 45nm ½ pitch and primary solution for 32nm and 22nm ½ pitch
• Electron projection and proximity electron not as probable as in 2004
• Maskless lithography remains as potential solution starting at 45nm ½ pitch
• Imprint extended to cover 32nm through 16nm ½ pitch Proposal only; Not for publication
Resolution improvement by immersion
Silicon Wafer
Photoresist
Lens
sin4
1
sin4
1
sin4
1,
AIR
RESIST
RESISTAIR
RESIST
RESISTDRYMIN
n
n
HP
LIQUIDAIR
RESISTLIQUID
RESISTAIR
RESIST
RESISTWETMIN
n
nn
n
HP
sin41
sin4
1
sin4
1,
Liquid
Photoresist
Silicon Wafer
Lens
N water = 1.44
Enabling NA > 1.3
WaterImmersion
Fluid
Final Lens Element
Resist
1.4 1.5 1.6 1.7 Numerical aperture
High Index Fluid
Plano CaF2
or SiO2
High Index Lens Material
Curved Final Element
Existing Platforms
High Index Resist
Earlier increase in index of fluid and/or resist yields process latitude improvement
Acknowledge: Andrew Grenville
Extreme Ultraviolet Lithography(EUV)
Laser80
012.0 13.0 14.0nm)
Ref
. (%
)
40
All optics surfaces coated with multilayer reflectors (40 - 80 layer pairs, each layer approx /4 thick, Control ~0.1 Å)
Wafer
CondenserOptics4X Reduction
Optics
EUV imaging with ultrathin resist (UTR)
Laser ProducedPlasma
ReflectiveReticle
Ring Field IlluminationScanning mask and wafer stages Flat, square mask with multilayers
Reflective Optical Surfaces are Aspheric with Surface
Figures & Roughness < 3 Å
= 13.5 nm
35nm70nm
BIM PSM
Max
imu
m o
per
atin
g f
req
uen
cy
Static Idd
Present mode of operation for circuit design and fabrication
Organizational, corporate cultural and geographical
barriersDesignersWafer fab
Circuit architecture
Masks
LayoutTest data Packaged IC
Device models Design rules
New mode of operation with design for manufacturing (DFM) practices
Designers Wafer fab
Circuit architecture
Masks optimized based on design intent
Layout with critical paths 0.1
1
10
800 1000 1200 1400 1600 1800
BIM, ACI CD 78.7 nm
PSM, ACI CD 83 nm
BIM, ACI CD 74.6 nm
Sta
tic_I
DD
@ V
dd=
1.5
5V
Fmax 18:1 @ 1.48 V (MHz)
Packaged IC
Device models Design rules
Statistical timing
optimization
Cache
010203040
0.1
50
0.1
54
0.1
58
0.1
62
0.1
66
0.1
70
0.1
74
0.1
78
0.1
82
Fre
qu
en
cy
Process variation distributions
Known contours of CD, topography or overlay error with mfg. process
Test data
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DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005
Proposed Changes to ITRS Resist Tables
• Re-evaluated all colors in resist tables– Input from resist suppliers toward matching
capability (colors) with requirements (numbers)
– Re-examined defect size in resist films
• Back surface particle levels updated based on FEP values
• Improved LWR/LER definition and values
Proposal only; Not for publication
Importance of Line Edge and Width Roughness
• Line Edge Roughness (LER) (High frequency roughness)
– Can affect dopant concentration profiles
– Probably affects interconnect resistance
• Line Width Roughness (LWR) (Mid-frequency roughness)
– Leakage of transistors affected– Affects device speed of
individual transistors– Leads to IC timing issues
Fourier PSD, averaged
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E-03 1.E-02 1.E-01 1.E+00
f
PS
D [
nm
3]
PSD a
PSD b
PSD CD
Ben Bunday, SEMATECH
Example: poly-silicon line
Edge assignment from SEM algorithmLine
-20
0
20
40
60
80
100
120
140
160
0 200 400 600 800 1000scan
edge a corr
edge b adj
CD
Spatial frequency (nm-1)
LER
LWR
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DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005
Fringing Field Disorder
n+ n+
Gate
Rough Gate Edge
Junction edge fluctuations
Gate-SD Overlap disorder
Halo fluctuations
Poly s
Eric Verret, Aaron Thean and Jonathan Cobb; Freescale Semiconductor
Areas of potential device impact• Front end patterning
– LWR after etch is what matters, not LWR in resist
– LWR affects leakage current more strongly than drive current
Ioff
( nA
/ um
on
log
scal
e )
Ion ( uA / um )
L=50nm
L=40nm
L=32nm
Nominal device w/o LER
7nm 3 LER
Scaling relations for Table 77 and 79Item Value (in nm) where becomes: Yellow RedCD = Physical gate width = 0.4 DRAM ½ pitch 40 20Overlay = 20% DRAM ½ pitch 20 13Minimum linewidth in resist = 1.6818 physical gate 50 25Contact size after etch = 1.125 ½ pitch 85 60Contact in resist = 1.1 contact after etch 85 60CD control for DRAM = 13.5% sqrt(0.75) DRAM ½ pitch 7 4CD control for MPU/ASIC = 7 4
12% sqrt(0.75) MPU/ASIC M1 contacted ½ pitchMask nominal image size = MAG resist linewidth 200 130 SRAF feature is ½ of mask nominal image 130 100 Mask Min. Primary Feature Size = 200 130
0.7 Mask nominal image size Mask CD control = CD MAG sqrt(0.75) 4% / MEEF 8 5 Placement = Overlay MAG 15% 14 10Defect size = DRAM ½ Pitch MAG / 5 80 60Linearity = 3.8% DRAM ½ pitch MAG 15 10CD mean-to-target = 2% DRAM ½ pitch MAG 7 4Absorber LER = Min. CD MAG 3% 7 4Blank flatness 1/NA2 (250nm in 2007) 250 150Data volume = 2 increase / node (260 GB in 2004) 260 5000 GB
Proposal only; Not for publication
Update
DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005
20
DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005
Summary• 193nm immersion and EUV lithography are promising candidate
technologies for 45-nm and 32-nm half-pitch patterning– Significant challenges remain in developing either technology to provide
a timely, economical manufacturing solution
• Innovations in immersion, EUV and new techniques such as ML2 and imprint might become prevalent starting at 32-nm ½ pitch
• Maintaining ±10% CD control doesn’t appear to be possible, and ±12% adopted, ±12% still difficult to achieve
• More stringent overlay tolerances important for manufacturing of memory circuits
• Measuring and controlling LWR and LER becoming increasingly important
• Increasing integration of design, modeling, lithographic resolution enhancement techniques and extensive metrology will be needed to maintain expected circuit performance