Post on 05-Apr-2018
7/31/2019 Design With MOSFETs
1/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Chapter 02
Logic Design with MOSFETs
Introd uction to VLSI Circuits and Systems
Dept. of Electronic Engineering
National Chin-Yi University of Technology
Fall 2007
7/31/2019 Design With MOSFETs
2/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits Clocking and Dataflow Control
7/31/2019 Design With MOSFETs
3/51
Introduction to VLSI Circuits and Systems, NCUT 2007
p-n Junction A junction betweenp-type and n-type semiconductor forms a diode
Current flows only in one direction
anode cathode
P N
7/31/2019 Design With MOSFETs
4/51
Introduction to VLSI Circuits and Systems, NCUT 2007
nMOS Transistor
Four terminals: gate (G), source (S), drain (D), body (B)
Gateoxidebody stack looks like a capacitor
Gate and body are conductors
SiO2 (oxide) is a very good insulator
Called metal oxide semiconductor (MOS) capacitor
Even though gate is no longer made of metal
7/31/2019 Design With MOSFETs
5/51
Introduction to VLSI Circuits and Systems, NCUT 2007
nMOS Operation (1/ 2)
Body is usually tied to ground (0 V)
When the gate is at a low voltage
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
7/31/2019 Design With MOSFETs
6/51
Introduction to VLSI Circuits and Systems, NCUT 2007
nMOS Operation (2/ 2)
When the gate is at a high voltage
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from source through channel to drain,
transistor is ON
7/31/2019 Design With MOSFETs
7/51
Introduction to VLSI Circuits and Systems, NCUT 2007
pMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
7/31/2019 Design With MOSFETs
8/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits Clocking and Dataflow Control
7/31/2019 Design With MOSFETs
9/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Ideal Switches (1/ 3)
CMOS integrated circuits use bi-directional devices called MOSFETs as
logic switches
Controlled switches, e.g, assert-high and assert-low switches
An assert-high switch is showing in Figure 2.1
Figure 2.1 Behavior of an assert-high sw itch
(a) Open (b) Closed
7/31/2019 Design With MOSFETs
10/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Ideal Switches (2/ 3)
g = (a1)b = (a1)b
g = (a1) + (b1) = a + b
Figure 2.2 Series-connected switches
Figure 2.4 Parallel-connected switches
7/31/2019 Design With MOSFETs
11/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Ideal Switches (3/ 3)
Figure 2.5 An assert-low switch
(a) Closed
(b) Open
Figure 2.6 Series-connected complementary switches
Figure 2.7 An assert-low switchFigure 2.8 A MUX-based
NOT gate
7/31/2019 Design With MOSFETs
12/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits Clocking and Dataflow Control
7/31/2019 Design With MOSFETs
13/51
Introduction to VLSI Circuits and Systems, NCUT 2007
MOSFET as Switches
MOSFET: Metal-Oxide-Semiconductor Field-Effect
Transistor
nFET: an n-channel MOSFET that uses negatively
charged electrons for electrical current flow
pFET: a p-channel MOSFET that uses positive
charges for current flow
In many ways, MOSFETs behave like the idealized
switches introduced in the previous section
The voltage applied to the gate determines thecurrent flow between the source and drain terminals
Figure 2.9 Symbols used
for nFETs and pFETs
(a) nFET symbol
(b) pFET symbol
7/31/2019 Design With MOSFETs
14/51
Introduction to VLSI Circuits and Systems, NCUT 2007
MOSFET as Switches
Early generations of silicon MOS logic
circuits used both positive and negative
supply voltages as Figure 2.10 showing
In modern designs require only a single
positive voltage VDD and the ground
connection, e.g. VDD
= 5 V and 3.3 V or
lower
The relationship between logic variables
x and its voltages Vx
Figure 2.11 Single voltage pow er supply
Figure 2.10 Dual power sup ply voltages
(a) Power sup ply connection (b) Logic definitions
DDx VV 0
VVthatmeansx x 00 ==
DDx VVthatmeansx ==1
(2.14)
(2.15)
7/31/2019 Design With MOSFETs
15/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Switching Characteristics of MOSFET
In general,
The transition region between the highest
logic 0 voltage and the lowest logic 1
voltage is undefined
nFET
pFET
Figure 2.13 pFET switching characteristics
(a) Open (b) Closed
Figure 2.12 nFET switching characteristics
(a) Open (b) Closed
Low voltages correspond to logic 0 values
High voltages correspond to logic 1 values
1== AiffvalidiswhichAxy
0== AiffvalidiswhichAxy
(2.16)
(2.17)
7/31/2019 Design With MOSFETs
16/51
Introduction to VLSI Circuits and Systems, NCUT 2007
nMOS FET Threshold Voltages
An nFET is characterized by a threshold voltage
VTn that is positive, typical is around VTn = 0.5 V
to 0.7 V
If , then the transistor acts like an open
(off) circuit and there is no current flow between
the drain and source
If , then the nFET drain and source are
connected and the equivalent switch is closed (on)
Thus, to define the voltage VA that is associatedwith the binary variableA
Figure 2.14 Threshold voltage of an nFET
(a) Gate-source voltage
(b) Logic tran slation
TnGSn VV
TnGSn VV
GSnA VV = (2.20)
7/31/2019 Design With MOSFETs
17/51
Introduction to VLSI Circuits and Systems, NCUT 2007
pMOS FET Threshold Voltages
Figure 2.15 pFET threshold voltage
(a) Source-gate voltage
(b) Logic tran slation
An pFET is characterized by a threshold voltage
VTp that is negative, typical is around VTp = 0.5
V to 0.8 V
If , then the transistor acts like an open (off)
switch and there is no current flow between the drain
and source
If , then the pFET drain and source are
connected and the equivalent switch is closed (on)
Thus, to the applied voltage VA we first sum
voltage to write
TpSGp VV
TpSGp VV
DDSGpA VVV =+ VVA 0=
DDA VV =SGpDDA VVV =
(2.23)
(2.24)(2.26)
TpDD
VV (2.25)Note that the transition between a
logic 0 and a logic 1 is at (2.25) !
7/31/2019 Design With MOSFETs
18/51
Introduction to VLSI Circuits and Systems, NCUT 2007
nFET Pass Characteristics
An ideal electrical switch can pass any voltage
applied to it
As Figure 2.16(b), the output voltage Vy is
reduced to a value
Which is less than the input voltage VDD, called
threshold voltage loss
Thus, we say that the nFET can only pass a weak
logic 1; in other word, the nFET is said to pass a
strong logic 0 can pass a voltage in the range
[0, V1]
Figure 2.16 nFET pass characteristics
(a) Logic 0 transfer
(b) Logic 1 transfer
TnDD VVV =1 since TnGSn VV =(2.27)
7/31/2019 Design With MOSFETs
19/51
Introduction to VLSI Circuits and Systems, NCUT 2007
pFET Pass Characteristics
Figure 2.17(a) portrays the case where Vx =
VDD corresponding to a logic 1 input. The
output voltage is
Figure 2.17(b), the transmitted voltage can
only drop to a minimum value of
The results of the above discussion
nFETs pass strong logic 0 voltages, but weak
logic 1 values pFETs pass strong logic 1 voltages, but weak
logic 0 levels
Use pFETs to pass logic 1 voltages ofVDD
Use nFETs to pass logic 0 voltages ofVSS
= 0 V Figure 2.17 pFET pass characteristics
(a) Logic 0 transfer
(b) Logic 1 transfer
DDy VV =
Tpy VV = since TpSGp VV =
,which is an ideal logic 1 level(2.29)
(2.30)
7/31/2019 Design With MOSFETs
20/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits Clocking and Dataflow Control
7/31/2019 Design With MOSFETs
21/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Basic Logic Gates in CMOS
Digital logic circuits are nonlinear networks that
use transistors as electronic switches to divert one
of the supply voltages VDD or 0 V to the output
The general switching network
Figure 2.18 General CMOS logic gate
Figu re 2.19 Op erat ion of a CMOS logic gate
(a) f= 1 outpu t
(b) f= 0 outpu t
7/31/2019 Design With MOSFETs
22/51
Introduction to VLSI Circuits and Systems, NCUT 2007
The NOT Gate (1/ 2)
Figure 2.20 A comp lementary p air(b) x = 1 input (b) Tru th Table
(a) Logic symbol(a) x = 0 input
Figure 2.22 NOT gateFigure 2.21 Operation of
the comp lementary pair
7/31/2019 Design With MOSFETs
23/51
Introduction to VLSI Circuits and Systems, NCUT 2007
The NOT Gate (2/ 2)
Figu re 2.23 CMOS not gate (b) x = 1 input
(a) x = 0 input
Figure 2.24 Operation of
the CMOS NOT gate
7/31/2019 Design With MOSFETs
24/51
Introduction to VLSI Circuits and Systems, NCUT 2007
The NOR Gate (1/ 2)
(b) Truth Table
(a) Logic symbol (a) Logic diagram
(b) Voltage network
Figure 2.26 NOR2
using a 4:1 mu ltiplexorFigure 2.25 NOR logic gate
Figure 2.27 NOR2 gate
Karnaugh map
7/31/2019 Design With MOSFETs
25/51
Introduction to VLSI Circuits and Systems, NCUT 2007
NOR (2/ 2)
Figu re 2.30 NOR3 in CMOS
Figu re 2.28 NOR2 in CMOS
Figure 2.29 Operational sum mary of the NOR2 gate
7/31/2019 Design With MOSFETs
26/51
Introduction to VLSI Circuits and Systems, NCUT 2007
NAND (1/ 2)
(b) Tru th Table
(a) Logic symbol
(a) Logic diagram
(b) Voltage network
Figure 2.32 NAN D2
using 4:1 mu ltiplexor
Figure 2.31 NAND2 logic gate
Figure 2.33 NAN D2 K-map
7/31/2019 Design With MOSFETs
27/51
Introduction to VLSI Circuits and Systems, NCUT 2007
NAND (2/ 2)
Figure 2.36 NAND3 in CMOS
Figure 2.34 CMOS NAN D2 logic circuit
Figure 2.35 Operational sum mary of the NAND2 gate
7/31/2019 Design With MOSFETs
28/51
7/31/2019 Design With MOSFETs
29/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Complex Logic Gate (1/ 3)
Complex or combinational logic gates
Useful in VLSI system-level design
Consider a Boolean expression
Expanding by simply ANDing the result with a logical 1
1)]([)(
)(),,(
+=++=
+=
cbacba
cbacbaF
)(),,( cbacbaF +=
1)(1 += cbaF (2.51)
(2.50)
7/31/2019 Design With MOSFETs
30/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Complex Logic Gate (2/ 3)
Figu re 2.37 Logic function example
Figure 2.38 pFET circuit for F
function from equation (2.51)
Figure 2.39 nFET circuit for F
Figure 2.40 Karnau gh for nFET circuit
nFET array that
gives F=0 wh en
necessary
1)(1 += cbaF
7/31/2019 Design With MOSFETs
31/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Complex Logic Gate (3/ 3)
Figure 2.41 Finished complex
CMOS logic gate circuit
The characteristics of Complementary CMOS CMOS
0 ~ VDD
(full swing)
VDD
~ 0
()0VDD
CMOS(function)(mass production)(reliability)
(variation corners) (specifications)(margin)
7/31/2019 Design With MOSFETs
32/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Structured Logic Design (1/ 4)
CMOS logic gates are intrinsically inverting
Output always produces aNOT operation acting on the input variables
Figure 2.42 Origin of the inver ting
characteristic of CMOS gates
7/31/2019 Design With MOSFETs
33/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Structured Logic Design (2/ 4)
Figure 2.43 nFET logic formation
(a) Series-connected nFETs
(b) Parallel-connected n FETs
Figure 2.44 nFET AOI circuit
Figu re 2.45 nFET OAI circuit
7/31/2019 Design With MOSFETs
34/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Structured Logic Design (3/ 4)
Figure 2.46 pFET logic format ion
(a) Parallel-connected pFETs
(b) Series-connected pFETs
Figure 2.47 pFET arrays for AOI and OAI gates
(a) pFET AOI circuit
(b) pFET OAI circuit
7/31/2019 Design With MOSFETs
35/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Structured Logic Design (4/ 4)
Figure 2.48 Comp lete CMOS AOI and OAI circuits
(a) AOI circuit (b) OAI circuit
7/31/2019 Design With MOSFETs
36/51
7/31/2019 Design With MOSFETs
37/51
Introduction to VLSI Circuits and Systems, NCUT 2007
XOR and XNOR Gates
An important example of using
an AOI circuit is constructing
Exclusive-OR (XOR) andExclusive-NOR circuits
bababa +=
bababa +=
babababa +== )(
bababa += Figure 2.57 AOI XOR and XNOR gates
(a) Exclusive-OR (b) Exclusive-NOR
Figure 2.58 General naming convention
(a) AOI22 (b) AOI321 (c) AOI221
Figure 2.56 XOR
(2.71)
(2.72)
(2.73)
(2.74)
7/31/2019 Design With MOSFETs
38/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
The Fundamental MOSFETs
Ideal Switches and Boolean Operations
MOSFETs as Switches
Basic Logic Gates in CMOS
Complex Logic Gates in CMOS
Transmission Gate Circuits
Clocking and Dataflow Control
7/31/2019 Design With MOSFETs
39/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Transmission Gate Circuits
A CMOS TG is created by connecting an nFET and pFET in parallel
Bi-directional
Transmit the entire voltage range [0, VDD]
1== siffsxy (2.78)
Figure 2.60 Transmission gate (TG)
7/31/2019 Design With MOSFETs
40/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Analysis of CMOS TG (1/ 4)
Four representations of CMOS Transmission Gate (TG)
=)(,0
::
:
impedancehighZC
SignalControlCOutputB
InputA
AB =,1
7/31/2019 Design With MOSFETs
41/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Analysis of CMOS TG (2/ 4)
Case (A) Vin=Vdd, C=Vdd (Both transistors ON)
>
=
=
ntDDout
outDDngs
outDDnds
VVVoffTrun
operationNMOS
VVV
VVVNMOS
,
,
,
,.1
:
:
ntDDout VVVSaturation ,,.2 <
PMOS is always ON regardless of VoutValue
Summary of operating regions of MOS
Vout
Region I Region II Region III
0V |Vt,p| (VDD-Vt,n) VDD
nMOS: saturation
pMOS: saturation
nMOS: saturation
pMOS: linear reg.
nMOS: cut-off
pMOS: linear reg.
Total Current fromI/P to O/P: ID = IDS,n+ISD,pEquivalent resistance of NMOS and PMOS
Equivalent R of TG = reg,n// reg,p
psd
outDDp
nds
outDDn
I
VVreg
IVV
reg,
,,
,,
==
7/31/2019 Design With MOSFETs
42/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Analysis of CMOS TG (3/ 4)
Region (I): Vout < |Vt,p| {NMOS: saturation
PMOS: saturation
2,
)
2,
)(
(2,
)( )(2,
ptDDp
outDDp
ntoutDDn
outDDn
VV
VVreg
VVV VVreg
=
=
Region (II): |Vt,p| < Vout < (VDD-Vt,n) { NMOS: saturationPMOS: linear reg.
])())((2[)(2,
)()(2
,
2,
2,
outDDoutDDptDDp
outDDp
ntoutDDn
outDDn
VVVVVVVVreg
VVV
VVreg
=
=
(Vgs-Vt) Vds (Vds)2
Note:
NMOS source-to-substrate voltage
= VSB,n = Vout - 0 = Vout(Body Effect)
PMOS source-to-substrate voltage
= VSB,p = 0 - 0 = 0 (constant)
Vout
Region 1 Region 2 Region 3
0V |Vt,p| (VDD-Vt,n) VDD
nMOS: saturationpMOS: saturation
nMOS: saturationpMOS: linear reg.
nMOS: cut-offpMOS: linear reg.
7/31/2019 Design With MOSFETs
43/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Analysis of CMOS TG (4/ 4)
Region (III): Vout > (VDD-|Vt,p|) {NMOS: cut-off
PMOS: linear reg.
)()]()(2[
2,
,,
,
simplifyVVVV
reg
openreg
outDDptDDp
p
n
=
=
Total resistance of CMOS TG v.s. Vout
Equivalent resistance of TG is relatively
constant
Individual reg. of NMOS and PMOS arestrongly dependent on Vout!!
Vout
Region 1 Region 2 Region 3
0V |Vt,p| (VDD-Vt,n) VDD
nMOS: saturation
pMOS: saturation
nMOS: saturation
pMOS: linear reg.
nMOS: cut-off
pMOS: linear reg.
7/31/2019 Design With MOSFETs
44/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Logic Design using TG (1/ 3)
Multiplexors
TG based 2-to-1 multiplexor
The 2-to-1 extended to a 4:1 network by using the 2-bit selector word (s1, so)
sPsPF += 10 (2.79)
013012011010 ssPssPssPssPF +++= (2.80)
Figure 2.61 A TG-based 2-to-1 mu ltiplexor
7/31/2019 Design With MOSFETs
45/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Logic Design using TG (2/ 3)
TG based XOR/XNOR
TG based OR gate
bababa =+ babababa =+=
(2.81) (2.82)
ba
baa
baaaf
+=
+=
+= )(
(2.83)
Figure 2.62 TG-based exclusive-OR and exclusive-NOR circuits
(a) XOR circu it (b) XNOR circuit
Figu re 2.63 A TG-based OR gate
L i D i i TG (3/ 3)
7/31/2019 Design With MOSFETs
46/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Logic Design using TG (3/ 3)
Alternate XOR/XNOR Circuits
Mixing TGs and FETs which are designed for exclusive-OR and equivalence
(XNOR) functions Its important in adders and error detection/correction algorithms
Figure 2.64 An XNOR gate that used both TGs and FETs
7/31/2019 Design With MOSFETs
47/51
Cl k d D fl C l
7/31/2019 Design With MOSFETs
48/51
Introduction to VLSI Circuits and Systems, NCUT 2007
Clock and Dataflow Control
Synchronous digital design using a clock signal
Simply, the switching characteristics of TGs
As Figure 2.66(b), when TG is off, the value ofy =x for
a very short time thold. If we use a high-frequency clock
then the periodic open-closed change occurs at every
half clock cycle
Figure 2.65 Complementary clocking signals
Tf 1= (2.84)
Figure 2.66 Behavior of a clocked TG
(a) Closed switch
(b) Open switch
holdtT
7/31/2019 Design With MOSFETs
49/51
A S h i d W d Add
7/31/2019 Design With MOSFETs
50/51
Introduction to VLSI Circuits and Systems, NCUT 2007
A Synchronized Word Adder
In figure 2.69(a), the input word an-1a0 and
bn-1b0 are controlled by the plane,
while the sum sn-1s0 is transferred to theoutput when
Every bit in a word is transmitted from one
point to another at the same time, which allows
us to track the data flow through the system
In figure 2.69(b), a larger scale with the ALU
(arithmetic and logic unit)
Input A and B are gated into the ALU by the
control signal
The result word Out is transferred to the next
stage when , i.e.,
Figu re 2.69 Control of binary
word s using clocking p lanes
clock
0=
(a) Clocked adder
(b) Clocked ALU
plane
1= 0=
7/31/2019 Design With MOSFETs
51/51