Post on 18-Dec-2015
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FET (Field effect transistor)
• Two main groups
– JFET (junction FET)
– MOSFET (metal-oxide-semiconductor FET)
• Advantage
– extremely large input impedance
• Disadvantages
– Smaller gain (gm) than bipolar transistor
– More difficult to analyze
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JFET
• n-channel JFET
– just a slab of n-type semiconductor !!
• like transistor, the drain current is controlled by VGS
FET BipolarGate = baseSource = emitterDrain = collector
Gate
Source
Drain
I
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JFET
• n-channel JFET
– PN junction
– reversed biased
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JFET operation
• VGS=0– Max conducting channel, max
drain current ID
• VT <VGS < 0 – pn junction is reverse biased– reduce the conducting channel– reduce the drain current
• VGS < VT (Pinch-off voltage)– Further reduce VGS until the
depletion layer grows so wide that the channel is completely blocked
– ID=0
VG=0
PN
VS=0 VD
VT <VG<0
VS=0 VD
VG< VT
VS=0 VD
ID
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JFET as a voltage-controlled resistor
• If VDS is small
– VGS controls the channel width, and therefore the resistance
• JFET is a voltage-controlled resistor
VG
VSVD
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JFET as a voltage-controlled current source
• If VDS is large– the drain end is more reversed biased !– The channel is warped– Increase VDS => increase depletion reduce ID
– But increase VDS increase ID
• Net result– ID remains constant even VDS is increased
• A voltage-controlled current source
VG= -2V
VS=0 VD = 5VP
N-channel
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Saturation region
• Small VDS - linear region (voltage controlled resistor)
• Large VDS – saturation region (constant ID, voltage controlled current source)
Linear regionSmall VDS
JFET is likea resistor
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ID vs VGS (saturation region)
• IDSS – maximum current at VGS=0 (widest channel width,
smallest resistance)– different FET has different IDSS
IDSS
VP
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ID vs VGS
• The slope of ID vs VGS (gm) is less steep (not an exponential)
– smaller gm, not as good as bipolar transistor
• FET is difficult to analyze
– Bipolar is easier to analyze because VBE ~ 0.6V
– VGS can vary over a wide range, usually analyze by graphical method (load-line)
• The most important advantage
– Input is connected to an reversed biased pn junction
– Extremely high input impedance (IG~0)
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FET versus bipolar
• FET is similar to bipolar transistor
– Voltage-controlled current source
– bipolar circuits can be used by FET
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VDS
A simple current source
• What is VGS?
• What is ID?
• The simplest current source !
• But we cannot choose the current, as IDSS
may vary from transistor to transistor
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An adjustable current source
• Add a resistor RS so as to adjust ID
• Find by load-line (graphical) method
VSG= IDRS
VGS= -IDRS
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gm of FET
VT
Curve approx by a parabola2( )D GS TI V V
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Transconductance gm
• 2( )
2 ( )
D GS T
DGS T m
GS
I k V V
dIk V V g
dV
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k can be found by measuring gm at two points
• At VGS=0, measure gm (gm is maximum)
• Find VT (corresponds to gm=0)
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Typical value of gm at ID=1mA
• JFET ~ 2m A/V (from data book)
• bipolar ~ 40m A/V (by calculation gm=IC /25mV)
• Gain of bipolar is much higher than FET !
• Why use FET?
– extremely high input impedance
– almost zero input current
– good for picking up signal from source that has high source impedance
• e.g. microphones, input stage of oscilloscope
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Source Follower
• Same as emitter follower
• Output voltage (VS) follows input (VG)
– vG , iD , iDRS , vS
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Source Follower
• AC signal analysis
–
– if RSgm >> 1, then VG ~ VS good follower
– To have large RS, use current source (active load)
( )
(1 )
D m GS
m G S
S S D
S mS G
S m
i g v
g v v
v R i
R gso v v
R g
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Output impedance
• Fixed gate voltage, what is the output impedance
• model the gate-source section by a resistor
– vOUT / iD = rS = 1/gm (because vOUT ~ VIN)
• Typical value
– gm ~ 2m A/V, therefore rS ~ 500
• The output impedance of source follower (500) is much higher than emitter follower (25)
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Matched FET follower
• The follower is made of matched FET
– Q2 is a current source at VGS=0 and ID2=IDSS
– Q1 and Q2 are matched,
• Since ID1 = ID2 , therefore
VGS1= VGS2 = 0V (!)
• zero DC offset
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FET amplifier
• vG , iD , vOUT = -RDiD
– input and output are 180o out of phase, just like bipolar amplifier
• gain
– iD = gmvGS
– vD = -RDiD
= -gmRDvGS
• voltage gain = -gmRD
– same as bipolar amp except
gm is smaller
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FET amplifier
• DC bias
– VGS = -ID R
– use load-line to find the
best R for VGS and ID
R
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Hybrid op amp - best of both worlds
The tail,large impedancegives high CMRR
Mirror asactive load.High gain
Follower as buffer
amplifier
Push-pullclass B amp
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Voltage Regulators
• Input: unregulated power supply (voltage is quite constant but still has some ripple)
• Output: regulated (constant) voltage
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Voltage Regulator
• Regulator = Voltage reference + follower
– unregulated input provides the power
– zener diode (Vref) provides the voltage reference
– follower provides the output power and current
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Dropout voltage
• Dropout voltage
– difference between input and output voltage
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Dropout voltage
• For 723
– supply voltage of 9.5V (min) produces 5V output
– Large 4.5V dropout voltage (not good), waste power
– also requires too many external components
• Modern regulators
– dropout voltage ~ 2-3V
• Specialized low-dropout regulators
– dropout voltage ~ a few tenths of a volt
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723
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78xx family
• A modern regulator that you would use
– only need to provide a couple smoothing capacitors
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High current output
• Use parallel transistors to give high output current
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Thermal runaway
• Consider the bipolar transistors– different discrete transistor has different IC vs VBE
curve
– if one transistor conducts more current than the other
• the transistor gets hotter
• conduct more current !!
• which makes the transistor hotter still, develops a local hot spot, may eventually break down
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Thermal runaway
• The use of the resistor R in the emitter follower
– Negative feedback
– If a transistor gets hot and conducts more current
• VE is increased, providing a feedback voltage so that VBE is reduced, which reduces the current
• FET does not have the problem of thermal runaway
– Because FET has –ve temperature coefficient
– Increase in temperature reduces output current
– Really large power amplifiers can be built using MOSFET as the output stage
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Switching regulators
• Regulators powered by microprocessors
– run at 75%-90% efficiency, more efficient than traditional regulators
– transformer-less (so that the size is small)
– but more noisy (high frequency noise)
• Work by dumping charges into a capacitor via a switch
– charges stored in the capacitor give a constant voltage
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Switching regulators
Dump charge to cap
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MOSFET (Metal Oxide Semiconductor FET)
• Any current in the circuit below?
• No current
– one end must be reversed biased
p
n n
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MOSFET
• Basic principle - capacitive effect
+++++++++++++
- - - - - - - - - - - - -
metal
charge
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Enhancement MOSFET
• Add a metal gate
– Capacitive effect builds up a –ve charge channel that allows electrons to flow
p
n n
metalinsulator
gate
source drain
- - - - - -- - - - - -
-ve charge, conducting channel
body
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NMOS (n-channel MOS)
• when gate voltage is zero, no drain current
• drain current increases as gate voltage increased
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Enhancement mode and depletion mode
• Enhancement mode operation
– No gate voltage, no conduction
– Increase gate voltage increases the conduction
• JFET
– Depletion mode
– no gate voltage, conduction is at its maximum
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Enhancement MOSFET
• if VDS is small – VGS controls channel width– IDS VDS
– behaves as a variable resistor
• Large VDS – VDS increase, drain becomes more positive– conducting channel becomes less -ve charged to the point that it
will almost be vanished– Channel is warped
• Saturation– increase in VDS also increase drain current but offset by the
reduction in channel– Constant ID over a range of VDS
- - - -- - -- - 0V
3V5V
warped
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With PMOS (p-channel MOS)
• Works in opposite polarity
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MOSFET symbol
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Digital circuits
• Logic gates
– the fundamental building block of digital electronics
– AND, OR, NAND, NOR, INVERTER
– with these gates, one can build adder, shifter, multiplier, logical unit, memory, and microprocessors
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Inverter gate
ON. Channel is conducting,drain is shorted to ground,VOUT = 0
OFF. Channel is non-conducting,ID=0, VOUT = VDD
Output impedanceat OFF state
• NMOS (n-channel MOSFET) inverters
VOUT
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Drawback of NMOS
• ON state
– draw current though R, large static power dissipation
• OFF state
– Large output impedance = R
– Large R gives small output current, which slows the switching speed of the circuit
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Problems of NMOS
• Large RD takes longer to charge up Cstray
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CMOS inverter (Complementary MOSFET)
• PMOS + NMOS
• Input = 0V, Output = 5V
– for NMOS (bottom one)
• VGS=0V, OFF
• (open circuit)
– for PMOS
• VG= 0V, VS= 5V
• VGS= -5V, ON
• (Short circuit)
(5V)
VGS = -5V
VGS = 0V
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CMOS inverter (Complementary MOSFET)
• PMOS + NMOS
• Input = 5V, Output = 0V
– for NMOS (bottom one)
• VGS=5V, ON
• (short circuit)
– for PMOS
• VGS= 0V, OFF
• (open circuit)
(5V)
VGS = 0V
VGS = 5V
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CMOS
• Output impedance– Either the PMOS or the NMOS is short– Zero , tiny RC, fast switching
• Static power consumption– output = 5V
• NMOS (bottom) is open circuit, draw no current• PMOS is short, draw no voltage• Power = VI = 0
– output = 0V (same, power=0)– ideal for low power applications
• e.g. mobile phone, notebook PC
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Dynamic power dissipation
• Dynamic power dissipation
– Power consumes when there is a change of state
– 01 or vice versa
• CMOS draws power when the MOSFET is changing state
– Both MOSFETs are partially conducting
– Charging up the stray capacitor of next stage consumes energy
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Both MOSFETs are conducting
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CMOS - capacitive charging current
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Dynamic power dissipation
• Let the total stray capacitance = C– Energy needs to charge up C =– Energy needs to discharge C =
• Total energy needs per cycle =
• Total energy dissipation per second =
• High clock rate hotter and need larger heat sink
• To reduce power– Reduce power supply voltage V– Reduce frequency (e.g. asychronous IC)
212 CV
212 CV
2CV
2 f CV
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Why digital circuits use CMOS
• Extremely small output impedance
• Zero static power dissipation
– No change of state, don’t consume power
• can go all the way to 0V
– bipolar can only go as low as 0.2V (min VCE)
• Simpler processing higher yields, lower costs
• Smaller size smaller capacitance higher speed
• The main problem is dynamic power dissipation
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CMOS NAND gate
• NAND gate can be used to build all other gates
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Flash memory
• Non-volatile memory for NMOS and CMOS
• Add a floating gate
– A layer of oxide sandwiched between insulators
p
n n
insulator floating gate(layer of oxide)
source drain
- - - - - -- - - - - -
body
Control gate
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Operation
• To store logic 1– The oxide layer contains no charge– positive voltage at the control gate will turn ON the
MOSFET
• To store logic 0– Apply a high voltage (20V) across the floating gate– Breakdown the insulator, electrons trapped in the
oxide layer– The electrons stored act as a screen, positive voltage
at the control gate cannot turn ON the MOSFET (MOSFET is OFF)