Post on 03-Feb-2022
CPU testing & testable Design .1
CPU Testing & Testable Design
• Problems in CPU Testing• Test Strategies for CPU• Testable CPU Architectures• Testable Design Flow
CPU testing & testable Design .2
Problems in CPU Testing
! Large number of registers! Large number of small buffers or queues! Different sizes of memories! Complex random logic (control path & data
path)! Cell library! Board level testing! Test control! Test integration & Scheduling! CAD tool supporting
CPU testing & testable Design .3
Test Strategies
! Design hierarchy & Circuit partitioning! BIST for large memories / arrays! Special BIST for small buffers! Scan for random logic! Shadow registers where necessary! Boundary Scan for test control and board
level testing! Functional testing! Testable design rules! CAD tool usage
CPU testing & testable Design .4
Design Hierarchy &Circuit Partitioning
! Represent the design in a hierarchy fashion! Try to identify all the bottom components! Identify test strategy for each bottom
component! Go up the hierarchy from the bottom
component, determine test strategy for thecircuitry between components
CPU testing & testable Design .5
Example: a simple pipelined CPU
! 4-level hierarchy! 5 functional units
��
����
��- IFU: instruction fetch unit - CU: control unit - BU: bus unit - RFU: register file unit - EU: execution unit
CPU testing & testable Design .6
Example: a simple pipelined CPU(cont.)
CHIP
IFU CU BU RFU EU
PC ROM IR OIR PSRALU
BYPASS LOGIC SHIFT ARITHMETIC
CPU testing & testable Design .7
BIST for Large Memories / Arrays
! Use BIST for all large memories! Test all memories in parallel! Deal with memories with different sizes! Deal with memories with different widths of
cells! Use one test controller
CPU testing & testable Design .8
Memory BIST Architecture with aCompressor
MemoryModule
di
addr
wen
data
sys_disys_addrsys_wen
MemoryModulerst_l
clkhold_l
test_hsise
data
q
so
Before After
CPU testing & testable Design .9
Memory BIST Architecture with aCompressor (cont.)
BIST Circuitry
MemoryModule
Alg
orith
m-B
ased
Patte
rn G
ener
ator
Com
pres
sor
diaddrwen
data
compress_h
sys_addrsys_disys_wen
rst_lclk
hold_ltest_h
q
so
clkrstsise
CPU testing & testable Design .10
Three Memories and OneCompressor
ROM4KX4Module
addr1 data
compress_h
sys_addr1
sys_di2sys_wen2
rst_l clkhold_ltest_h
Compressorqsosi
se
RAM8KX8Module
di2addr2wen2 data
RAM8KX8Module
di3addr3wen3
data
BISTCircuitry
Alg
orith
m-B
ased
Patte
rn G
ener
ator
sys_addr3
sys_addr2
sys_wen3sys_di3
4
8
8
CPU testing & testable Design .11
Small Buffer Testing
! Several FIFOs reside in a superscalar CPU− Instruction queue− Reorder buffer− Reservation station
! Memory cells as well as the control logic forthese cells must be tested
! Need a special test architecture to test thesebuffers
CPU testing & testable Design .12
Parallel Test Architecture forSmall Buffers
Address Control Data
FIFO1
Serial
FIFO2
Serial
FIFO3
Serial
Multiple Input Signature Register
bistdoneBIST circuit
CPU testing & testable Design .13
Scan for random logic
! Scan cell design! Full scan v.s. partial scan! Single scan chain v.s. multiple scan chain! Test control and scheduling
CPU testing & testable Design .14
Scan Cell Design
DI
DI
D Q
CK
DI D Q Q,SOSI
MU
X
CKN/T(SE)
DIQ,SO
SI
ΦΦΦΦT
ΦΦΦΦ
ΦΦΦΦTΦΦΦΦ +
Q
ΦΦΦΦ
ΦΦΦΦ
Q
CPU testing & testable Design .15
A possible method to drive multiplescan chains using a data input
TDI
TDO
TAP
CK
T_AC
KT_A
CK
T_BC
KT_B
MISR
Scan_In
CK
T_CC
KT_C
CPU testing & testable Design .16
Boundary scan for test controland board level testing
! Must provide test control signals and test data for - Scan testing (including shadow registers) - BIST - Small buffer testing - Any ad hoc techniques
! Must define some new Boundary Scan instructions
! Must determine required TMS signals
CPU testing & testable Design .17
Functional testing
! Several circuitry, especially some interconnectionsare not tested by component testing
- interconnections network - Interface between register file and ALU or other logic - Bus Interface unit - Cache control logic - Global chip function! Functional testing is carried out by executing a
sequence of instructions
CPU testing & testable Design .18
An example of functional testingfor cache control
For functional fault - Cache always miss
10 0 1Tag=ATag=ATag=ATag=A
0 0Tag=A Tag=A
Cache(enable)
Main Memory
Initial state
Cache(disable)
Main Memory
(write 1 of tag A )
Fault activation
Processor
0 1
Cache(enable)
MainMemory
Fault detection
( read different datainto processor)
CPU testing & testable Design .19
Testable design rules andrequirements
! Important for full-custom design! All custom design must have a corresponding
Verilog RTL code! If DFT circuitry is added by tools, then usually the
rules are satisfied
CPU testing & testable Design .20
Some design rules
(1) Synchronous design ONLY except reset
(2) Avoid gated clocks
(3) Must be able to break global feedback loop
(4) SET/RESET must not be driven by other FF/s
(5) ROM and RAM must be isolatable during testing
CPU testing & testable Design .21
CAD Tools Usage
! Should try to use tools wherever possible! Comparison between - Syntest - Mentor Graphics - Synopsys! Usually tools are not turn-key solutions, much
human work has to be done to generate - Data files - Control files - Interface between tools
CPU testing & testable Design .22
Testable CPU architecture
! A generic global CPU test architecture
! A simple pipelined CPU
! Test control architecture for the pipelined CPU
CPU testing & testable Design .23
A Global Test Control Architecture
CompressorRegister
S3
Data Scan Chain
PRPG BIST Core MISR
PRPG/Signature Analyzer
Shadow Register
BypassRegister
IRDecoder
TAP Controller
Combinational
PRPG BIST Core MISR
PRPGBIST Core
PRPG/Signature AnalyzerBIST Core
S1
S5
TDOTDI
TCK
TMS
BIST setupRegister
Boundary ScanRegister
Data Scan Register
S2
S4
CPU testing & testable Design .24
Boundary ScanInstruction Set
! 2 classes, 9 instructions
Class Group Instruction Opcode Target register
BYP AS S 000 0 Bypass register
SAM./P RELO AD 000 1 Boundary scan register
M andatory
EX TES T 111 1 Boundary scan register
CLAM P 001 0 Bypass register
IE EE
11 49.1
Instruction
Optional
HI G HZ 001 1 Bypass register
S H AD O W SHASCAN 010 0 Shadow register
SCAN IN SCAN 010 1 Data scan chain
S ETBIS T 0110 Setup scan chain
User
defined
instruction BIS T
R UNBIST 0111 Compressor register
CPU testing & testable Design .25
A Simple Pipelined CPU! Input pins: CLK, RESET, INIT, SWITCH! Output pins: HALT, STORE, MEM_ADDR,
MEM_OUT
OIR
IR
ROM
PC
CU
BU
FRU
ALU
PSR
IFU
EU
CLK
RESET
INIT
SWITCH
HALT
STORE
MEM_ADDR[3:0]
MEM_OUT[31:0]
CPU testing & testable Design .26
Instruction SetClass Inst. Opcod
eFormat Description
NOP 0000 NOP No operationCTLHALT 1111 HALT Halt system
0010 LOAD DST, #n Load constant to registerLOAD0010 LOAD Load mem data to register
0011 STORE mem, #n Store constant tomemory
DST,[mem]LD/ST
STORE0011 STORE mem,
SRCStore register data tomemory
AND 1100 AND DST, SRC SRC & DST to DSTOR 1101 OR DST, SRC SRC | DST to DSTXOR 1110 XOR DST, SRC SRC ^ DST to DSTLSF 1000 LSF DST, SRC SRC << DST to DST
LOGIC
RSF 1001 RSF DST, SRC SRC >> DST to DSTBRA 0001 BRA LABEL Branch to label alwaysBRN 0001 BRN LABEL Branch to label if
negativeBRZ 0001 BRZ LABEL Branch to label if zeroBRP 0001 BRP LABEL Branch to label if parityBRE 0001 BRE LABEL Branch to label if even
BRANCH
BRC 0001 BRC LABEL Branch to label if carryADD 0100 ADD DST, SRC SRC + DST to DSTSUB 0101 SUB DST, SRC SRC - DST to DSTARITH.MUL 0110 MUL DST,SRC SRC * DST to DST
CPU testing & testable Design .27
Test Strategy
Blocks Component Architecture Test strategyPC Random logic gates ScanROM Memory elements BISTIR Register Scan
IFU
OIR Register ScanALU Combinational gates ScanEUPSR Register Scan
FRU R_FILE Memory elements BISTCU CU Combinational gates ScanBU BU Random logic gates Scan
Shadow SamplingShadowRegister
ShadowRegister
RegisterScanBoundary ScanCHIP CPU Complex circuit designFunctional testing
CPU testing & testable Design .28
CPU Test Control Architecture
Shadow Register
BypassRegister
IR Decoder
TAP Controller
TDOTDI
TCK
TMS
PRPG ROM MISR
CU and ALU
PC IR OIR PSR BU
PRPG RegisterFile
MISR
CPU testing & testable Design .29
Boundary Scan Instruction Set
! 2 classes, 8 instructions
Class Group Instruction Opcode Target registerBYPASS 0000 Bypass register
SAM./PRELOAD 0001 Boundary scan registerMandatory
EXTEST 1111 Boundary scan registerCLAMP 0010 Bypass register
IEEE1149.1Instruction
OptionalHIGHZ 0011 Bypass register
SHADOW SHASCAN 0100 Shadow registerSCAN INSCAN 0101 Data scan chain
Userdefinedinstruction BIST RUNBIST 0110 Compressor register
CPU testing & testable Design .30
Testable Design Flow
! Traditional design flow
! Testable design flow at gate-level
! DFT instruction phases
! Testable design flow at RTL/gate level
! Automatic DFT insertion
! Test Scheduling
CPU testing & testable Design .31
External Spec.Instruction set
Golden DeviceBehavioral Level
Requirement
RTL Model
DFT Insertion
Synthesis to LayoutPost-Layout Simulation
Production of chip
System at Work
Internal Spec.Architecture
Synthesis to GateGate Level Simulation
Traditional Design Flow (cell-based)
CPU testing & testable Design .32
Testable Design Flow (gate-level)Requirement
ExternalSpec.
Instruction set
Golden DeviceBehavioral
Level
InternalSpec.
Architecture
RTL Model
DFT Insertion
Synthesis to LayoutPost-Layout Simulation
Production of chip
System at Work
Test
Pro
gram
s an
d Te
st P
atte
rns
Synthesis to GateGate Level Simulation
Choose TestStrategies
Insert/VerifyBIST Circuit
Synthesize/Optimize Design
TestabilityAnalysis
Insert ShadowRegister
Synthesize/Optimize Design
MBISTArchitect
Design Compiler
Shell Script
Design Compiler
Verilog XL
FastScan
Test Compiler
Shell Script
Design Compiler
Insert InternalScan Circuit
Insert/VerifyBoundary Scan
Integrate DFTCircuits
Synthesize/Optimize Design
FunctionalTesting
Generate/VerifyTest Patterns
DFTadvisor
BSDArchitect
CPU testing & testable Design .33
DFT Insertion Phase! Choose test strategy! Insert/Verify BIST circuit! Synthesize/optimize design! Testability analysis! Insert shadow register! Insert internal scan circuit! Synthesize/optimize design! Insert/Verify Boundary Scan! Integrate DFT components! Synthesize/optimize design! Functional testing! Generate/verify test patterns
CPU testing & testable Design .34
Memory BIST Insertion! Automatic RTL BIST insertion! MBISTArchitect and batch program
Library
rom.v rom_tb.v rom_con.v rom_bist.v rom_comp.v
test_rom.v top.v
SectionOver
top_gate.vCompassLibrary
MBIST
RTL SimulationSynthesis ProcessDesign Compiler
Gate Level Simulation Compare
rom_gate.v
rom_mbist.do
mod_tv.awk mod_con.awk
dc_script
CPU testing & testable Design .35
Shadow Register Insertion
! Test points selection" Testability analysis
- Gate level- Test Compiler
Circuit characteristic! Automatic shadow register insertion! Shadow register generator
C-shell script! RT-level insertion
CPU testing & testable Design .36
Scan Chain Insertion
! Automatic scan chain insertionGate levelScan cell identificationScan cell connection
! DFTAdvisor or Test Compiler328 scan cells
CPU testing & testable Design .37
Testable Design Flow (RTL/Gate)Requirement
ExternalSpec.
Instruction set
Golden DeviceBehavioral
Level
InternalSpec.
Architecture
RTL Model
DFT Insertion
Synthesis to LayoutPost-Layout Simulation
Production of chip
Choose TestStrategies
Insert/VerifyBIST CircuitInsert/Verify
Boundary ScanSynthesize/
Optimize DesignTestabilityAnalysis
Insert ShadowRegister
Synthesize/Optimize Design
Insert InternalScan Circuit
Integrate DFTCircuits
Synthesize/Optimize Design
FunctionalTesting
Generate/VerifyTest PatternsSystem at Work
Test
Pro
gram
s an
d Te
st P
atte
rns R
TL M
odel
MBIST
BSDArchitect
Test Compiler
Shell Script
DFTAdvisor
Design Compiler
Shell Script
Verilog XL
FastScan
Gat
e Le
vel
Design Compiler
Design Compiler
CPU testing & testable Design .38
Automatic DFT Insertion! Programs list
Step Programs FunctionsTest Program program_gen Code translation
NOP insertionDesign Compiler Pipelined CPU SynthesisBatch FilesMBISTArchitect BIST synthesismon_tn.awk Test fixture modificationmon_con.awk Top module modificationDesign Compiler Synthesis/Optimization
BIST Insertion
Batch files Batch executionTestability analysis Test Compiler Testability analysisShadow RegisterInsertion
shadow_gen Shadow Registersynthesis
DFTAdvisor Scan chain synthesisScan Chain InsertionBatch file Batch executionBSDArchitect Boundary Scan
synthesisBoundary Scan Insertion
Batch file Batch executionDFT Integration dft_gen DFT integrationTest Fixture Generation fixture_gen Test fixture generation
FastScan Test patterns generationTest Patterns GenerationBatch file Batch execution
Tutorial Demo Program dft_tutorial Tutorial demo program
Synthesis/OptimizationBatch execution
CPU testing & testable Design .39
Test SchedulingStart
BSComponents
BS PublicInstructions
BISTTesting
Scan Testing
ShadowSampling
NormalTesting
END
Diagnostics
Diagnostics
Diagnostics
Diagnostics
P
P
P
P
P
P
P
F
F
Y
N
N
F
YF
Y
F
Y
F
N
N
CPU testing & testable Design .40
ConclusionsMost important tasks in CPU testing! Design partition - RTL codes! Test training course! Design rules / constrains! Test architecture decision! Close link between design team and test team! Good management for coordination! Test integration! Functional testing