Universally Testable AND-EXOR Networks

Ugur Kalay,Marek Perkowski, Douglas Hall

Universally Testable AND-EXOR NetworksUniversally Testable

AND-EXOR Networks

Portland State University

Speaker: Alan Mishchenko

2

AgendaAgenda

• Introduction– desired properties of a test set

– testing AND and EXOR gates

– test scheme proposed by Reddy

• Testing Two-level AND-EXOR Networks– implementation of the new testing scheme

– experimental results

• Testing Multi-Level AND-EXOR Networks– extending the scheme for multi-level circuits

• Conclusions and Directions of Future Research

3

• 100% Fault Coverage– no fault simulation

• Minimal (as few tests as possible)– shorter testing time

• Universal (does not depend on the circuit)– portability of the pattern generator

– reduced engineering

• Regular (test patterns have certain structure)– simpler pattern generator

• Good Scalability– easy pattern generator expandability

IntroductionIntroduction

Requirements for a Test Set

4


Testing AND gate

TestsFaults

1 2 3 4

a b c sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1

1 1 1 + + + +

0 1 1 + +

1 0 1 + +

1 1 0 + +

1

2

3

4abc

5


Testing EXOR gate

Inputs Class A Class B

a b g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 g12 g13 g14 g15 g16

0 0 0 0 0 0 1 1 1 0 0 1 0 0 1 1 1 1

0 1 1 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0

1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 0 1 0

1 1 0 0 0 1 0 0 1 0 1 0 1 1 1 0 1 1

a b Faults detected

0 0 g5, g6, g7, g10

0 1 g2, g3, g4

1 0 g8, g11

1 1 g9

ag

b

6

x1x2x3

fx0

• Reddy’s Positive Polarity Reed-Muller Testing Scheme

Example: f = x1x2 x1x3 x1x2x3

x0 x1 x2 x3 x0 x1 x2 x3

0 0 0 0 - 0 1 1

T1= 0 1 1 1 T2= - 1 0 1

1 0 0 0 - 1 1 0

1 1 1 1

-: don’t care

* Large expression leads to long EXOR cascade


* 100% Single Stuck-at Fault Coverage

* Minimal (C = n + 4)

* Universal

* Regular Patterns

* Linear increase

7

• Other Reed-Muller Canonical FormsPPRM (Positive Polarity Reed-Muller)

x1x2x3 x1x2

FPRM (Fixed Polarity Reed-Muller)

x1x2x’3 x2x’

3

GRM (Generalized Reed-Muller)

x1 x2 x’2x’

3

• Free ExpressionESOP (EXOR-Sum-of-Products)

x1x2x3 x’1x’

2x’3

PPRMFPRMGRMESOP


8

• Comparison of the Number of Product Terms:

Function PPRM FPRM GRM ESOP SOP

adr4 34 34 34 31 75

log8 253 193 105 96 123

nrm4 216 185 96 69 120

rdm8 56 56 31 31 76

rot8 225 118 51 35 57

sym9 210 173 126 51 84

wgt8 107 107 107 58 255


9

c1 c2 x1 x2 x3 … xn

0 0 0 0 0 … 00 0 1 1 1 … 10 1 0 0 0 … 00 1 1 1 1 … 1

T = 1 0 0 0 0 … 01 1 1 1 1 … 10 - 0 1 1 … 10 - 1 0 1 … 1

…

0 - 1 1 1 … 0

* Perfect for BIST !

x1x2

xn

f

ANDPart

L itera lPart

c2

...

...

. . .

...

. . .

c2

c1

o2

LinearPart

CheckPart

...o1A

c1

B

Testing Two-level AND-EXOR NetworksTesting Two-level AND-EXOR Networks

* 100% single stuck at faults* Minimal C = n + 6

* Universal

* Regular

* Linear size increase

10

• much shorter test cycle than pseudo-random and pseudo-

exhaustive test sets

• better fault coverage than a pseudo-random test set

• no test point insertion required

• a fixed, simple, and easily expandable pattern generator


Advantages of deterministic testing for ESOP

11

Correct Signature Compare accept / reject

f o1 o2

ESOP DeterministicPattern Generator


PRPG

Circuit Under Test

MISR

EDPG

Easily Testable 2-level ESOP Network

• Built-in Self-Test Circuitry for ESOP Networks

12

• ESOP Deterministic Pattern Generator

Q

QS E T

C L R

D

Q

QS E T

C L R

D

Q

QS E T

C L R

D...

Q

QS E T

C L R

D

...

FSM

Rst

Clk

c1 c2 x1 x2xn-1 xn

Part II

Part I


• Linearly expandable

• No initialization seed & circuitry

• Much shorter cycle than a PRPG

• Comparable size to PRPG (see later)

13

• FSM (Part II) for EDPG

Reset

TestVector 1

TestVector 2

TestVector 3

Stop

TestVector 6

TestVector 5

TestVector 4

Q

QS E T

C LR

D

Q

QS E T

C LR

D

Q

QS E T

C LR

D

c1

c2

SETCLR

Vcc

Rst

Clk


14

• Comparisons of the number of test vectors for 100% single stuck-at fault fault coverage

Multi-level implementation Our ESOP

Implementation Pseudo-random Test Generation (LFSR)

Algorithmic Test Generation (SIS)

Our Test Scheme Circuit Num. of Primary Inputs

#Tests Undetected Total Faults

Fault Coverage

#Tests Fault

Coverage #Tests

Fault Coverage

9symml 9 512 0 513 100 137 100 15 100

adr4 8 96 0 146 100 37 100 14 100

alu2 10 864 0 664 100 117 100 16 100

alu4 14 10K 108 4158 97.4 961 100 20 100

apex6 135 10K 27 1680 98.3 400 100 141 100

ex4 128 10K 92 1042 91.1 474 100 134 100

f51ml 8 256 0 465 100 101 100 14 100

mux 21 320 0 104 100 53 100 27 100

rd73 7 128 0 341 100 78 100 13 100

x1 51 10K 50 1342 96.2 301 100 57 100

x4 94 3744 0 991 100 280 100 100 100

x9dn 27 10K 129 480 73.1 126 100 33 100


Experimental Results

15

• Comparisons of the number of test vectors for 100% single stuck-at fault fault coverage (cont…)

CircuitNum. ofPrimaryInputs

Algorithmic /Ordinary

ESOP

Our Scheme /ESOP with

DFT

9symml 9 181 15

a04 9 173 15

alu1 12 8 18

alu2 10 133 16

alu4 14 1174 20

dk16 7 77 13

mux 21 48 27

rd73 7 48 13

rd84 8 62 14

sse 11 60 17

x2 10 27 16


16

• Area and delay comparisons (LSI Logic Corp., 0.5 micron)Multi-level

Using Allcomponents

Using AND2,OR2, INV

2-level

SOP

Our

ESOPCircuitNum. ofPrimaryInputs

Num. ofPrimaryOutputs

Area Delay Area Delay # Terms Area Delay # TermsArea

(Function)Area

(DFT)Delay

9symml 9 1 193 3.21 598 4.04 87 1042 10.88 51 803 27 7.32

adr4 8 5 62 1.07 153 1.65 75 706 9.44 31 245 24 4.44

alu1 12 8 31 0.58 101 0.91 19 80 2.47 16 108 36 2.35

alu2 10 6 315 8.07 800 10.97 260 3952 31.92 69 925 30 9.77

alu4 14 8 1800 11.38 6020 14.75 1138 20834 137.56 455 9099 42 60.12

apex5 117 88 1833 7.68 5026 9.37 1216 14,582 147.51 399 7577 351 53.68

apex6 135 99 686 3.03 1754 4.73 657 7604 80.01 408 5636 405 54.54

ex4 128 28 431 1.94 1231 2.90 559 7416 67.66 317 5975 384 42.43

f51ml 8 8 184 2.91 566 3.99 97 1052 12.22 31 253 24 4.58

mux 21 1 36 1.7 120 2.34 16 190 2.36 16 208 63 2.6

rd73 7 3 174 3.07 560 5.33 187 2374 22.91 41 357 21 5.88

x1 51 35 308 1.31 673 2.05 324 4294 39.88 414 9402 153 55.46

x2 10 7 50 1.33 112 1.67 31 154 4.16 15 141 30 2.5

x4 94 71 450 8.42 1008 5.76 531 5174 64.33 297 3805 282 39.72

x2dn 82 56 223 1.11 377 2.04 120 974 15.68 101 1053 246 14.63

x9dn 27 7 224 2.4 572 3.27 120 2274 15.71 184 4240 81 25.56


17

• Area comparisons (Cont...)

Area of PRPG(LFSR)

CircuitNum. ofPrimaryInputs 1 EXOR n EXORs

Area ofBILBO

Area ofEDPG

alu4 14 129 168 236 202

apex1 45 408 540 747 543

apex5 117 1056 1404 1935 1335

i2 201 1812 2412 3321 2259

rd73 7 66 84 120 125

x4 94 849 1128 1556 1082

x9dn 27 246 324 450 345


18

• Multiple Fault Simulation Results

Circuit PI PO AND Part EXOR Part Check Part Literal Part

520 784 312 312 72 72 64 64 Single

50,456 5,358,704 13,436 735,008 644 7,744 1,040 16,128 Simulatedadr4 14 31

0 0 0 0 36 (5%) 680 (8%) 0 0 NotDetected

184 360 144 144 88 88 80 80

7,380 302,200 3,512 98,672 964 14,160 1,660 32,400alu1 45 16

0 0 0 0 44 (4%) 1,008 (7%) 0 0

524 880 344 344 56 56 56 56

47,940 4,964,248 16,912 1,038,072 388 3,672 784 10,584f51ml 117 31

0 0 0 0 28 (6%) 416 (11%) 0 0

308 544 176 176 72 72 64 64

15,776 939,376 4,788 156,752 644 7,744 1,040 16,128x2 201 15

0 0 0 0 36 (5%) 680 (8%) 0 0

2 Faults 3 Faults


19

Testing Multi-level AND-EXOR NetworksTesting Multi-level AND-EXOR Networks

• Two-level implementations– easily testable

– large delay

• It is possible to factorize the two-level ESOP expression

• Universal testing of two-level ESOPs can be adopted for multi-level testing– requires scan registers

20


Example: The multi-output function,

X = acefg ace’f’g’ ad’efg ad’e’f’g’ ajh’i ajd b’cefg b’ce’f’g’ b’d’efg b’d’e’f’g’ b’h’ij bdj

Y = bg’ a’cefg a’d’efg

Z = adj b’dj ah’ij b’h’ij

can be factorized as,

X = U[V(efg e’f’g’) jW]

Y = bg’ a’efgV

Z = jUW

where,

U = a b’

V = c d’

W = h’i d

21

• Implementation without testability improvements


ab

cd

ef

h

i

j

g

X

Y

Z

L ite ra l P a rtsca n -in

22

• Inserting Literal Part


ab

cd

ef

h

i

j

g

X

Y

Z

c 1

Litera l Par tscan-in

23

• Inserting Check Part


ab

cd

ef

h

i

j

g

X

Y

Z

c 1

o1

C heck Par t

c 2

scan-in

24

• Creating cascade of EXOR gates at each level


ab

cd

ef

h

i

j

g

X

Y

Z

c 1

c 2

o1

C heck Par t

Litera l Par tscan-in

25

• Identifying ESOP Planes


ab

cd

ef

h

i

j

g

X

Y

Z

c 1

c 2

o1

C heck Par t

E 1

E 2

E 3

E 4

E 6

E 7

E 5 E 8

scan-in

26

• Inserting specialized Scan Registers and Scan Path


ab

cd

ef

h

i

j

g

X

Y

Z

c 1

scan-in scan-out

c 2

o1

C heck Par t

Litera l Par t E 1

E 2

E 3

E 4

E 6

E 7

E 5 E 8

SR 1

SR 2

SR 3

SR 4

SR 5

27

TESTING SCHEME:• Each level is tested separately (can be improved)

• ESOP planes of the same level are tested in parallel

• Test vectors of the first level are applied from the primary inputs in parallel

• Test vectors of the internal levels are applied from the primary inputs and from the scan registers

• The bits applied from the scan registers are shifted into the scan path before applied in parallel

• The network results are collected by the scan registers and shifted out, and/or observed from the primary outputs


28

• Implementation of Scan Registers


m ux1

ESO P

Dff

D Q

m ux 2

ESO P

S ca n R eg is te r

to n ex tsca n b lo c k

......

fro m p rev .sca n b lo c k

R ea d /S h ift C lk N o rm a l/T est

• In normal circuit operation, only one mux delay added

• Inserted only at the output of internal ESOP planes

29

• Scan Register mode of operations


m u x

1

E S O P

D ff

D Q

m u x

2

E S O P

Scan R egis ter

to nex tscan b lock

.... . .

from prev.scan b lock

R ead/Shift C lk N orm al/Tes t

30



m u x

1

E S O P

D ff

D Q

m u x

2

E S O P

Scan R egis ter

to nex tscan b lock

.... . .



31



m u x

1

E S O P

D ff

D Q

m u x

2

E S O P

Scan R egis ter

to nex tscan b lock

.... . .



32

• Critical Path Delay = 2.95 ns


ab

cd

ef

h

i

j

g

X

Y

Z

c 1

scan-in scan-out

c 2

o1

C heck Par t

Litera l Par t E 1

E 2

E 3

E 4

E 6

E 7

E 5 E 8

SR 1

SR 2

SR 3

SR 4

SR 5

vs.

4.33 ns of 2-level impl.

33


ab

cd

ef

h

i

j

g

X

Y

Z

c 1

scan-in scan-out

c 2

o1

C heck Par t

Litera l Par t E 1

E 2

E 3

E 4

E 6

E 7

E 5 E 8

SR 1

SR 2

SR 3

SR 4

SR 5

• (4 AND3 + 5 AND2 + 24 EXOR2) gates + 5 SR

vs.

(17 AND3 + 24 AND2 + 33 EXOR2) gates of 2-level impl.

34

Future DirectionsFuture Directions

• Developing a universal test set for bridging and stuck-open faults

• Developing a factorization/decomposition method targeting EXOR-based multi-level synthesis and universal (deterministic) testability

35

Advantages and Disadvantages of the New SchemeAdvantages and Disadvantages of the New Scheme

• Test set is exponentially smaller than a pseudorandom test set and much smaller than algorithmically generated test set for 100% coverage of single stuck-at faults

• Properties of deterministic pattern generator for BIST – easy to implement (small area overhead)

– does not require seed generation

– guarantees 100% testability

• Detects significant fraction of multiple stuck-at faults and bridging faults

• Cascade of EXOR gates is relatively slow

• Area of the AND-EXOR circuit is relatively large

• ESOP factorization algorithm is computationally complex

36

RereferencesRereferences

[1] Ugur Kalay, Douglas V. Hall, Marek A. Perkowski. “A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits”. IEEE Trans. Comp. Vol. 49, N3, March 1999, pp.267-276.

[2] Ugur Kalay, Marek Perkowski. “Rectangle Covering Factorization of EXORs into Scan-Based Levelized Circuits with Universal Test Set”. Proc. of International Workshop on Application of Reed-Muller Expansion in Circuit Design. 1999.

Universally Testable AND-EXOR Networks

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