Department of EECS University of California, Berkeley

EECS 105 Spring 2017, Module 3

Prof. Ali M. Niknejad Prof. Rikky Muller

Complete MOS Small-Signal Model

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Announcements

l  Welcome back! l  Pick up graded MT2 in lecture on Tuesday l  Check updated syllabus l  No lab this week l  HW8 due on Friday

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EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

3

Review: An MOS Amplifier

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DSI

GSV

vgs

DR DDV

vGS =VGS + vgs

ov

Input signal

Output signal

Supply “Rail”

This type of amplifier is known as “Common Source (CS)”

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Plot of Output Waveform (Gain!)

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output

input

mV

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Total Small Signal Current

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( )DS DS dsi t I i= +

DS DSds gs ds

gs ds

i ii v vv v∂ ∂

= +∂ ∂

1ds m gs ds

o

i g v vr

= +

Transconductance Conductance

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Changing One Variable at a Time

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Assumption: VDS > VDS,SAT = VGS – VTn (square law)

GSV

/DSI k

Square Law Saturation

Region

Linear Triode Region

Slope of Tangent: Incremental current increase

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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The Transconductance gm

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Defined as the change in drain current due to a change in the gate-source voltage, with everything else constant

, ,

( )(1 )GS DS GS DS

D Dm ox GS T DS

GS GSV V V V

i i Wg C V V Vv v L

µ λΔ ∂

= = = − +Δ ∂

2, ( ) (1 )

2ox

DS sat GS T DSCWI V V V

Lµ

λ= − +

( )m ox GS TWg C V VL

µ= −

0≈

2 2DSm ox ox DS

ox

IW Wg C C IWL LCL

µ µµ

= =

2( )

DSm

GS T

IgV V

=−

Gate Bias

Drain Current Bias

Drain Current Bias and Gate Bias

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Output Resistance ro

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Defined as the inverse of the change in drain current due to a change in the drain-source voltage, with everything else constant

Non-Zero Slope Caused by Channel-Length Modulation

DSVδ

DSIδ

IDS / K

VDS (V )

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Evaluating ro

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1

,GS DS

Do

DS V V

irv

−⎛ ⎞∂⎜ ⎟=⎜ ⎟∂⎝ ⎠

2( ) (1 )2ox

D GS T DSCWi V V V

Lµ

λ= − +

02

1

( )2ox

GS T

r CW V VLµ

λ=

−

01

DS

rIλ

≈

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Simple Small Signal Model for MOSFET

l  This is a simplified, 3-terminal small-signal model for a MOSFET

l  In later lectures we will develop a more complete model l  gm = transconductance

–  defined as dids/dvgs, units [Ohms]-1

l  ro = output resistance –  defined as [dids/dvds]-1, units Ohms

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NMOS

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Small-Signal PMOS Model

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l  This is a simplified, 3-terminal small-signal model for a MOSFET

l  In later lectures we will develop a more complete model l  gm = transconductance

–  defined as disd/dvsg, units [Ohms]-1

l  ro = output resistance –  defined as [disd/dvsd]-1, units Ohms

PMOS

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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What we’ve ignored…until now!

l  The fourth terminal of the MOSFET is the body of the transistor… it can act like a second gate, or “back gate”

l  The junctions of the transistor form pn-junction diodes with body, this introduces parasitic capacitance

University of California, Berkeley

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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MOSFET Capacitances in Saturation

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•  Note that gate-source capacitance: channel charge is mostly controlled by gate-source and not drain in saturation

MOSFETS have many parasitic capacitances Let us analyze where each parasitic comes from

LD

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Gate-Source Capacitance Cgs

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Wedge-shaped charge in saturation à effective area is (2/3)WL

ovoxgs CWLCC += )3/2(

Overlap capacitance along source edge of gate à

Cov = LDWCox

(Underestimate due to fringing fields)

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Gate-Drain Capacitance Cgd

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Not due to change in inversion charge in channel. Overlap (and fringing) capacitance Cov between drain and source is Cgd

Cgd =Cov = LDWCox

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Drain-Bulk Capacitance Cdb

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•  Drain-Bulk and Source-Bulk capacitance is caused by p-n junction depletion

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Summary of Capacitance Models

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Cgs = (2 / 3)WLCox +Cov

Cgd =Cov

Csb =Cjsb(area+ perimeter) junctionCdb =Cjdb(area+ perimeter) junction

Csb

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Back-Gate Effect

l  Transistor really has four terminals: –  Source / Drain –  Gate / Body

l  There is a symmetry between the gate and the body. The body can act like a “back gate”

l  In many instances the body terminal is simply tied to the source (ground or VSS for NMOS, supply or VDD for PMOS)

l  What happens if there is a DC or AC voltage swing on the body?

University of California, Berkeley

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Body Bias Affects VT l  If there is a body bias VSB, a depletion capacitance

appears in parallel with Cox and affects the amount of channel charge:

l  Cdep changes with body bias, if we account for this:

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( )0 2 2T T SB p pV V Vγ φ φ= + − − −

Qinv = −Cox VGS −VT +CdepCox

VSB⎡

⎣⎢⎢

⎤

⎦⎥⎥

VT (VSB ) =VT 0 +CdepCox

VSB

Cdep = εs / xdep,maxQinv = −Cox (VGS −VT )+CdepVSB

VT 0n =VFB − 2φ p +1Cox

2qεsNa (−2φ p )

ΔVT =1Cox

2qεsNa ( −2φ p +VSB − −2φ p )

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

20 University of California, Berkeley

Role of the Substrate Potential

Note: Need not be the source potential, but VB < VS Effect: changes threshold voltage, which changes the drain current … substrate acts like a “backgate”

QBS

D

QBS

Dmb v

ivig

∂∂

=ΔΔ

= Q = (VGS, VDS, VBS)

gmb =∂iD∂vBS Q

=∂iD∂VTn Q

∂VTn∂vBS Q

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

21 University of California, Berkeley

Backgate Transconductance

Result: 2 2Tn mD D

mbBS Tn BS BS pQ Q Q

V gi igv V v V

γ

φ

∂∂ ∂= = =∂ ∂ ∂ − −

( )0 2 2T T SB p pV V Vγ φ φ= + − − −

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

22 University of California, Berkeley

Four-Terminal Small-Signal Model

1ds m gs mb bs ds

o

i g v g v vr

= + +

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Complete Small-Signal Model NMOS

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G

S

D

gmbvbs

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Complete Small-Signal Model PMOS

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