The Devices:

MOS Transistors

Prof. Kaushik Roy

@ Purdue Univ.

References:

Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley

Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al.

Prentice Hall

NMOS Transistor

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

CROSS-SECTION of NMOS Transistor

Gate Oxide

Field Oxide

Cross-Section of CMOS Technology

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Current-Voltage Relations

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

V VGS

VDS

ID

V(x)

L

x

- +

At x, the gate to channel voltage equals VGS - V(x)

Transistor in Linear Region

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

WxQxvI inD ).().(

])([)( TGSoxi VxVVCxQ

:)(xvndrift velocity

dx

dVxEv nnn )(

dVVVVWCdxI TGSoxnd )(..

ox

oxnoxnn

DSDSTGSnD

T

CCK

VVVV

L

WKI

'

)2

).(('

2

• Current

• Integrating over the length of the channel L

• Assume that the voltage exceeds VT all along the channel

• Induced charge/area at point x

Transistor In Saturation

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Transistor in Saturation

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

TDSGS VVV

• If drain-source voltage increases, the assumption that

the channel voltage is larger than VT all along the

channel ceases to hold.

• When VGS - V(x) < VT pinch-off occurs

• Pinch-off condition

Saturation Current

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

2)(2

'TGS

nD VV

L

WKI

• The voltage difference over the induced channel

(from pinch-off to the source) remains fixed at VGS -

VT and hence, the current remains constant.

• Replacing VDS by VGS-VT in equation for ID yields

• Effective length of the conductive channel is

modulated by applied VDS - Channel Length

Modulation

Current-Voltage Relations

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Cut-off: VGS VT, IDS 0

Linear Region: VDS < VGS - VT

Process Transconductance

Parameter

Saturation Mode: VDS VGS - VT

ox

oxnoxnn

tCk

'

2

2' DS

DSTGSnD

VVVV

L

WkI

DSTGSn

D VVVL

WkI 1

2

' 2

Channel Length Modulation

I-V Relations

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Linear: VDS < VGS - VT

(a) ID as a function of VDS (b) as a function

of VGS (for VDS = 5V)

DI

NMOS Enhancement Transistor: W = 100 ,L = 20 m m

Linear

Threshold Voltage: Concept

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

VT = VFB + VB + Vox

VB = 2fF

(strong inversion)

MOS-CAP Band Diagrams

Prof. Kaushik Roy

@ Purdue Univ.

Energy band diagram

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Vacuum Level

qϕm = 4.1 eV

0.95 eV

8 - 9 eV

qχ = 4.05 eV

qϕs

P-type silicon

Silicon Dioxide

Metal (aluminum)

Eg =

1.12 eV

Ef

Ec

Ev

Ec

Ev Ef

Evac

qϕs = qχ + Eg/2 + qϕB

MOS-cap: Equilibrium

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Ef

Ec

Ev

Ef

S O M

Here, ϕm = ϕs Flat band condition

ϕs can be changed with doping Bands will not be flat if ϕm ≠ ϕs -- apply a negative voltage (ϕm - ϕs ) with respect to Si substrate

qϕm qϕs

Gate

Evac

P-type Si

MOS-cap: Accumulation

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

The electric field causes band bending Electric field at any point is the slope of Ec or Ev at that point The electrostatic potential (ψ) at any point is the net band bending at that point

Ef

Gate

+++ +++

Ec

Ev

Ef

Vg < 0

Accumulation of holes

Bands bend upwards

No band bending deep in the bulk

- - - - - -

Surface potential (ψs) < 0

ψ (bulk) = 0

Negative gate voltage

MOS-cap: Depletion

Prof. Kaushik Roy

@ Purdue Univ.

Ef

Gate

Ec

Ev

Ef Vg > 0

Depletion region

+ +

Surface potential (ψs) > 0

ψ (bulk) = 0

For a small positive gate bias: Bands bend downwards at the surface i.e. Ev moves away from Ef Majority carriers (holes) are depleted at the surface

Positive gate voltage

MOS-cap: Inversion

Prof. Kaushik Roy

@ Purdue Univ.

Ef

Gate

Ec

Ev

Ef Vg > 0

Inversion layer at the surface

+ + + + +

Surface potential (ψs) > 0

ψ (bulk) = 0

- - - - - -

Channel at the surface is inverted when (ψs = 2ψB)

i

aBBs

n

N

q

Tkinv ln22)(

Where, Na = Doping density in the bulk (cm-3) ni = Intrinsic carrier concentration ~ 10E10 (cm-3)

Threshold Adjustment by Ion Implantation

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• Implant a relatively small, precisely controlled number

of either boron or phosphorus ions into the near-

surface region of semiconductor

• Implantation of boron causes a positive shift in

threshold voltage

• Implantation of phosphorus causes a negative shift

• Like placing additional “fixed” charges

ox

I

C

QV

acceptor:)(donor :)(

II qNQ

Back Biasing or Body Effect

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• VSB is normally positive for n-channel devices,

negative for p-channel devices

• Always increases the magnitude of the ideal device

threshold voltage

• Inversion occurs at fS = (2fF + VSB)

• Increases the charges stored in depletion region

)2(2 SBFsiAB VqNQ f

Threshold voltage

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

ox

BF

ox

ImsT

oxBFBT

C

Q

C

QV

VVVV

2

Dynamic Behavior of MOS Transistor

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Source of Cap. - Basic MOS structure

- channel charge

- depletion region of resource bias p-n junctions

The Gate Capacitance

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

(a) Top view

(b) Cross-section

Can be decomposed into a number of elements

each with a different behavior

WLt

Cox

oxgate

CGSO

s

CSB CDB

CgDO

Lateral diffusion

P

The Gate Capacitance

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Parasitic capacitance between gate and source (drain) called

Overlap Capacitance (linear)

CgsO = CgdO = Cox.xd.W = Co.W

Channel Capacitance: Cgs, Cgd, and Cgb

Cut-Off: no channel, total capacitance = CoxWLeff

appears between gate and bulk

Triode Region: Inversion layer - acts as conductor

Symmetry dictates

Saturation: Pinch off,

Cgs averages (2/3)CoxWLeff

0,0 gbgd CC

2

effox

gdgs

WLCCC

0 gbC

Diffusion Capacitance (Junction Capacitance)

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Reverse biased source-bulk and drain-bulk pn junctions

Diffusion Capacitance (Junction Capacitance)

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

- Bottom plate

Cbottom = CjWLs,

- Side-wall junctions - formed by source (ND) and P+ channel

stop (NA+)

- graded junction (m=1/3)

Csw = C’jswxj(w+2Ls)

= Cjsw(W + 2Ls)

Cjsw = C’jswxj , xj = junction depth

- Cdiff = Cbottom + Csw

= Cj * Area + Cjsw x Perimeter

= CjLsW + Cjsw (2Ls + W)

Junction Capacitance

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

VD (V)

m

D

j

jV

CC

)/1( 0

0

f

The Sub-Micron MOS Transistor

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• Threshold Variations (Manufacturing tech., VSB)

• Parasitic Resistances

• Velocity Saturation and Mobility Degradation

• Subthreshold Conduction

• Latchup

Threshold Variations

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

VT

VDS

DIBL (Drain Induced Barrier Lowering)

Low L

VT

L

Low VDS

Long channel

• In derivation of VT the following assumption were made:

– charge beneath gate originates from MOS field effects

– ignores depletion region the source and drain junctions (reverse

biased)

• A part of the region below the gate is already depleted (by

source & drain fields), a smaller VT suffices to cause strong

inversion

• VT decreases with L

• Similar effect can be obtained by increasing VDS or VDB as it

increases drain-junction depletion region

Threshold Variations

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• VT can also drift over time (Hot-carrier effect)

– Decreased device dimensions

– Increase in electrical field

– Increasing velocity of electrons, can leave Si surface and

enter gate oxide

– Electrons trapped in gate oxide change VT (increases in

NMOS, decreases in PMOS)

• For a electron to be hot, electric field of 104 V/cm is

necessary

– Condition easily met for sub-micron devices

Parasitic Resistances

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

CS RRW

LR []

Solutions: cover the diffusion regions with low-resistivity material

such as titanium or tungsten, or make the transistor wider

Velocity Saturation (1)

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

short channel devices

cm/sec

(a) Velocity saturation (b) Mobility degradation

Velocity Saturation (2)

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

)( TDSATGSoxSATDSAT VVVWCvI

Linear Dependence on VGS

independent on L current drive cannot be improved by

decreasing L

Sub-threshold Conduction

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

SOI has better sub-threshold leakage

(Inverse) Rate of decrease of current : )1(10ln)ln(

1

q

KTI

dV

dD

GS

60mV/decade At T= 300oK

VGS < VT

)1(//)( kTqVnkTqVV

Ddstgs eeKI

Latch-up

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

NMOS PMOS

S S D D

(a) Origin of latch-up

VB > VBE

(b) Equivalent circuit

Latch-up

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

p n p n Cathode C Anode A

Gate G

A C

G

Ig

• Parasitic circuit effect

• Shorting of VDD and VSS lines resulting in chip self-destruction or

system failure with requirements to power down

• To understand latchup consider: Silicon Controlled Rectifiers

(SCRs)

Ib2

Ib1 Ia

Ic2 Ic1

Ic

Latch-up

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

If Ig Ic2

Ic2 is the base current Ib1 of the p-n-p transistor

Ig Ib1 Ic1 Ib2

(magnitude of current increases)

If the gain of the transistor are b1 and b2

Then if b1 b2 1, the feedback action will turn device ON

permanently and current will self destruct device.

Latch-up Triggering

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• Parasitic n-p-n & pin-p has to be triggered and holding state to be

maintained

• Can be triggered by transient currents

– Voltages during power-up

– Radiation pulses

– Voltages or current beyond operating range

wellnpn

onpnp

ntriggerR

VI

.

Lateral

triggering

:npn Common base gain of n-p-n transistor

Similarly, vertical triggering due to the voltage

drop across Rsubstrate as current is injected into the

emitter

Latch-up Triggering

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• Triggering occurs due to (mainly) I/O circuits where internal

voltages meet external world and large currents can flow

– When NMOS experiences undershoot by more than 0.7V, the

drain is forward biased, which initiates latchup

– When PMOS experiences overshoot by more than 0.7V, the

drain is forward biased, which initiates latchup

Latch-up Prevention

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Analysis of the circuit shows that for latchup to occur the

following inequality has to be true

where

total supply current

The feedback current flowing into n-p-n base is collector

current offset by IRsub. To cause the feedback, this current

must be greater than initial n-p-n base current, Ib.

RsubDD

pnpRwellRsubnpn

pnpnpnII

II

).)(1(1

bbbb

DD

well

bepnp

Rwell

sub

benpn

Rsub

I

R

VI

R

VI

Prevention of latch-up

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• Reduce the resistor values (substrate & well) and reduce the

gain of parasitic transistors

• Latch-up resistant CMOS process

• Layout techniques

Spice Models

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• Level 1: Long Channel Equations - Very Simple

• Level 2: Physical Model - Includes Velocity Saturation and

Threshold Variations

• Level 3: Semi-Emperical - Based on curve fitting to measured

devices

• Level 4 (BSIM): Emperical-Simple and Popular

Main MOS Spice Parameters

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

SPICE Parameters for Parasitics

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

SPICE Transistor Parameters

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Technology Evolution

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.