CMOS VLSIDesign

Introduction

All materials are from the textbook

Weste and Harris, 3rd Edition CMOS VLSI DESIGN

Slide 2CMOS VLSI Design

Introduction Chapter 1 previews the entire field, subsequent

chapters elaborate on specific topics Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): very many Complementary Metal Oxide Semiconductor

– Fast, cheap, low power transistors Today: How to build your own simple CMOS chip

– CMOS transistors– Building logic gates from transistors– Transistor layout and fabrication

Rest of the course: How to build a good CMOS chip

Slide 3CMOS VLSI Design

Slide 4CMOS VLSI Design

Slide 5CMOS VLSI Design

Slide 6CMOS VLSI Design

Silicon Lattice Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors

Si SiSi

Si SiSi

Si SiSi

Slide 7CMOS VLSI Design

Dopants Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type)

As SiSi

Si SiSi

Si SiSi

B SiSi

Si SiSi

Si SiSi

-

+

+

-

Slide 8CMOS VLSI Design

p-n Junctions A junction between p-type and n-type semiconductor

forms a diode. Current flows only in one direction

p-type n-type

anode cathode

Slide 9CMOS VLSI Design

nMOS Transistor Four terminals: gate, source, drain, body Gate – oxide – body stack looks like a capacitor

– Gate and body are conductors– SiO2 (oxide) is a very good insulator– Called metal – oxide – semiconductor (MOS)

capacitor– Even though gate is

no longer made of metaln+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+

Slide 10CMOS VLSI Design

nMOS Operation Body is commonly tied to ground (0 V) When the gate is at a low voltage:

– P-type body is at low voltage– Source-body and drain-body diodes are OFF– No current flows, transistor is OFF

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

0

S

Slide 11CMOS VLSI Design

nMOS Operation Cont. When the gate is at a high voltage:

– Positive charge on gate of MOS capacitor– Negative charge attracted to body– Inverts a channel under gate to n-type– Now current can flow through n-type silicon from

source through channel to drain, transistor is ON

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

1

S

Slide 12CMOS VLSI Design

pMOS Transistor Similar, but doping and voltages reversed

– Body tied to high voltage (VDD)– Gate low: transistor ON– Gate high: transistor OFF– Bubble indicates inverted behavior

SiO2

n

GateSource Drain

bulk Si

Polysilicon

p+ p+

Slide 13CMOS VLSI Design

Slide 14CMOS VLSI Design

Power Supply Voltage GND = 0 V In 1980’s, VDD = 5V VDD has decreased in modern processes

– High VDD would damage modern tiny transistors

– Lower VDD saves power VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

Slide 15CMOS VLSI Design

Transistors as Switches We can view MOS transistors as electrically

controlled switches Voltage at gate controls path from source to drain

gs

d

g = 0

s

d

g = 1

s

d

gs

d

s

d

s

d

nMOS

pMOS

OFF ON

ON OFF

Slide 16CMOS VLSI Design

Slide 17CMOS VLSI Design

CMOS InverterA Y

0

1

VDD

A Y

GNDA Y

Slide 18CMOS VLSI Design

CMOS InverterA Y

0

1 0

VDD

A=1 Y=0

GND

ON

OFF

A Y

Slide 19CMOS VLSI Design

CMOS InverterA Y

0 1

1 0

VDD

A=0 Y=1

GND

OFF

ON

A Y

Slide 20CMOS VLSI Design

CMOS NAND GateA B Y

0 0

0 1

1 0

1 1A

B

Y

Slide 21CMOS VLSI Design

CMOS NAND GateA B Y

0 0 1

0 1

1 0

1 1

A=0

B=0

Y=1OFF

ON ON

OFF

Slide 22CMOS VLSI Design

CMOS NAND GateA B Y

0 0 1

0 1 1

1 0

1 1

A=0

B=1

Y=1OFF

OFF ON

ON

Slide 23CMOS VLSI Design

CMOS NAND GateA B Y

0 0 1

0 1 1

1 0 1

1 1

A=1

B=0

Y=1ON

ON OFF

OFF

Slide 24CMOS VLSI Design

CMOS NAND GateA B Y

0 0 1

0 1 1

1 0 1

1 1 0

A=1

B=1

Y=0ON

OFF OFF

ON

Slide 25CMOS VLSI Design

CMOS NOR GateA B Y

0 0 1

0 1 0

1 0 0

1 1 0

A

BY

Slide 26CMOS VLSI Design

3-input NAND Gate Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0

Slide 27CMOS VLSI Design

3-input NAND Gate Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0

A

B

Y

C

Slide 28CMOS VLSI Design

3-input NOR Gate

Slide 29CMOS VLSI Design

Slide 30CMOS VLSI Design

Pass Transistor

Slide 31CMOS VLSI Design

Transmission Gate

Slide 32CMOS VLSI Design

Why is it a bad design?

Slide 33CMOS VLSI Design

Tristates

EN = 0, Y = ZEN = 1, Y = A

Slide 34CMOS VLSI Design

Slide 35CMOS VLSI Design

What is the logic function of Y?

Y = D0 S’ + D1 S

Slide 36CMOS VLSI Design

Slide 37CMOS VLSI Design

D Latch

A D latch using one 2-input multiplexer and two invertersWhen CLK = 1, the latch is transparent, Q = DWhen CLK = 0, the latch is opaque, Q is unchanged

Slide 38CMOS VLSI Design

D Latch

A D latch using two transmission gates and two inverters

Slide 39CMOS VLSI Design

Positive edge triggered D flip flop

When CLK is low, QM follows D, (master samples the input D.)

When CLK is high, Q = QM, now QM holds the D value.

master slave

Slide 40CMOS VLSI Design

Positive edge triggered D flip flop

Slide 41CMOS VLSI Design

Slide 42CMOS VLSI Design

Slide 43CMOS VLSI Design

Clock skew problems will not occur as long as the phases do not overlap.

Slide 44CMOS VLSI Design

CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or

etched Easiest to understand by viewing both top and

cross-section of wafer in a simplified manufacturing process

Slide 45CMOS VLSI Design

Inverter Cross-section Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors

n+

p substrate

p+

n well

A

YGND VDD

n+ p+

SiO2

n+ diffusion

p+ diffusion

polysilicon

metal1

nMOS transistor pMOS transistor

Slide 46CMOS VLSI Design

Well and Substrate Taps Substrate must be tied to GND and n-well to VDD

Metal to lightly-doped semiconductor forms poor connection called Shottky Diode

Use heavily doped well and substrate contacts / taps

n+

p substrate

p+

n well

A

YGND VDD

n+p+

substrate tap well tap

n+ p+

Slide 47CMOS VLSI Design

Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line

GND VDD

Y

A

substrate tap well tapnMOS transistor pMOS transistor

Slide 48CMOS VLSI Design

Detailed Mask Views Six masks

– n-well– Polysilicon

– n+ diffusion– p+ diffusion– Contact

– MetalMetal

Polysilicon

Contact

n+ Diffusion

p+ Diffusion

n well

Slide 49CMOS VLSI Design

Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well

– Cover wafer with protective layer of SiO2 (oxide)– Remove layer where n-well should be built– Implant or diffuse n dopants into exposed wafer– Strip off SiO2

p substrate

Slide 50CMOS VLSI Design

Oxidation Grow SiO2 on top of Si wafer

– 900 – 1200 C with H2O or O2 in oxidation furnace

p substrate

SiO2

Slide 51CMOS VLSI Design

Photoresist Spin on photoresist

– Photoresist is a light-sensitive organic polymer– Softens where exposed to light

p substrate

SiO2

Photoresist

Slide 52CMOS VLSI Design

Lithography Expose photoresist through n-well mask Strip off exposed photoresist

p substrate

SiO2

Photoresist

Slide 53CMOS VLSI Design

Etch Etch oxide with hydrofluoric acid (HF)

– Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed

p substrate

SiO2

Photoresist

Slide 54CMOS VLSI Design

Strip Photoresist Strip off remaining photoresist

– Use mixture of acids called piranah etch Necessary so resist doesn’t melt in next step

p substrate

SiO2

Slide 55CMOS VLSI Design

n-well n-well is formed with diffusion or ion implantation Diffusion

– Place wafer in furnace with arsenic gas– Heat until As atoms diffuse into exposed Si

Ion Implanatation– Blast wafer with beam of As ions– Ions blocked by SiO2, only enter exposed Si

n well

SiO2

Slide 56CMOS VLSI Design

Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps

p substraten well

Slide 57CMOS VLSI Design

Polysilicon Deposit very thin layer of gate oxide

– < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer

– Place wafer in furnace with Silane gas (SiH4)– Forms many small crystals called polysilicon– Heavily doped to be good conductor

Thin gate oxidePolysilicon

p substraten well

Slide 58CMOS VLSI Design

Polysilicon Patterning Use same lithography process to pattern polysilicon

Polysilicon

p substrate

Thin gate oxidePolysilicon

n well

Slide 59CMOS VLSI Design

Self-Aligned Process Use oxide and masking to expose where n+ dopants

should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well

contact

p substraten well

Slide 60CMOS VLSI Design

N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates

because it doesn’t melt during later processing

p substraten well

n+ Diffusion

Slide 61CMOS VLSI Design

N-diffusion cont. Historically dopants were diffused Usually ion implantation today But regions are still called diffusion

n wellp substrate

n+n+ n+

Slide 62CMOS VLSI Design

N-diffusion cont. Strip off oxide to complete patterning step

n wellp substrate

n+n+ n+

Slide 63CMOS VLSI Design

P-Diffusion Similar set of steps form p+ diffusion regions for

pMOS source and drain and substrate contact

p+ Diffusion

p substraten well

n+n+ n+p+p+p+

Slide 64CMOS VLSI Design

Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed

p substrate

Thick field oxide

n well

n+n+ n+p+p+p+

Contact

Slide 65CMOS VLSI Design

Metalization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires

p substrate

Metal

Thick field oxide

n well

n+n+ n+p+p+p+

Metal

Slide 66CMOS VLSI Design

Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor

size (and hence speed, cost, and power) Feature size f = distance between source and drain

– Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Normalize for feature size when describing design

rules Express rules in terms of = f/2

– E.g. = 0.3 m in 0.6 m process

Slide 67CMOS VLSI Design

Simplified Design Rules Conservative rules to get you started

Slide 68CMOS VLSI Design

Inverter Layout Transistor dimensions specified as Width / Length

– Minimum size is 4 / 2sometimes called 1 unit– In f = 0.6 m process, this is 1.2 m wide, 0.6 m

long

Slide 69CMOS VLSI Design

Summary MOS Transistors are stack of gate, oxide, silicon Can be viewed as electrically controlled switches Build logic gates out of switches Draw masks to specify layout of transistors

Now you know everything necessary to start designing schematics and layout for a simple chip!

Slide 70CMOS VLSI Design

Homework #1due: September 4 class timeNo late homework accepted

Chapter 1 Exercises1.1, 1.3, 1.4, 1.6, 1.7