Ppt of Principles of Cmos Vlsi Design

EE559 MOS VLSI Design

Prepared by CK & KR 1

EE559: MOS VLSI Design

I t t K RInstructors: K. RoyEmail: [email protected]: www.ece.purdue.edu/~kaushikOffice: MSEE 232Telephone: 494-2361Office Hours: Tuesday/Thursday 11am-12noon

b i t tor by appointments

Grading Policy

• Mid-terms + quizzes + hw will account for 75% of the grade– 3 mid-terms– Mandatory and has to be taken on the scheduled day of the exam.

• Project will account for 25% of the grade. Late projects will not be accepted.

• You are guaranteed an A if your weighted average score over exams, quizzes, and projects is 90 or above.

• Any form of cheating will be heavily penalized and reported to the Dean of students and may result in a failing grade.y g g

• Instructor reserves right to change project requirements.



Text and References

• Text:Text:– Digital Integrated Circuits: A Design Perspective,

J. Rabaey, Prentice Hall, Second edition

• References:– Principles of CMOS VLSI Design: A Systems Perspective,

2nd Ed., N. H. E. Weste and K. Eshraghian, Addison Wesley

– Circuits, Interconnects, and Packaging for VLSI, H. Bakoglu, Addison Wesley

• Class Notes:– http://www.ece.purdue.edu/~vlsi/ee559/20001

Conferences & Journals

• IEEE Transactions on VLSI Systems• IEEE Transactions on CAD of IC’sIEEE Transactions on CAD of IC s• IEEE Journal of Solid State Circuits• IEEE VLSI Circuits Symposium• Journal of Electronic Testing• ACM Design Automation Conference• IEEE International Conference on CAD• IEEE Solid State Circuits Conference• International symposium on Low-Power Electronics & Design• IEEE Conference on Computer Design• IEEE International Test Conference



Course Outline

• Introduction: Historical perspective and Future Trend• Semiconductor Devices

CMOS Logic Layout techniques• CMOS Logic, Layout techniques• MOS devices, SPICE models• Inverters: transfer characteristics, static and dynamic

behavior, power and energy consumption of static MOS inverters

• Designing combinational logic gates in CMOS– Static CMOS design: Complementary CMOS, ratioed logic,

pass-transistor logic– Dynamic CMOS logic

Course Outline (Cont’d)

• Designing combinational logic gates (Cont’d)– Power consumption in CMOS gatesp g– Low-power design

• Designing sequential circuits• Interconnect and timing issues• Designing memory and array structures• Designing arithmetic building blocks

S f• VLSI testing and verification



VLSI CAD Lab and TA

• VLSI CAD Lab located in 360 Potter Engineering Center– SUN workstations running Mentor Graphics tools– Courtesy key for after-hour access can be obtained from

front desk in Potter Engineering Library– Additional workstations in MSEE 186

• Lab TA: Kuntal Roy ([email protected])– Facilitates the use of lab design tools. – Office hours: TBA– Lab Orientation will be held in the second week

• Lab URL– http://min.ecn.purdue.edu/~mgcdevel/ee559_lab.html

Course Project

• Complete design of a functional logic block or system– Complexity of 1000+ transistors or novelty– Design using the CADENCE tools and HSPICE

• Design your own library from scratch– Functionality to be verified– Critical path timing should be verified using HSPICE– Project report due the last day of class– Project presentation by each group in the last week of class– Work in a group of 2 will be allowed in special cases– Start early!Start early!– Emphasis on new ideas, power dissipation, performance,

reconfigurability, low voltage design



Introduction:A Historical Perspective and Future

Trends

References: Adapted from: Digital Integrated Circuits: A Design Perspective, p g g g p ,

J. Rabaey © UCBPrinciples of CMOS VLSI Design: A Systems Perspective,

2nd Ed., N. H. E. Weste and K. Eshraghian

Digital Computation: Particle Location is an Indicator of State

1 1 0 0 1 0



Physical Medium for Computation: Barrier Model

V=0 SOURCE DRAIN

GATE

Eb

V=Vmin=Ebmin

ToxLeff

Vg

Vd

1. Can we operate with Vmin ~ KBTln2 ?

2. Can we operate with Qmin = q ?



The First Computer

• The Babbage Differential gEngine (1834)

• 25,000 mechanical parts• Cost £17,470

Digital Electronic Computing

• Started with the introduction of vacuum tube• ENIAC for computing artillery firing tables in 1946• ENIAC for computing artillery firing tables in 1946• Integration density

– 80 feet long, 8.5 feet high, and several feet wide– 18,000 vacuum tubes

• Reliability issues and excessive power consumption• Did not go far until the invention of the transistor at

Bell Lab in 1947



HISTORY• MOS field-effect transistor: Lilienfeld (1925), Heil (1935)

• Bipolar transistors: Bardeen (1947), Schockley (1949)

• First Bipolar digital logic: Harris (1956)First Bipolar digital logic: Harris (1956)– IC Logic family:

• Transistor-Transistor Logic (TTL) (1962)

• Emitter-Coupled Logic (ECL) (1971)

• Integrated Injection Logic (I2L) (1972)

• PMOS and NMOS transistors on the same substrate: Weimer (1962), Wanlass (1965)( ), ( )

• PMOS-only logic until 1971 when NMOS technology emerged• NMOS-only logic until late 1970s, when CMOS technology took

over• Later developments: BiCMOS, GaAs, low-temperator CMOS,

super-conducting technologies, Nano-electronic

Exponential Increase in Leakage

Non-SiliconSilicon Silicon

1 µm 100 nm 10 nm

1970 1980 2000 2010 2020

5 µm

Non Silicon Technology

Silicon Micro- electronics

Silicon Nano- electronics

GateS

Subthreshold Leakage

Gate Leakage

% o

f Tot

al)

40%

50%Must stop

at 50%

610ON

OFF

II

=310ON

OFF

II

= 2~6~ 10ON

OFF

II

Junctionleakage

Source

n+n+

Bulk

Drain

A. Grove, IEDM 2002

Technology (μ)

Leak

age

Pow

er (%

0%

10%

20%

30%

1.5 0.7 0.35 0.18 0.09 0.05



Technology Trend

Buried Oxide (BOX)Substrate

Fully-depleted body

Gate

VG

VS VD

DrainSource

Vback

Buried Oxide (BOX)Substrate

Fully-depleted body

Gate

VG

VS VD

DrainSource

Vback

Bulk-CMOS

FD/SOI

Nano devices Carbon nanotubeIII-V devices nano-wiresSpintronics

DGMOS

FinFET TrigateBuried Oxide (BOX)

Substrate

Source Floating Body Drain

GateVS

VG

VD

Buried Oxide (BOX)

Substrate

Source Floating Body Drain

GateVS

VG

VD

PD/SOISingle gate device Multi-gate devicesPD/SOI

Design methods to exploit the advantages of technology innovations

Things NaturalThings Natural Things ManmadeThings ManmadeHead of a pin

1-2 mm

Ant~ 5 mm

Dust mite

200 μm

The Challenge

0 1 mm

1 millimeter (mm)

1 cm10 mm

10-2 m

10-3 m

10 4

Micro

wave

1,000,000 nanometers =

The Scale of Things The Scale of Things –– Nanometers and MoreNanometers and More

MicroElectroMechanical (MEMS) devices10 -100 μm wide

Fly ash~ 10-20 μmHuman hair

~ 60-120 μm wide

Red blood cellswith white cell

~ 2-5 μm

200 μm

O O

O

OO

O OO O OO OO

O

S

O

S

O

S

O

S

O

S

O

S

O

S

O

S

PO

O

Fabricate and combine nanoscale building blocks to make useful devices, e.g., a photosynthetic reaction center with

Mic

row

orld

0.1 μm100 nm

1 micrometer (μm)

0.01 mm10 μm

0.1 mm100 μm

10-4 m

10-5 m

10-6 m

10-7 m

Visib

le

1,000 nanometers =

Infra

red

Zone plate x-ray “lens”Outer ring spacing ~35 nm

Red blood cellsPollen grain

Smaller is different!

DNA~2-1/2 nm diameter Atoms of silicon

spacing ~tenths of nm

Quantum corral of 48 iron atoms on copper surfacepositioned one at a time with an STM tip

Corral diameter 14 nm

ATP synthase

~10 nm diameterNanotube electrode

Carbon nanotube~1.3 nm diameter

integral semiconductor storage.

0.1 nm

1 nanometer (nm)

0.01 μm10 nm

10-8 m

10-9 m

10-10 m

Nan

owor

ld Ultra

violet

Soft

x-ray

Office of Basic Energy SciencesOffice of Science, U.S. DOE

Version 10-07-03, pmd

Carbon buckyball

~1 nm diameter

Self-assembled,Nature-inspired structureMany 10s of nm

More is different!



Variation in Process ParametersDevice 1 Device 2

130nm

30 %

1.11.1

1 .21 .2

1 .31 .3

1 .41 .4

rmal

ized

Fre

quen

cyrm

aliz

ed F

requ

ency

Source: Intel

Channel length

5X0.90 .9

1 .01 .0

11 22 33 44 55N o rm alized L eakag e (N o rm a lized L eakage ( IsbIsb ))

NorNor

Delay and Leakage Spread

100

1000

10000

nt a

tom

s Source: Intel

Inter and Intra-die Variations

Device parameters are no longer deterministic

10

100

1000 500 250 130 65 32Technology Node (nm)

# do

paRandom dopant fluctuation

ReliabilityTemporal degradation of performance -- NBTI

y

Tech. generation

Failu

re p

roba

bilit

y

TimeLif tiDefects Life time degradationInterface trap generation over time



Scaling & Ion/Ioff

1 um 100 nm 10 nm

• Increasing leakage

• Increasing process variations

Non-Silicon technology

Silicon micro electronics

I

V• Carbon Nanotubes

Silicon nano electronics

610=OFF

ON

II 310=

OFF

ON

II

p

• Short Channel Effects

• Molecular transistors

• Molecular RTDs

410=OFF

ON

II

2. Power & Power Density

atts

)

P6Pentium ® proc

10

100

cm2 )

Pow

er (W

a 486

3862868086

80858080

80084004

0.1

1

Pow

er D

ensi

ty (W

/

Year1971 1974 1978 1985 1992 2000

Year

Increased Average Power• Battery Life • Cooling Cost

Increased Power Density• Reliability

Source: Intel



Nano-Scaled Si DevicesSi Fin

DGMOSPlanar double-gate structure

FinFET or Tri-GateQuasi-planar DG structure

Ground PlaneSOI MOSShared back gate DG devices

Independent gate FinFET Bulk Si MOSFETs

Variation in Process Parameters

1 3 0 n m

3 0 %

1 .11 .1

1 .21 .2

1 .31 .3

1 .41 .4

qy

ency

(nor

m)

S I t l

1000

10000

oms Source: Intel

5 X0 .90 .9

1 .01 .0

11 22 33 44 55Leakage (normalized)

Freq

ue Source: Intel

Inter and Intra-die Variations

10

100

1000 500 250 130 65 32Technology Node (nm)

# do

pant

ato

Random dopant fluctuation



Evolution in Complexity

Processor Trends

PP 66 PPro-150UltraSparc-167

HP PA8000

700

800

i486C-33486-66

PP-66

DX4 100

PPC 601-80MIPS R4400

PP-133

PPro 150

PPro200

MIPS R10000A21164-300SuperSparc2-90

HP PA7200

PPC 604-120A21064APP-100

300

400

500

600

Die

Siz

e (m

il2)

i386i386C-33

0

100

200

300

'91 '93 '94 '95 '96



Processor Trends (cont’d)

A21064A

A21164-300300

PP-100

MIPS R4400

SuperSparc2-90

PPC 604-120

PPro-150

PPC603e-100

PP166MIPS R10000

PPro200

PP-66486-66 PPC 601-80

HP PA7200PP-133

UltraSparc-167HP PA8000

MIPS R5000

DX4 100100

150

200

250

Freq

(MH

z)

i386i486C-33

i386C-33PP-66

0

50

'91 '93 '94 '95 '96

Higher Performance:•Higher Frequencies (2x/Generation)•Higher Device counts (2x /Generation)

Power Trends

A21164-300 HP PA8000

35

40

PP-66

A21064A

MIPS R4400

SuperSparc2-90PPC 604-120

PPro-150

PP166MIPS R5000

MIPS R10000

PPro200UltraSparc-167

HP PA7200

15

20

25

30

35

Pow

er(W

)

[Source: Microprocessor Report]

486-66DX4 100

PP-100MIPS R4400

PP-133

PPC603e-100

PP166PPC 601-80

i386C-33i486C-33

i3860

5

10

'91 '93 '94 '95'94 '96

2x Performance Increase ==> 2x power increase



• Chips fail when they get hot• Need compact and cost-effective cooling solns

Heat Dissipation

p g

CPU Thermal Soln Cost

486/33mhz HeatSink $0.50486DX2 66mhz Heatsink $1.00Pentium 66mhz Larger Heatsink $2.00

System Fan $4.00

• Cooling Solns will become more exotic/expensive– Extruded Heatsinks, Heatpipes, Blowers, Noise....

• Every Watt impacts System Cost, esp. for HVM

Where is the Power Going? (Mobile PC)

20

25

30

CPU Power: predicted from average device count/area growth

0

5

10

15

89 91 92 93 94 95 96 97

CPU Graphics I/O Subsystem Total

• CPU Power increasing (Predicted in 1994 Low power workshop)

• Graphics & Chipset Power increasing faster than predicted

p g g

Power reduction is not only a CPU problem



Intel 4004 Microprocessor

Intel Pentium (II) Microprocessor



Dunnington is the first IA (Intel Architecture) processor with 6-cores, is based on the 45nm high-k process technology, and has large shared caches.

Tukwila, 4-cores, world's first 2 billion transistor microprocessor



T h l ( ) 0 25 0 18 0 13 0 10 0 07

National Technology Roadmap for Semiconductor (NTRS)

Technology (um) 0.25 0.18 0.13 0.10 0.07Year 1998 2001 2004 2007 2010

# transistors 28M 64M 150M 350M 800MOn-Chip Clock (MHz) 450 600 800 1000 1100

Area (mm2) 300 360 430 520 620Wiring Levels 5 5-6 6 6-7 7-8

Interconnect Performance Trend

Technology (um) 0.25 0.18 0.15 0.13 0.10 0.072cm line delay (ns) 2.589 2.480 2.650 2.620 3.730 4.670

1mm line delay (ns) 0.059 0.049 0.051 0.044 0.052 0.042

Intrinsic gate delay (ns) 0.071 0.051 0.049 0.045 0.039 0.022



Interconnect Complexity

Technology (um) 0.25 0.18 0.13 0.10 0.07Length (m) 820 1,480 2,840 5,140 10,000

6 6 8 8 9Wiring Levels 6 6-7 7 7-8 8-9Opt. # buffers per net few many

Opt. # wiresizes per net few manyOpt. # buffers per chip 5K 25K 54K 230K 797K

• Performance

• Signal reliability

• Electromigration

Distributions of Wire lengths

1E+06

1E+07

ts

Rent's exponent = 0.6Rent's coefficient = 4.0

1E+01

1E+02

1E+03

1E+04

1E+05

umbe

r of

Inte

rcon

nect

0.07 um tech.

Rent s coefficient 4.0Avg. fanout = 3

1E+00

1E+01

0 10 20 30Length (mm)

Nu

0.25 um tech.



Technology Scaling

Technology scaling improves:

Transistor & interconnect performanceTransistor densityEnergy consumed per switching transition

0.7X scaling factor (30% scaling) results in:

30% t d l d ti (43% f ↑ )30% gate delay reduction (43% freq. ↑ ) 2X transistor density increase (49% area ↓ )Energy per transition reduction

Technology Scaling

• Speed & PerformanceHigh drive current and low parasitics– High drive current and low parasitics

– Low gate delay and high frequency

• Density & Area– Small feature size

• Power & Reliability– Low power supply voltage

L ff t t l k– Low off-state leakage



Technology Generation Scaling

,,7.0 ββ ⎯⎯ →⎯⎯⎯ →⎯⎯⎯→⎯ scalest

scalesdd

scale VVDimensions

reduction)delay (30% 7.07.0

7.07.0 )(

ββ

ββ

=×

⎯⎯ →⎯=

=×⎯⎯ →⎯−=

scalesdd

scalestdd

ICV

D

VVTkWI

ox

22 7.0 β⎯⎯ →⎯= scalesddCVE

IC Frequency & Power Trends

• Clock frequency improves 50%

• Gate delay Hz)100

1000

800

1000

)

PowerPentium

Pentium IIProcessor

R

R

1000

100W)

1000

800improves ~30% • Power increases

50%• Power =

CL V2 f

Freq

uenc

y (M

H

0.1

1

10

Chi

p Po

wer

(W)

200

400

600

requ

ency

(M H

z)

Frequency

486DX CPU

Pentium Processor

386

R100

10

1

0.1Chi

p Po

wer

(W 800

600

400

200

58

1.0 0.8 0.6 .35 .25 .18

Technology Generation (μm)

0.01 1 2 3 4 5 6 7 0

Fr0.01 0

Active switched capacitance “CL” is increasing.



Constant Voltage vs Field Scaling

• Recently: constant e-field scaling, aka voltage scaling 4

5VCC

5voltage scaling

• VCC ⌫ 1V

• VCC & modest VT

scaling• Loss in gate overdrive

(VCC-VT)

0

1

2

3

4

VC

C o

r VT (V

)

VT=.45V

VCC=1.8V

VT

(VCC- VT)Gate over drive

V CC o

r V T

(V) 4

3

2

1

59

1.4 1.0 0.8 0.6 .35 .25 .18Technology Generation (μm)

0 0 1 2 3 4 5 6 70

Voltage scaling is good for controlling IC’s active power, but it requires aggressive VT scaling for high performance

Barriers to Voltage Scaling

Voltage Scaling = Constant Electric Field Scaling

Voltage scaling is good for IC’s active power, but degrades gate over

Leakage powerShort-channel effectsSpecial circuit functionality, noise

drive. Requires VT scaling.

60

Soft errorParameter variation



Barriers to Voltage Scalingka

ge 1000 constrained Ioffmaintain Vcc/Vt

Leakage powerbt

hres

hold

Lea

k

10

100

maintain Vcc/VtShort-channel effectsSoft errorSpecial circuit functionality

61

Technology Generation

Su 10.25um 0.18um 0.13um 0.09um

functionality

Delay

D

DDLd I

VC=τ

2)1()2

(DD

TDDox

Ld

VVVC

LW

C

−=

μτ Long Channel MOSFET

2WW

1 .τ =

−+

CL Tox

VVT

V n p

05 05

0 3 0 9 13

2. .

. ( ) .( ) [1]

D

)1(DD

TSATox

Ld

VVWC

C

−=

υτ Short Channel MOSFET

62

VDD VDDn p0 9( . )

[1] C. Hu, “Low Power Design Methodologies,” Kluwer Academic Publishers, p. 25.

Performance significantly degrades when VDD approaches 3VT.



VT Scaling: VT and IOFF Trade-off

Performance vs Leakage:

VT ↓ IOFF ↑ ID(SAT) ↑ Low VT

ID(SAT)

High VTI DS

IOFFL

IOFFH

VD = VDDfixed Tox2

2 )()( TGSeff

effD VVK

LW

SATI −∝

)(1

TGS VV

eff

effsubthOFF eK

LW

II −∝∝

63

As VT decreases, sub-threshold leakage increasesLeakage is a barrier to voltage scaling

VGVTL VTH)()( 3 TGSSAToxeffD VVCWKSATI −∝ υ

IOFF vs VT

1E-04

IOFF

Log IOFF

1E-09

1E-08

1E-07

1E-06

1E-05IOFF

(A)

)( TGS VVOFF eI −∝

VTP (V)IOFF is an exponential function of VT.

1E-10-0.5 -0.45 -0.4 -0.35 -0.3 -0.25 -0.2

VT (V) - Normalized



Future: Projected Leakage Trends

1,000

10,0000.10 um0.13 um0.18 um0 25 um

1

10

100

IOFF

(nA

/ μm

) 0.25 um

IOFF (0.25um) = 1 nA/um (scales 5X)VT (0.25um) = 450 mV (scales by 15%)

St (30C) = 80 mV/decSt (100C) = 100d VT/dT = 0.7 mV/C

1

30 40 50 60 70 80 90 100 110Temperature (C)

Why Excessive leakage an Issue?

• Leakage component to active power becomes significant % of total power

100

10

1 1.E+00

1.E+01

1.E+02

Active Power

P ti

Pentium Pro Processor

R

R

101

101

100)significant % of total power• Approaching ~10% in 0.18

μm technology• Acceptable limit less than

~10%, implies serious challenge in VT scaling!

1

10-1

10-2

10-3

10-4

10-5

10-6

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

Standby power (component Transistor

Leakage T=110C)

486DX CPU

Pentium Processor386

R100

10-1

10-2

10-3

10-4

10-5

6

Pow

er

(W)

67

1.0 0.8 0.6 .35 .25 .1810

1.E-060 1 2 3 4 5 6 7

Technology Generation (μm)

10-6

Barrier high static leakage (standby) power



Power Trends

• Enable development of ultra low voltage circuits• At lower Vt,

– leakage becomes a problem

Vt Variation for optimum energy2.5

g p– Signal integrity and

Noise margin

• Multiple on-chip Vt 0.5

1

1.5

2

Nor

mal

ized

Ene

rgy

Decreasing Switching Power

Decreasing Leakage Power

Vdd =1.7V

f=20MHz

Vdd = 0..9V

Vdd = 0..5V

• Multiple on-chip Vt, dynamic Vt

• Other challenges for low voltages ?

0.50 0.2 0.4 0.6 0.8 1

Threshold Voltage (Vt)[Source: A.Chandrakasan et.al. Proc of IEEE April’95]

Trends in Microelectronics

• Improvement in device technology– Smaller circuits– Faster circuitsFaster circuits– More circuits on a chip

• Higher Integration– More complex systems– Lower cost of computation– Higher reliability

• Limitations• Limitations– Intrinsic device scaling limits– Cost of fabrication– Interconnect limitation– Large scale design management



Problems of Microelectronics• Design Cost:

– design time– fabrication time

i ibilit t i– impossibility to repair– reduce design cost to be competitive in price

• Marketing Issues:– use most recent technologies to stay competitive in

performance– volume production is inexpensive– time-to-market is critical– time-to-market is critical– evolving market

• Solution:– Hierarchical and abstraction– Different design styles– Computer-Aided-Design

Circuit and System RepresentationsComplex digital system Component gates

+Memory systems

• 3 design domains– Behavioral

• specifies what a particular system does– Structural

• how entities are connected together to effect the prescribed manner

Memory systems

manner– Physical

• how to actually build a structure that has the required connectivity to implement the prescribed behavior



Design Abstraction Levels

SYSTEM

+

CIRCUIT

GATE

MODULE

n+n+S

GD

DEVICE

CIRCUIT

For a Digital Design

• ArchitectureArchitecture• Algorithm• Module or Functional Block• logical• Switch• Circuit• Layout



Behavioral Representation Domain

• Hardware description languageVHDL V il– VHDL, Verilog

• Boolean equation• Within this domain, there are various level of

abstraction– Algorithm– Register transfer level (communication between registers)

Acc Acc + R1

CO = A.B + A.C + B.C

carry

– Boolean equations

Behavioral Representation Domain - cont.

• Algorithm level (Verilog)

output coinput a, b, c

MODULE carry (co, a,b,c)

can include speed info assign co = (a&b)|(a&c)|(b&c);

ENDMODULE



Structural Domain• The levels of abstraction include

– module– gate

input a, b, c;output co;

MODULE carry (co, a, b, c)

wire x, y, z

– switch– circuit

, y,AND g1 (x, a, b)AND g2 (y, a, c)AND g3 (z, b, c)OR g4 (co, x, y, z);

ENDMODULE

Structural Domain- cont.

bab

ac

x bc

z

y xy

co

g3g1

zg4g2

z



Transistor Level

input a, b, c;MODULE carry (co, a, b, c)

output co;wire i1, i2, i3, i4, cn;

NMOS n1(i1, vss, a)NMOS n2(i1, vss, b)

PMOS p1(i3, vdd, b);

...

ENDMODULE

p ( , , );PMOS p2(cn, i3, a);

..

.

Physical Representation

Input a, b, c;MODULE carry ;

p , , ;output co;boundary [0, 0, 100, 400]

port a aluminum width = 1 origin = [0,2]port b aluminum width = 1 origin = [0,7]

.

.port

.

ENDMODULE

Port ci polysilicon ……..



CMOS Logica a

b

s s

b

Consider them as switches

s = 0

a

b

s = 0

a b s = 0

a

b

a b

NMOS transistor PMOS transistorb

s = 1

a

b

as = 1

a

b

s = 1a b b

Inverter (A)

VDD

BA

- Low power dissipation



NAND (AB)

AA

B

A

BBA+

Out

1 1

1 0

0 1

0

1

A

B

A

B

BA.

NOR (A+B)

A

B

A

B

1 0

0 0

0 1

0

1

A

B

A . B

A + B



A

CBADDCBAF +=++= )).((

DCBAF ).( ++=

Complex Gates

B

C

D

D

A B C

VLSI Design is Inter-Disciplinary

• Breadth of field– Semiconductor physics and technology– Integrated electronics– Systems design– Testing– Computer-Aided Design

• Depth of fieldp– Complexity of fabrication technology– Difficulty of design problems

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