Post on 30-Nov-2014
description
KTH/ESDlab/HT 04/09/23 1
CMOS Arithmetic Circuits
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Multiplication of numbers
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Datapath circuit techniquesfor adders
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Binary adder
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Binary adder
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Special trick for reducing No of transistor
Cout = AB + CIN.(A + B)
SUM = ABCCN + C’OUT (A + B + CIN)
The advantage of these type realization is that transistor count is less as compared to earlier realization using expression of slide 5.
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CMOS full adder
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Mirror Adders
As discussed is class, Mirror adder circuit is having symmetrical N block and P block.
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Ripple carry adder
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Pipelined adder
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Carry bypass adder
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Carry bypass adder
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Linear carry select adder
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Linear carry select adder: critical path
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Carry look-ahead adder
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Carry look-ahead circuit structures
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Carry save (CSA) and carry propagate (CPA) adders
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Adder delays
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Adder delays summary
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Datapath circuit techniquesfor multipliers
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Multiplier definition
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Binary multiplication
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Indirect multiplication
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Array multiplier
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MxN array multiplier critical path
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Carry ripple vs. carry save array multiplier
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Carry save multiplier
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Adder cells in array multiplier
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Array multiplier floorplan
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Wallace tree multiplier
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Wallace tree multiplier
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Wallace tree multiplier
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Dadda tree multiplier
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Serial-serial multiplier
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Serial-parallel multiplier
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Parallel vs. serial multipliers
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Parallel vs. serial multipliers
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Multiplier performance
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Multiplier performance
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Multiplier summary
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Other datapath elements
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Binary shifter
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Barrel shifter
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4x4 barrel shifter
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Logarithmic shifter
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Power considerations in datapath structures
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Reducing supply voltage
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Reducing supply voltage
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Architecture trade-offs: reference datapath
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Parallel datapath
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Pipelined datapath
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Datapath architecture summary
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Glitching in NOR chain
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Glitching in RCA
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Switching activity in adders
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Switching activity in multipliers
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Layout strategy for datapath
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Layout strategy for datapaths
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Cell area: 2 vs. 3 metal layer process
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Summary