Cmos Arithmetic Circuits

KTH/ESDlab/HT 04/09/23 1

CMOS Arithmetic Circuits


Multiplication of numbers


Datapath circuit techniquesfor adders


Binary adder


Special trick for reducing No of transistor

Cout = AB + CIN.(A + B)

SUM = ABCCN + C’OUT (A + B + CIN)

The advantage of these type realization is that transistor count is less as compared to earlier realization using expression of slide 5.


CMOS full adder


Mirror Adders

As discussed is class, Mirror adder circuit is having symmetrical N block and P block.


Ripple carry adder


Pipelined adder


Carry bypass adder


Linear carry select adder


Linear carry select adder: critical path


Carry look-ahead adder


Carry look-ahead circuit structures


Carry save (CSA) and carry propagate (CPA) adders


Adder delays


Adder delays summary


Datapath circuit techniquesfor multipliers


Multiplier definition


Binary multiplication


Indirect multiplication


Array multiplier


MxN array multiplier critical path


Carry ripple vs. carry save array multiplier


Carry save multiplier


Adder cells in array multiplier


Array multiplier floorplan


Wallace tree multiplier


Dadda tree multiplier


Serial-serial multiplier


Serial-parallel multiplier


Parallel vs. serial multipliers


Multiplier performance


Multiplier summary


Other datapath elements


Binary shifter


Barrel shifter


4x4 barrel shifter


Logarithmic shifter


Power considerations in datapath structures


Reducing supply voltage


Architecture trade-offs: reference datapath


Parallel datapath


Pipelined datapath


Datapath architecture summary


Glitching in NOR chain


Glitching in RCA


Switching activity in adders


Switching activity in multipliers


Layout strategy for datapath


Layout strategy for datapaths


Cell area: 2 vs. 3 metal layer process


Summary

Cmos Arithmetic Circuits

Technology

Transcript of Cmos Arithmetic Circuits