Post on 21-Oct-2020
frohne@physik.uni-bonn.de10.02.20
*
Bonn Module Testing Plans
RD53A Testing Meeting
M. Frohne*, F. Hinterkeuser,M. Daas, M. Hamer, F. Hügging, H. Krüger
10.02.20 frohne@physik.uni-bonn.de 2
Outline
● Module readout with BDAQ53– Multi-chip (single module) readout– Multi-module readout
● Test setups & experience– Dual-chip modules [Hybridization M/S]– Quad-chip modules [RD53A/ITkPix QC]– SP Quad-chip modules [Serial Powering Tests]
frohne@physik.uni-bonn.de10.02.20
Module readout with BDAQ53
10.02.20 frohne@physik.uni-bonn.de 4
Multi-chip readout with BDAQ53
● So far:Readout one RD53A chip onsingle-chip card (SCC)in four-lane mode
● Could use BDAQ readout boardwith up to 7 Aurora lanes
10.02.20 frohne@physik.uni-bonn.de 5
Multi-chip readout with BDAQ53
● So far:Readout one RD53A chip onsingle-chip card (SCC)in four-lane mode
● Could use BDAQ readout boardwith up to 7 Aurora lanes
10.02.20 frohne@physik.uni-bonn.de 6
Multi-chip readout with BDAQ53
● Multi-chip firmware/software implemented in BDAQ53(not released, module_support branch)
● Working multi-chip readout@ 1.28 Gbps– Up to four SCCs @ 1-lane– One quad-chip module @ 1-lane
● 4-lane readout of one chip stillpossible with different firmware
10.02.20 frohne@physik.uni-bonn.de 7
Multi-chip readout with BDAQ53
● Multi-chip firmware/software implemented in BDAQ53(not released, module_support branch)
● Working multi-chip readout@ 1.28 Gbps– Up to four SCCs @ 1-lane– One quad-chip module @ 1-lane
● 4-lane readout of one chip stillpossible with different firmware
10.02.20 frohne@physik.uni-bonn.de 8
Multi-module readout with BDAQ53
● Multi-module readout not possible with BDAQ board– Only 7 MGTs on KX2 FPGA board– Limited amount of DP connectors
● Different plans for different module types– M/S dual modules:
● 4 BDAQ boards– SP quad modules:
● Readout one module with BDAQ board● Switch between modules via cross-point switch on end-of-stave card
– Common ITkPix quad modules:● New revision of BDAQ board, built-in cross-point switches
10.02.20 frohne@physik.uni-bonn.de 9
Multi-module readout – Duals
10.02.20 frohne@physik.uni-bonn.de 10
Multi-module readout – SP quads
10.02.20 frohne@physik.uni-bonn.de 11
Multi-module readout – common quads
frohne@physik.uni-bonn.de10.02.20
Test setups
10.02.20 frohne@physik.uni-bonn.de 13
Dual-chip modules
● Produce O(200) dual-chip modulesfor hybridization M/S
● Flex with two Samtec connectorsfor LV / HV / CMD / 2*RX / HitOr
● Accessible via „flex adapter“● Testing:
4 modules → 4 BDAQ boards● Glued to square aluminum plate,
fits FE-I4 cooling block
10.02.20 frohne@physik.uni-bonn.de 14
Dual-chip modules – Testbox
10.02.20 frohne@physik.uni-bonn.de 15
Dual-chip modules – Testbox
● Wooden box with removable top cover
● Filled with insulating foam and lead shielding
● Flooded with nitrogen● Cooling block for 4 duals● Chiller: Julabo FP-50● Temperature tests pending
10.02.20 frohne@physik.uni-bonn.de 16
Dual-chip modules – First tests
● Have two digital dual modules readout testing● Sucessfully tested first module last year (@ 640 Mbps)
→ In principle everything was working● No communication possible with first module anymore
– Some SMD solder joints/pads on flex are broken, could not re-solder– One chip seems broken
● Also issues with second digital module (fixed impedance adapter)– Could talk to only one chip, readout o.k., tuning o.k. (@ 640Mbps)– No Aurora sync @ 1.28Gbps– Same problem with broken solder joints (hand-soldered!)– Samtech connectors unreliable, Aurora/CMD sometimes passes with pressure only
● Other issues– Flex connectors very tight fitting, hard to unplug
10.02.20 frohne@physik.uni-bonn.de 17
Quad-chip modules (common hybrid)
● Will build testbox similar to the dual module testbox– Choose cooling, shielding, insulation based on
experience with dual module setup● Should fit 8 quad modules
– Two separate cooling blocks à 4 modules,recess with shape of module carrier
– One source mount per cooling block● Box wall openings on each side for LV / HV / pigtails● One readout board & multi-module stave adapter per block,
both to be developed
10.02.20 frohne@physik.uni-bonn.de 18
Quad-chip modules (serial powering)
● Bonn serial powering prototype will feature up to 8 RD53 quad modulesper local support
– Flex and services designed by Hans– For now only digital modules (without sensor)
● Goal of this prototype: Investigate the electrical behaviour of RD53A based modulesin a serial powering chain
– Need to provide additional test points not needed for the final detector● Stave readout using BDAQ53
Type-0 services
Cooling jigDigital quad To EoS-cardSense contacts, test points
10.02.20 frohne@physik.uni-bonn.de 19
Quad-chip modules (serial powering)
● Quad modules on dedicated module flexes– 3 layer flex with ~10 cm pigtail,
2 links / FE (only 1 link used on type-0)● Provide additional testpoints:
sense lines, Shunt-LDO reference circuit (VRext)
Digital quad module on assembly tooling after wirebonding
19
https://indico.cern.ch/event/838117/contributions/3525272/attachments/1891744/3119931/08082019_itkpixmodules_mhamer.pdfhttps://indico.cern.ch/event/838117/contributions/3525272/attachments/1891744/3122815/Addendum_-_Power_Simulation_of_Flex.pdf
M. Hamer
Voltage drop simulation for SP quad flex(Iin = 6A)- ~ 30 mV over
flex body- ~ 125 mV
including pigtail
VINmainly bottom layer
Voltage drop
https://indico.cern.ch/event/838117/contributions/3525272/attachments/1891744/3119931/08082019_itkpixmodules_mhamer.pdfhttps://indico.cern.ch/event/838117/contributions/3525272/attachments/1891744/3119931/08082019_itkpixmodules_mhamer.pdfhttps://indico.cern.ch/event/838117/contributions/3525272/attachments/1891744/3119931/08082019_itkpixmodules_mhamer.pdfhttps://indico.cern.ch/event/838117/contributions/3525272/attachments/1891744/3122815/Addendum_-_Power_Simulation_of_Flex.pdfhttps://indico.cern.ch/event/838117/contributions/3525272/attachments/1891744/3122815/Addendum_-_Power_Simulation_of_Flex.pdfhttps://indico.cern.ch/event/838117/contributions/3525272/attachments/1891744/3122815/Addendum_-_Power_Simulation_of_Flex.pdf
10.02.20 frohne@physik.uni-bonn.de 20
Current status
● First digital module assembled,wirebonded and integrated on structure,electrical testing ongoing
– Chips for more modules available,but assembly currently halted
● Showstopper (bug) in EoS-Card delayed stave commissioning– Hardware fix successfully applied, EoS-Card now operational
● Communication with module not yet successful● Module input IV curve looks ok, but slope higher than expected:
– FE2: current through Rext,A ~ factor 10 too small,looks like high-ohmic SLDO failure
– Likely caused by an accidental short during testing/debugging● Debugging of setup and remaining 3 FEs still ongoing
Expected from wafer probing data:Reff = 0.103 OhmVofs = 0.95 V
frohne@physik.uni-bonn.de10.02.20
Thank you!
frohne@physik.uni-bonn.de10.02.20
frohne@physik.uni-bonn.de10.02.20
frohne@physik.uni-bonn.de10.02.20
Backup
10.02.20 frohne@physik.uni-bonn.de 25
Serial powering
● Type-0 PCB provides power supply and data routing● Module slots can be shorted / bypassed as needed● Modules placed on Al-stave fixed to a cooling structure
– Rather easily assembled, accessed and maintained
Type-0 services
Cooling jigDigital quad To EoS-cardSense contacts, test points
Digital quad module on local support connected to type-0 services
Type-0 services
Sense contacts, test points
10.02.20 frohne@physik.uni-bonn.de 26
Serial powering
● End-of-Structure (EoS) card provides interface to the DAQ system● Two crosspoint switches (XPTs) for up-/downlinks● XPTs and GPIO configured via I2C
– I2C backend included in BDAQ firmware
Type-0 services
GPIOs
XPT
HV configuration
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