Post on 28-Mar-2015
ATLAS: Hardware and Upgrades
Liverpool, HEP Christmas Meeting
17 December 2007
Paul Dervan
Contents
SCT ENDCAP-C past year Ashley, Katharine, Dave, George, Helen, Joost, Neil J, Neil T, Nick, Paul D, Paul P, Phil, Sergey, Scott, Tim + many SCT colleagues
General ATLAS
Super-LHC upgrade activitiesAshley, Gianluigi, Joost, Neil, Peter, Phil, Tony +others joining
EC-C assembled in Liverpool.Last Year:• Transported to CERN• Tested and Repaired This year:• Installation into ATLAS• Service connections• Warm tests• Cooling installation
• 4 barrels• 2 endcaps with 9 disks each • ~60 m2 of silicon strip detectors• ~4000 modules• 6.3 Million channels• |η| < 2.5
Sct and Inner Detector
ID-C Status at end of 2006
• SCT integrated into the TRT
• Models tested OK
• Cosmic ray tests carried out
• Waiting for installation into
ATLAS
SCT EC Installation• EC-C was moved to pit on June 18th Plan
was to move the week before (Friday)
but due to rain postponed to Monday
• EC-C stayed the weekend in the
unloading dock of SR1
• The transport went very smoothly
• Only one crane was necessary
to move EC from SR1 to SCX1
EC-C arrived in the pit around 11am
Accelerations measured < 0.2g
SCT EC Installation• Alignment of EC-C (Tuesday morning)
and insertion was completed by 19h
• EC-C was positioned ~3.5mm
away from its nominal position
SCT EC In Position
• Phase 1 – Pre-Installation – June - July 2007 – (Complete)• Phase 2 – LMTs (Connect & DC test) – August 2007 – (Complete)• Phase 3 – Fibres (Connect & DwD) – August 2007 – (Complete)• Phase 4 – Cooling installation – November - December 2007• Phase 5 – Power modules with cooling – January 2007 Sign off the End-cap (Pixel can now connect-up)• Phase 6 – Full module readout with cooling – March 2007
SCT Installation and Commissioning
The rest of the ID
• Has been painful because of a short to LAr ground (insulation failure of the sliding rails).
May 24
May 29
June 25 - June 28 2007
Pixel Installation
VA-A
VA-C
Ion pump
Both Calorimeter beam pipes are now in position and connected to the Be pipe
Calorimeter beam pipe installation
22ndnd June 07 June 07
End-cap Toroids installation
ATLAS Inner Detector Upgrade
• To keep ATLAS running more than 10 years the inner tracker has to be replaced (Current tracker designed to survive up to 730 fb-1 ≈ 10Mrad in strip detectors)
• For the luminosity-upgrade (SLHC) the new tracker will have to cope with >3000 fb-1– much higher occupancy levels
– much higher dose rates 1016neq/cm2 pixel b-layer
9×1014neq/cm2 middle layers
5×1014neq/cm2 outer layers
• For a new tracker by 2015, major international R&D programme already underway. (Current ATLAS Inner Detector TDR CERN/LHCC/97-16 is now 10 years old)
Pixels:Short (2.4 cm) -strips (stereo layers):Long (9.6 cm) -strips (stereo layers):
r=5cm, 12cm, 18cm, 27cmr=38cm, 49cm, 60cmr=75cm, 95cm
z=±40cmz=±100cmz=±190cm
New SLHC Layout
Including disks this leads to:
Pixels: 5 m2, ~300,000,000 channels
Short strips: 60 m2, ~28,000,000 channels
Long strips: 100 m2, ~15,000,000 channels
WP3: Sensors
1 01 4
1 01 5
1 01 6
0
5 0 0 0
1 0 0 0 0
1 5 0 0 0
2 0 0 0 0
2 5 0 0 0
# e
lec
tro
ns
1 M e V n f lu e n c e [c m-2
]
1 01 4
1 01 5
1 01 6
0
5 0 0 0
1 0 0 0 0
1 5 0 0 0
2 0 0 0 0
2 5 0 0 0
# e
lec
tro
ns
F lu e n c e [c m-2
]
p F Z S i 2 8 0 m ; 2 5 n s ; -3 0 ° C [1 ]
p -M C z S i 3 0 0 m ;0 .2 -2 .5 s ; -3 0 ° C [2 ]
n E P I S i 7 5 m ; 2 5 n s ; -3 0 ° C [3 ]
n E P I S i 1 5 0 m ; 2 5 n s ; -3 0 °C [3 ]
s C V D D ia m 7 7 0 m ; 2 5 n s ; + 2 0 °C [4 ]
p C V D D ia m 3 0 0 m ; 2 5 n s ; + 2 0 °C [4 ]
n E P I S iC 5 5 m ; 2 .5 s ; + 2 0 °C [5 ]
3 D F Z S i 2 3 5 m [6 ]
Comparison of measured collected charge on different radiation-hard materials and devices (M. Bruzzi, H. F.-W. Sadrozinski, A. Seiden, NIM A 579 (2007) 754–761)
Sign
al (
elec
tron
s)
Signal vs Dose +
++
Latest n-in-p datafrom Liverpool (1000V) Micron
Semiconductor UK Ltd
Liverpool are pushing the n-in-p sensor designs (Gianluigi)
WP3: Irradiated Microstrip CCE(V)
140mm and 300mm thickness(Micron)Doses up to 1016neq/cm2 (Ljubljana reactor neutrons )
Short microstrip layers to withstand 9×1014neq/cm2 (50% neutrons) at 500V with 750e- noise, → can expect S/N ≈12
Tony Affolder, Gianluigi Case
1.6E15 cm-2
0
5
10
15
20
300 500 700 900 1100
Bias Voltage (V)
Co
llecte
d C
harg
e (
ke-)
300 microns
140 microns
3.0E15 cm-2
0
5
10
15
20
300 500 700 900 1100Bias Voltage (V)
Co
llecte
d C
harg
e (
ke
- )
300 microns
140 microns
1.0E16 cm-2
0.0
5.0
10.0
15.0
20.0
300 500 700 900 1100Bias Voltage (V)
Co
llecte
d C
harg
e (
ke
-)300 microns
140 microns
5.0E14 cm-2
0
2
4
6
8
10
12
14
16
18
20
100 150 200 250 300 350 400 450 500 550
Bias Voltage (V)
Co
lle
cte
d C
ha
rg
e (
ke
-)
300 microns140 microns
WP4: SLHC Hybrid conceptual layout
Digital I/O
Power/Aux Bus
99mm
99mm
MCC
Power Regulation
24mm
74mm
SE
NS
OR
Readout ASICs
Ashley (provisional)
• 2 ‘fingers’ per hybrid populated with 2 columns of 10 ASICs (40 ASICs total)
• Electrically one item?
• 4 Cu Layers with Kapton dielectric (example from LHCb VELO)
• Working closely with chip designers
• Working on how to layout the redundancy (various ways)
HV
MCC: Module Controller Chip
WP7: Single-sided Module Concept
Results Single-sided 1W/sensor Cooling -30 @8000W/m2
1W/Sensor0.38W/ChipMax Chip temp: -10CMax Si Temp: -19.46CTemp Gradient over Si: 1.17C
Thermal Runaway - Temperature
NB. Conductivity of air = 0 for ease of comparison!
SSM Thermal Runaway(25mm fingers, 0.5mm thk TPG, 0.75mm thk C-C bridge, 2mm dia. tube, 8000W/mK)
No Step, Eg=1.1
0.0
1.0
2.0
3.0
4.0
5.0
6.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Power Density (mW/mm2 @ 0 deg C)
To
tal
Sil
ico
n P
ow
er
(W)
0.25 W per ASIC
0.30 W per ASIC
0.35 W per ASIC
0.40 W per ASIC
ANSYS - 0.38
Summary
• SCT: SCT End-cap C installed in ATLAS Awaiting final tests with the cooling
• Upgrade: Liverpool is involved (and leading) in quite a few areas The Upgrade effect is increasing all the time
Merry Christmas