A 130 nm Sub-VT Power-Gated Processor for Body Sensor Network Applications

Yanqing ZhangYousef Shakhsheer

MotivationTo reduce energy while idling without

degrading performance, especially in battery constrained applications

i.e. ECG algorithm – Sampling rate is 1 kHzAverage time to process one sample is 20

µs 980 µs of idle timeOpportunity for savings!

Methodology• RTL• CPF • Place files in RTL

Compiler • Load Encounter• Commit CPF in Encounter

Methodology• Move power domain

macro modules• Encounter leaves a row

and column between different domains

Methodology• Add power switches in

respective power domain

Methodology• Specify switch topology

Methodology• Specify Global Net

Connections• Verilog has no concept of

VDD and GNDs, let alone different power domains

• Use “Override prior connection” button to your convenience

• Important step in flow

Methodology• A successfully

floorplanned design that is power-gate ready

• Rest of flow is same as SOC place and route flow

• Yay! So CPF retains the convenience synthesis flow brings us, with powerful flexibility for low power design

Our design

Header Topologies – Lumped vs Distributed

Metric Best ChoiceIR Drop Lumped

Delay degradation DistributedPower gating savings Distributed

Recovery time LumpedBreakeven cycles DistributedEase of Design Lumped

What we learned• Required to break the

VDD connection on the standard cell libraries

• Inherent VDD makes our life harder

What we learned • Our set of tools will not

automatically characterize headers and decide on sizing

• Header sizing is hard• Trade offs in metrics

8.4 um 16.8 um 33.6 um 67.2 um 134.4 um0.95

Switching Time Overhead

Header Sizing

8.4 um 16.8 um 33.6 um 67.2 um 134.4 um0.920.930.940.950.960.970.980.99

Vrail Min

8.4 um 16.8 um 33.6 um 67.2 um 134.4 um0

0.0050.01

0.0150.02

0.0250.03

0.0350.04

0.0450.05

Energy During Power Gat-ing

Header Sizing

8.4 um 16.8 um 33.6 um 67.2 um 134.4 um0

0.020.040.060.080.1

0.120.140.160.180.2

Recovery Time

8.4 um 16.8 um 33.6 um 67.2 um 134.4 um0.00

200.00

400.00

600.00

800.00

1000.00

1200.00

Break Even Cycles

Class Specific Action & Future Work• Using CPF to do header

insertion• Making tutorial

• Script based flow• Tool for analyzing header

sizing

A 130 nm Sub-VT Power-Gated Processor for Body Sensor Network Applications

Documents

Transcript of A 130 nm Sub-VT Power-Gated Processor for Body Sensor Network Applications

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A 130 nm Sub-VT Power-Gated Processor for Body Sensor Network Applications Yanqing Zhang Yousef Shakhsheer 1.

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