Post on 09-Jan-2022
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
1
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
1Gbit - 64M x 16 DDR3 SDRAM
Features• Tin-leadballmetallurgy
• VDD=VDDQ=1.5V±0.075V
• 1.5Vcenter-terminatedpush/pullI/O
• Differentialbidirectionaldatastrobe
• 8n-bitprefetcharchitecture
• Differentialclockinputs(CK,CK#)
• 8internalbanks
• Nominalanddynamicon-dietermination(ODT)fordata,strobe,andmasksignals
• ProgrammableCASREADlatency(CL)
• POSTEDCASADDITIVElatency(AL)
• ProgrammableCASWRITElatency(CWL)basedontCK
• Fixedburstlength(BL)of8andburstchop(BC)of4(viathemoderegisterset[MRS])
• SelectableBC4orBL8on-the-fly(OTF)
• Selfrefreshmode
• TCof0°Cto95°C
• 64ms,8192cyclerefreshat0°Cto85°C
• 32ms,8192cyclerefreshat85°Cto95°C
Table 1: Key Timing Parameters
Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns)
-15E 1333 9-9-9 13.5
*Backward compatible to 1066, CL=7
Table 2: Addressing
Parameter 64 Meg x 16
Configuration 8 Meg x 16 x 8 banks
Refresh Count 8K
Row Address 8K (A[12:0])
Bank Address 8 (BA[2:0])
Column Address 1K (A[9:0])
Page Size 2KB
Options Code
• Configuration:
• 64Megx16 64M16
• FBGApackage(Sn63/Pb37)
• 96-ballFBGA(8mmx14mm) JT
• Timing-cycletime
• 1.5ns@CL=9(DDR3-1333) -15E
• Operatingtemperature
• Commercial(0°C≤TC≤+95°C) None
• Industrial(-40°C≤TC≤+95°C) IT
• Automotive(-40°C≤TC≤+105°C) ET
• Selfrefreshtemperature(SRT)
• Automaticselfrefresh(ASR)
• Writeleveling
• Multipurposeregister
• Outputdrivercalibration
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
2
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Functional DescriptionDDR3SDRAMusesadoubledataratearchitecturetoachievehigh-speedoperation.Thedoubledataratearchitectureisan8n-prefetcharchitecturewithaninterfacedesignedtotransfertwodatawordsperclockcycleattheI/Opins.AsinglereadorwriteoperationfortheDDR3SDRAMeffectivelyconsistsofasingle8n-bit-wide,four-clockcycledatatransferattheinternalDRAM core and eight corresponding n-bit-wide, onehalf-clock-cycledatatransfersattheI/Opins.
The differential data strobe (DQS, DQS#) is transmittedexternally,alongwithdata,foruseindatacaptureattheDDR3SDRAM input receiver. DQS is center-aligned with data forWRITEs.The readdata is transmittedby theDDR3SDRAMandedge-alignedtothedatastrobes.
TheDDR3SDRAMoperatesfromadifferentialclock(CKandCK#).ThecrossingofCKgoingHIGHandCK#goingLOWisreferredtoasthepositiveedgeofCK.Control,command,andaddress signalsare registeredat everypositiveedgeofCK.InputdataisregisteredonthefirstrisingedgeofDQSaftertheWRITEpreamble, andoutput data is referencedon the firstrisingedgeofDQSaftertheREADpreamble.
Read and write accesses to the DDR3 SDRAM are burst-oriented.Accessesstartataselected locationandcontinuefor a programmed number of locations in a programmedsequence. Accesses begin with the registration of anACTIVATE command,which is then followed by aREADorWRITEcommand.TheaddressbitsregisteredcoincidentwiththeACTIVATEcommandareusedtoselectthebankandrowtobeaccessed.Theaddressbits registeredcoincidentwiththeREADorWRITEcommandsareusedtoselectthebankandthestartingcolumnlocationfortheburstaccess.
ThedeviceusesaREADandWRITEBL8andBC4.Anautoprechargefunctionmaybeenabledtoprovideaself-timedrowprechargethatisinitiatedattheendoftheburstaccess.
As with standard DDR SDRAM, the pipelined, multibankarchitectureofDDR3SDRAMallowsforconcurrentoperation,therebyprovidinghighbandwidthbyhidingrowprechargeandactivationtime.
A self refreshmode is provided, alongwith a power-saving,power-downmode.
Industrial TemperatureThe industrial temperature (IT) device requires that the casetemperaturenotexceed–40°Cor95°C.JEDECspecificationsrequiretherefreshratetodoublewhenTCexceeds85°C;thisalsorequiresuseof thehigh-temperatureself refreshoption.Additionally,ODTresistanceandthe input/output impedancemustbederatedwhenTCis<0°Cor>95°C.
General Notes• Thefunctionalityandthetimingspecificationsdiscussed
inthisdatasheetarefortheDLLenablemodeofoperation(normaloperation).
• Throughoutthisdatasheet,variousfiguresandtextrefertoDQsas“DQ.”DQistobeinterpretedasanyandallDQcollectively,unlessspecificallystatedotherwise.
• Theterms“DQS”and“CK”foundthroughoutthisdatasheetaretobeinterpretedasDQS,DQS#andCK,CK#respectively,unlessspecificallystatedotherwise.
• Completefunctionalitymaybedescribedthroughoutthedocument;anypageordiagrammayhavebeensimplifiedtoconveyatopicandmaynotbeinclusiveofallrequirements.
• Anyspecificrequirementtakesprecedenceoverageneralstatement.
• Anyfunctionalitynotspecificallystatedisconsideredundefined,illegal,andnotsupported,andcanresultinunknownoperation.
• RowaddressingisdenotedasA[n:0].Forexample,1Gb:n=12(x16);1Gb:n=13(x4,x8);2Gb:n=13(x16)and2Gb:n=14(x4,x8);4Gb:n=14(x16);and4Gb:n=15(x4,x8).
• DynamicODThasaspecialusecase:whenDDR3devicesarearchitectedforuseinasinglerankmemoryarray,theODTballcanbewiredHIGHratherthanrouted.RefertotheDynamicODTSpecialUseCasesection.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
3
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
General Notes (continued)• Ax16device’sDQbusiscomprisedoftwobytes.If
onlyoneofthebytesneedstobeused,usethelowerbytefordatatransfersandterminatetheupperbyteasnoted:
• ConnectUDQStogroundvia1kΩ*resistor.
• ConnectUDQS#toVDDvia1kΩ*resistor.
• ConnectUDMtoVDDvia1kΩ*resistor.
• ConnectDQ[15:8]individuallytoeitherVSS,VDD,orVREFvia1kΩresistors,*orfloatDQ[15:8].
*IfODT isused,1kΩ resistorshouldbechangedto4xthatoftheselectedODT.
Figure 1: 64 Meg x 16 Functional Block Diagram
Figure 4: 128 Meg x 8 Functional Block Diagram
Bank 5Bank 6
Bank 7
Bank 4
Bank 7
Bank 4Bank 5
Bank 6
14
Row-address
MUX
Controllogic
Column-addresscounter/
latch
Mode registers
10
Co
mm
and
d
eco
de
A[13:0]BA[2:0]
14
Addressregister
17
8,192
I/O gatingDM mask logic
Columndecoder
Bank 0memory
array(16,384 x 128 x 64)
Bank 0row-
addresslatchand
decoder
16,384
Sense amplifiers
Bankcontrol
logic
16
Bank 1Bank 2
Bank 3
14
7
3
3
Refreshcounter
8
64
64
64
DQS, DQS#
Columns 0, 1, and 2
Columns 0, 1, and 2
ZQCL, ZQCS
To ODT/output drivers
READ drivers DQ[7:0]
READFIFOanddataMUX
Data
8
3
Bank 1Bank 2
Bank 3
DM/TDQS(shared pin)
TDQS#
CK, CK#
DQS, DQS#
ZQ CALZQ
RZQ
CK, CK#
RAS#
WE#
CAS#
CS#
ODT
CKE
RESET#
CK, CK#
DLL
DQ[7:0]
DQ8(1 . . . 8)
(1, 2)
sw1 sw2
VDDQ/2
RTT,nom RTT(WR)
sw1 sw2
VDDQ/2
RTT,nom RTT(WR)
sw1 sw2
VDDQ/2
RTT,nom RTT(WR)
BC4 (burst chop)
BC4BC4
WRITE drivers
and input logic
Datainterface
Column 2(select upper or
lower nibble for BC4)
(128x64)
ODTcontrol
VSSQ A12
OTF
OTF
Figure 5: 64 Meg x 16 Functional Block Diagram
Bank 5Bank 6
Bank 7
Bank 4
Bank 7
Bank 4Bank 5
Bank 6
13
Row-address
MUX
Controllogic
Column-addresscounter/
latch
Mode registers
10
Co
mm
and
d
eco
de
A[12:0]BA[2:0]
13
Addressregister
16
(128x128)
16,384
I/O gatingDM mask logic
Columndecoder
Bank 0memory
array(8192 x 128 x 128)
Bank 0row-
addresslatchand
decoder
8,192
Sense amplifiers
Bankcontrollogic
16
Bank 1Bank 2
Bank 3
13
7
3
3
Refreshcounter
16
128
128
128
LDQS, LDQS#, UDQS, UDQS#
Column 0, 1, and 2
Columns 0, 1, and 2
ZQCL, ZQCS
To ODT/output drivers
BC4
READ drivers
DQ[15:0]
READFIFOanddataMUX
Data
16
BC4 (burst chop)
3
Bank 1Bank 2
Bank 3
LDM/UDM
CK, CK#
LDQS, LDQS#
UDQS, UDQS#
ZQ CALZQ
RZQ
ODT
CKE
CK, CK#
RAS#
WE#
CAS#
CS#
RESET#
CK, CK#
DLL
DQ[15:0]
(1 . . . 16)
(1 . . . 4)
(1, 2)
sw1 sw2
VDDQ/2
RTT,nom RTT(WR)
BC4
sw1 sw2
VDDQ/2
RTT,nom RTT(WR)
sw1 sw2
VDDQ/2
RTT,nom RTT(WR)
Column 2(select upper or
lower nibble for BC4)
Datainterface
WRITE drivers
andinputlogic
ODTcontrol
VSSQ A12
OTF
OTF
1Gb: x4, x8, x16 DDR3 SDRAMFunctional Block Diagrams
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
4
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Figure 2: 96-Ball FBGA – x16 (Top View)
Figure 8: 96-Ball FBGA – x16 (Top View)
1 2 3 4 6 7 8 95
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TVSS
VDD
VSS
VSS
NC CS#
BA0
A3
A5
A7
RESET#
NC VSS
VREFDQ VDDQ DQ4
RAS#
CAS#
WE#
BA2
A0
A2
A9
NC
VSSQ
VSSQ
VSSQ VDD VSS
VDDQ DQ2 LDQS
DQ6 LDQS#
VDDQ
VDDQ DQ13 DQ15
DQ11 DQ9
VDDQ UDM
VSS VSSQ DQ0
ODT VDD
VDD
NC
A11
A1
NC
A10/AP ZQ
VREFCA
BA1
A4
A6
A8
CK VSS
DQ7 DQ5 VDDQ
NC
CKE
NC
VSS
VDD
VSS
VDD
VSS
VDD
DQ8
UDQS# DQ14 VSSQ
DQ1 DQ3 VSSQ
VSS VSSQ
UDQS
DQ12 VDDQ VSS
DQ10 VDDQ
VSSQ VDD
LDM VSSQ VDDQ
CK# VDD
A12/BC#
Notes: 1. Ball descriptions listed in Table 5 (page 23) are listed as “x4, x8” if unique; otherwise,x4 and x8 are the same.
2. A comma separates the configuration; a slash defines a selectable function.Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# appliesto the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-fined in Table 5).
1Gb: x4, x8, x16 DDR3 SDRAMBall Assignments and Descriptions
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Notes:
1. BalldescriptionslistedinTable3(page5)arelistedas“x4,x8”ifunique;otherwise,x4andx8arethesame.
2. Acommaseparatestheconfiguration;aslashdefinesaselectablefunction.ExampleD7=NF,NF/TDQS#.NFappliestothex4configurationonly.NF/TDQS#appliestothex8configurationonly—selectablebetweenNForTDQS#viaMRS(symbolsaredefinedinTable3).
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
5
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Table 3: 96-Ball FBGA – x16 Ball Descriptions
Symbol Type Description
A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10/AP, A11, A12/BC#
Input
Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) ill be performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 20 (page 32).
BA0, BA1, BA2 InputBank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA.
CK, CK# InputClock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
CKE Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle),or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA.
CS# InputChip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA.
LDM InputInput data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte input data is masked when LDM is sampled HIGH along with the input data during a write access. Although the LDM ball is input-only, the LDM loading is designed to match that of the DQ and DQS balls. LDM is referenced to VREFDQ.
ODT Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS, and NF/TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA.
RESET# InputReset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and DC LOW ≤ 0.2 × VDDQ. RESET# assertion and desertion are asynchronous.
UDM InputInput data mask: UDM is an upper-byte, input mask signal for write data. Upper byte input data is masked when UDM is sampled HIGH along with that input data during a WRITE access. Although the UDM ball is input-only, the UDM loading is designed to match that of the DQ and DQS balls. UDM is referenced to VREFDQ.
DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7
I/O Data input/output: Lower byte of bidirectional data bus for the x16 configuration. DQ[7:0] are referenced to VREFDQ.
DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15
I/O Data input/output: Upper byte of bidirectional data bus for the x16 configuration. DQ[15:8] are referenced to VREFDQ.
LDQS, LDQS# I/O Lower byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data.
UDQS, UDQS# I/OUpper byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. DQS is center-aligned to write data.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
6
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Table 3: 96-Ball FBGA – x16 Ball Descriptions (continued)
Electrical Specifications - Absolute Ratings
Stresses greater than those listed in Table 4 may causepermanentdamagetothedevice.Thisisastressratingonly,and functionaloperationof thedeviceat theseoranyotherconditionsoutsidethoseindicatedintheoperationalsections
of this specification is not implied. Exposure to absolutemaximumratingconditionsforextendedperiodsmayadverselyaffectreliability.
Table 4: Absolute Maximum Ratings
Symbol Parameter Min Max Unit Notes
VDD VDD supply voltage relative to VSS -0.4 1.975 V 1
VDDQ VDDQ supply voltage relative to VSSQ -0.4 1.975 V
VIN, VOUT Voltage on any ball relative to VSS -0.4 1.975 V
TC Operating case temperature – Commercial 0 95 °C 2, 3
Operating case temperature – Industrial -40 95 °C 2, 3
TSTG Storage temperature -55 150 °C
Notes:
1. VDDandVDDQmustbewithin300mVofeachotheratalltimes,andVREFmustnotbegreaterthan0.6×VDDQ.WhenVDDandVDDQare<500mV,VREFcanbe≤300mV.
2. MAXoperatingcasetemperature.TCismeasuredinthecenterofthepackage.
3. DevicefunctionalityisnotguaranteediftheDRAMdeviceexceedsthemaximumTCduringoperation.
Symbol Type Description
VDD Supply Power supply: 1.5V ±0.075V.
VDDQ Supply DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immunity.
VREFCA SupplyReference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation.
VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (excluding self refresh) for proper device operation.
VSS Supply Ground.
VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.
ZQ Reference External reference ball for output drive calibration: This ball is tied to an external 240Ω resistor (RZQ), which is tied to VSSQ.
NC – No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls).
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
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1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Table 5: Thermal Characteristics
Description Value Unit Symbol Notes
Operating case temperature – Commercial
0 to +85 °C TC 1, 2, 3
0 to +95 °C TC 1, 2, 3, 4
Operating case temperature – Industrial
-40 to +85 °C TC 1, 2, 3
-40 to +95 °C TC 1, 2, 3, 4
Junction-to-case (TOP) 96-ball (JT) TBD °C/W ΘJC 5
Notes:
1. MAXoperatingcasetemperature.TCismeasuredinthecenterofthepackage.
2. AthermalsolutionmustbedesignedtoensuretheDRAMdevicedoesnotexceedthemaximumTCduringoperation.
3. DevicefunctionalityisnotguaranteediftheDRAMdeviceexceedsthemaximumTCduringoperation.
4. IfTCexceeds85°C,theDRAMmustberefreshedexternallyat2xrefresh,whichisa3.9μsintervalrefreshrate.TheuseofSRTorASR(ifavailable)mustbeenabled.
5. Thethermalresistancedataisbasedoffofanumberofsamplesfrommultiplelotsandshouldbeviewedasatypicalnumber.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
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1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Table 6: DDR3L Input/Output Capacitance
Note1appliestotheentiretable,
Capacitance Parameters SymbolDDR3L-1333
Unit NotesMin Max
CK and CK# CCK 0.8 1.4 pF
ΔC: CK to CK# CDCK 0 0.15 pF
Single-end I/O: DQ, DM CIO 1.5 2.5 pF 2
Differential I/O: DQS, DQS#, TDQS, TDQS# CIO 1.5 2.5 pF 3
ΔC: DQS to DQS#, TDQS, TDQS# CDDQS 0 0.15 pF 3
ΔC: DQ to DQS CDIO –0.5 0.3 pF 4
Inputs (CTRL, CMD, ADDR) CI 0.75 1.3 pF 5
ΔC: CTRL to CK CDI_CTRL –0.4 0.2 pF 6
ΔC: CMD_ADDR to CK CDI_CMD_ADDR –0.4 0.4 pF 7
ZQ pin capacitance CZQ – 3.0 pF
Reset pin capacitance CRE – 3.0 pF
Notes:
1. VDD=1.5V±0.075mV,VDDQ=VDD,VREF=VSS,f=100MHz,TC=25°C.VOUT(DC)=0.5×VDDQ,VOUT=0.1V(peak-to-peak).
2. DMinputisgroupedwithI/Opins,reflectingthefactthattheyarematchedinloading.
3. IncludesTDQS,TDQS#.CDDQSisforDQSvs.DQS#andTDQSvs.TDQS#separately.
4. CDIO=CIO(DQ)-0.5×(CIO(DQS)+CIO(DQS#)).
5. ExcludesCK,CK#;CTRL=ODT,CS#,andCKE;CMD=RAS#,CAS#,andWE#;ADDR=A[n:0],BA[2:0].
6. CDI_CTRL=CI(CTRL)-0.5×(CCK(CK)+CCK(CK#)).
7. CDI_CMD_ADDR=CI(CMD_ADDR)-0.5×(CCK(CK)+CCK(CK#)).
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
9
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Electrical Characteristics - IDD Specifications and Conditions
Within the following IDD measurement tables, the followingdefinitionsandconditionsareused,unlessstatedotherwise:
• LOW:VIN≤VIL(AC)max;HIGH:VIN≥VIH(AC)min.
• Midlevel:InputsareVREF=VDD/2.
• RONsettoRZQ/7(34Ω)
• RTT,nomsettoRZQ/6(40Ω)
• RTT(WR)settoRZQ/2(120Ω)
• QOFFisenabledinMR1.
• ODTisenabledinMR1(RTT,nom)andMR2(RTT(WR)).
• TDQSisdisabledinMR1.
• ExternalDQ/DQS/DMloadresistoris25ΩtoVDDQ/2.
• BurstlengthsareBL8fixed.
• ALequals0(exceptinIDD7).
• IDDspecificationsaretestedafterthedeviceisproperlyinitialized.
• InputslewrateisspecifiedbyACparametrictestconditions.
• OptionalASRisdisabled.
• Readbursttypeusesnibblesequential(MR0[3]=0).
• Looppatternsmustbeexecutedatleastoncebeforecurrentmeasurementsbegin.
Table 7: DDR3L Timing Parameters Used for IDD Measurements – Clock Units
IDD Parameter
DDR3L-1333
Unit-15
9-9-9
tCK (MIN) IDD 1.5 ns
CL IDD 9 CK
tRCD (MIN) IDD 9 CK
tRC (MIN) IDD 33 CK
tRAS (MIN) IDD 24 CK
tRP (MIN) 9 CK
tFAW x16 30 CK
tRRD IDD x16 5 CK
tRFC 1Gb 74 CK
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
10
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Electrical Characteristics - IDD Specifications
Table 8: IDD Maximum Limits
Speed BinDDR3L-1033 Units Notes
IDD Width
IDD0 x16 80 mA 1, 2
IDD1 x16 110 mA 1, 2
IDD2P0 (Slow) All 12 mA 1, 2
IDD2P1 (Fast) All 30 mA 1, 2
IDD2Q All 35 mA 1, 2
IDD2N All 40 mA 1, 2
IDD2NT x16 60 mA 1, 2
IDD3P All 30 mA 1, 2
IDD3N x16 45 mA 1, 2
IDD4R x16 165 mA 1, 2
IDD4W x16 180 mA 1, 2
IDD5B All 165 mA 1, 2
IDD6 All 8 mA 1, 2, 3,
IDD6ET All 10 mA 1, 4
IDD7 x16 265 mA 1, 2
IDD8 All IDD2P0 + 2mA mA 1, 2
Notes:
1. TC=85°C;SRTandASRaredisabled.
2. EnablingASRcouldincreaseIDDxbyuptoanadditional2mA.
3. RestrictedtoTC(MAX)=85°C.
4. TC=85°C;ASRandODTaredisabled;SRTisenabled.
5. TheIDDvaluesmustbederated(increased)onIT-optionandAT-optiondeviceswhenoperatedoutsideoftherange0°C≤TC≤+85°C:
6.
A. WhenTC<0°C:IDD2P0,IDD2P1andIDD3Pmustbederatedby4%;IDD4RandIDD5Wmustbederatedby2%;andIDD6andIDD7mustbederatedby7%.
B. WhenTC>85°C:IDD0,IDD1,IDD2N,IDD2NT,IDD2Q,IDD3N,IDD3P,IDD4R,IDD4W,andIDD5Bmustbederatedby2%;IDD2Pxmustbederatedby30%.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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Form #: CSI-D-685 Document 007
Electrical Specifications – DC and AC
DC Operating Conditions
Table 9: DC Electrical Characteristics and Operating Conditions
AllvoltagesreferencedtoVSS.
Parameter/Condition Symbol Min Nom Max Unit Notes
Supply voltage VDD
1.425 1.5 1.575 V 1, 2
I/O Supply voltage VDDQ
Input leakage currentAny input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.1V (all other pins not under test = 0V)
II -2 - 2 µA -
VREF supply leakage currentVREFDQ = VDD/2 or VREFCA = VDD/2 (all other pins not under test = 0V)
IVREF -1 - 1 µA 4
Notes:
1. VDDandVDDQmusttrackoneanother.VDDQmustbe≤VDD.VSS=VSSQ.
2. VDDandVDDQmayincludeACnoiseof±50mV(250kHzto20MHz)inadditiontotheDC(0Hzto250kHz)specifications.VDDandVDDQmustbeatsamelevelforvalidACtimingparameters.
3. VREF(seeTable10onpage12).
4. Theminimumlimitrequirementisfortestingpurposes.TheleakagecurrentontheVREFpinshouldbeminimal.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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Form #: CSI-D-685 Document 007
Input Operating Conditions
Table 10: DC Electrical Characteristics and Input Conditions
AllvoltagesreferencedtoVSS.
Parameter/Condition Symbol Min Nom Max Unit Notes
VIN low; DC/commands/address busses VIL VSS NA - V
VIN high; DC/commands/address busses VIH - NA VDD V
Input reference voltage command/address bus VREFCA(DC) 0.49 × VDD 0.5 × VDD 0.51 × VDD V 1, 2
I/O reference voltage DQ bus VREFDQ(DC) 0.49 × VDD 0.5 × VDD 0.51 × VDD V 2, 3
I/O reference voltage DQ bus in SELF REFRESH VREFDQ(SR) VSS 0.5 × VDD VDD V 4
Command/address termination voltage (system level, not direct DRAM input) VTT - 0.5 × VDDQ - V 5
Notes:
1. VREFCA(DC)isexpectedtobeapproximately0.5×VDDandtotrackvariationsintheDClevel.Externallygeneratedpeaknoise(noncommonmode)onVREFCAmaynotexceed±1%×VDDaroundtheVREFCA(DC)value.Peak-to-peakACnoiseonVREFCAshouldnotexceed±2%ofVREFCA(DC).
2. DCvaluesaredeterminedtobelessthan20MHzinfrequency.DRAMmustmeetspecificationsiftheDRAMinducesadditionalACnoisegreaterthan20MHzinfrequency.
3. VREFDQ(DC)isexpectedtobeapproximately0.5×VDDandtotrackvariationsintheDClevel.Externallygeneratedpeaknoise(noncommonmode)onVREFDQmaynotexceed±1%×VDDaroundtheVREFDQ(DC)value.Peak-to-peakACnoiseonVREFDQshouldnotexceed±2%ofVREFDQ(DC).
4. VREFDQ(DC)maytransitiontoVREFDQ(SR)andbacktoVREFDQ(DC)wheninSELFREFRESH,withinrestrictionsoutlinedintheSELFREFRESHsection.
5. VTTisnotapplieddirectlytothedevice.VTTisasystemsupplyforsignalterminationresistors.Minimumandmaximumvaluesaresystem-dependent.
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Form #: CSI-D-685 Document 007
Table 11: Differential Input Operating Conditions (CK, CK# and DQS, DQS#)
Parameter/Condition Symbol Min Max Units Notes
Differential input logic high – slew VIH,diff 200 NA mV 4
Differential input logic low – slew VIL,diff NA -200 mV 4
Differential input logic high VIH,diff(AC) 2 × (VIH(AC) - VREF) VDD/VDDQ mV 5
Differential input logic low VIL,diff(AC) VSS/VSSQ 2 × (VIL(AC) - VREF) mV 6
Differential input crossing voltage relative to VDD/2 for DQS, DQS#; CK, CK# VIX VREF(DC) - 150 VREF(DC) + 150 mV 4, 7
Differential input crossing voltage relative to VDD/2 for CK, CK# VIX (175) VREF(DC) - 175 VREF(DC) + 175 mV 4, 7, 8
Single-ended high level for strobesVSEH
VDDQ/2 + 175 VDDQ mV 5
Single-ended high level for CK, CK# VDD/2 + 175 VDD mV 5
Single-ended low level for strobesVSEL
VSSQ VDDQ/2 - 175 mV 6
Single-ended low level for CK, CK# VSS VDD/2 - 175 mV 6
Notes:
1. ClockisreferencedtoVDDandVSS.DatastrobeisreferencedtoVDDQandVSSQ.
2. ReferenceisVREFCA(DC)forclockandVREFDQ(DC)forstrobe.
3. Differentialinputslewrate=2V/ns
4. Definesslewratereferencepoints,relativetoinputcrossingvoltages.
5. MinimumDClimitisrelativetosingle-endedsignals;overshootspecificationsareapplicable.
6. MaximumDClimitisrelativetosingle-endedsignals;undershootspecificationsareapplicable.
7. ThetypicalvalueofVIX(AC)isexpectedtobeabout0.5×VDDofthetransmittingdevice,andVIX(AC)isexpectedtotrackvariationsinVDD.VIX(AC)indicatesthevoltageatwhichdifferentialinputsignalsmustcross.
8. TheVIXextendedrange(±175mV)isallowedonlyfortheclock;thisVIXextendedrangeisonlyallowedwhenthefollowingconditionsaremet:Thesingle-endedinputsignalsaremonotonic,havethesingle-endedswingVSEL,VSEHofatleastVDD/2±250mV,andthedifferentialslewrateofCK,CK#isgreaterthan3V/ns.
9. VIXmustprovide25mV(single-ended)ofthevoltagesseparation.
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Form #: CSI-D-685 Document 007
Figure 15: Input Signal
0.575V
0.0V
0.650V
0.720V0.735V0.750V0.765V0.780V
0.850V
0.925V
VIL(AC)
VIL(DC)
VREF - AC noiseVREF - DC error
VREF + DC errorVREF + AC noise
VIH(DC)
VIH(AC)
1.50V
1.90V
–0.40V
VDDQ
VDDQ + 0.4V narrowpulse width
VSS - 0.4V narrowpulse width
VSS
0.575V
0.650V
0.720V0.735V0.750V0.765V0.780V
0.850V
0.925V
Minimum VIL and VIH levels
VIH(DC)
VIH(AC)
VIL(AC)
VIL(DC)
VIL and VIH levels with ringback
Note: 1. Numbers in diagrams reflect nominal values.
1Gb: x4, x8, x16 DDR3 SDRAMElectrical Specifications – DC and AC
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Figure 3: Input Signal
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Form #: CSI-D-685 Document 007
AC Overshoot/Undershoot Specification
Table 12: Control and Address Pins
Parameter DDR3L-1333
Maximum peak amplitude allowed for overshoot area (see Figure 4) 0.4V
Maximum peak amplitude allowed for undershoot area (see Figure 5) 0.4V
Maximum overshoot area above VDD (see Figure 4) 0.4 Vns
Maximum undershoot area below VSS (see Figure 5) 0.4 Vns
Table 13: lock, Data, Strobe, and Mask Pins
Parameter DDR3L-1333
Maximum peak amplitude allowed for overshoot area (see Figure 4) 0.4V
Maximum peak amplitude allowed for undershoot area (see Figure 5) 0.4V
Maximum overshoot area above VDD/VDDQ (see Figure 4) 0.15 Vns
Maximum undershoot area below VSS/VSSQ (see Figure 5) 0.15 Vns
Figure 4: Overshoot
AC Overshoot/Undershoot Specification
Table 25: Control and Address Pins
Parameter DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133
Maximum peak amplitude al-lowed for overshoot area(see Figure 16)
0.4V 0.4V 0.4V 0.4V 0.4V 0.4V
Maximum peak amplitude al-lowed for undershoot area(see Figure 17)
0.4V 0.4V 0.4V 0.4V 0.4V 0.4V
Maximum overshoot area aboveVDD (see Figure 16)
0.67 Vns 0.5 Vns 0.4 Vns 0.33 Vns 0.28 Vns 0.25 Vns
Maximum undershoot area be-low VSS (see Figure 17)
0.67 Vns 0.5 Vns 0.4 Vns 0.33 Vns 0.28 Vns 0.25 Vns
Table 26: Clock, Data, Strobe, and Mask Pins
Parameter DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133
Maximum peak amplitude al-lowed for overshoot area(see Figure 16)
0.4V 0.4V 0.4V 0.4V 0.4V 0.4V
Maximum peak amplitude al-lowed for undershoot area(see Figure 17)
0.4V 0.4V 0.4V 0.4V 0.4V 0.4V
Maximum overshoot area aboveVDD/VDDQ (see Figure 16)
0.25 Vns 0.19 Vns 0.15 Vns 0.13 Vns 0.11 Vns 0.10 Vns
Maximum undershoot area be-low VSS/VSSQ (see Figure 17)
0.25 Vns 0.19 Vns 0.15 Vns 0.13 Vns 0.11 Vns 0.10 Vns
Figure 16: Overshoot
Maximum amplitudeOvershoot area
VDD/VDDQ
Time (ns)
Volts (V)
Figure 17: Undershoot
Maximum amplitude
Undershoot area
VSS/VSSQ
Time (ns)
Volts (V)
1Gb: x4, x8, x16 DDR3 SDRAMElectrical Specifications – DC and AC
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AC Overshoot/Undershoot Specification
Table 25: Control and Address Pins
Parameter DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133
Maximum peak amplitude al-lowed for overshoot area(see Figure 16)
0.4V 0.4V 0.4V 0.4V 0.4V 0.4V
Maximum peak amplitude al-lowed for undershoot area(see Figure 17)
0.4V 0.4V 0.4V 0.4V 0.4V 0.4V
Maximum overshoot area aboveVDD (see Figure 16)
0.67 Vns 0.5 Vns 0.4 Vns 0.33 Vns 0.28 Vns 0.25 Vns
Maximum undershoot area be-low VSS (see Figure 17)
0.67 Vns 0.5 Vns 0.4 Vns 0.33 Vns 0.28 Vns 0.25 Vns
Table 26: Clock, Data, Strobe, and Mask Pins
Parameter DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133
Maximum peak amplitude al-lowed for overshoot area(see Figure 16)
0.4V 0.4V 0.4V 0.4V 0.4V 0.4V
Maximum peak amplitude al-lowed for undershoot area(see Figure 17)
0.4V 0.4V 0.4V 0.4V 0.4V 0.4V
Maximum overshoot area aboveVDD/VDDQ (see Figure 16)
0.25 Vns 0.19 Vns 0.15 Vns 0.13 Vns 0.11 Vns 0.10 Vns
Maximum undershoot area be-low VSS/VSSQ (see Figure 17)
0.25 Vns 0.19 Vns 0.15 Vns 0.13 Vns 0.11 Vns 0.10 Vns
Figure 16: Overshoot
Maximum amplitudeOvershoot area
VDD/VDDQ
Time (ns)
Volts (V)
Figure 17: Undershoot
Maximum amplitude
Undershoot area
VSS/VSSQ
Time (ns)
Volts (V)
1Gb: x4, x8, x16 DDR3 SDRAMElectrical Specifications – DC and AC
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Figure 5: Undershoot
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Form #: CSI-D-685 Document 007
Figure 6: Definition of Differential AC-Swing and tDVACFigure 20: Definition of Differential AC-Swing and tDVAC
VIH,diff(AC)min
0.0
VIL,diff,max
tDVAC
VIH,diff,min
VIL,diff(AC)max
Half cycle tDVAC
CK - CK#DQS - DQS#
Table 28: Allowed Time Before Ringback (tDVAC) for CK - CK# and DQS -DQS#
Slew Rate (V/ns)
tDVAC (ps) at |VIH,diff(AC) to VIL,diff(AC)|
350mV 300mV
>4.0 75 175
4.0 57 170
3.0 50 167
2.0 38 163
1.9 34 162
1.6 29 161
1.4 22 159
1.2 13 155
1.0 0 150
<1.0 0 150
Note: 1. Below VIL(AC)
1Gb: x4, x8, x16 DDR3 SDRAMElectrical Specifications – DC and AC
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Table 14: Minimum Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC Ringback
Slew Rate (V/ns)tDVAC (ps) at |VIH,diff(AC) to VIL,diff(AC)|
320mV 300mV
>4.0 75 175
4.0 57 170
3.0 50 167
2.0 38 163
1.9 34 162
1.6 29 161
1.4 22 159
1.2 13 155
1.0 0 150
<1.0 0 150
Note:
1. BelowVIL(AC)
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ODT Characteristics
ODT CharacteristicsThe ODT effective resistance RTT is defined by MR1[9, 6, and 2]. ODT is applied to theDQ, DM, DQS, DQS#, and TDQS, TDQS# balls (x8 devices only). The ODT target valuesand a functional representation are listed in Table 31 and Table 32 (page 58). The indi-vidual pull-up and pull-down resistors (RTT(PU) and RTT(PD)) are defined as follows:
• RTT(PU) = (VDDQ - VOUT)/|IOUT|, under the condition that RTT(PD) is turned off• RTT(PD) = (VOUT)/|IOUT|, under the condition that RTT(PU) is turned off
Figure 23: ODT Levels and I-V Characteristics
RTT(PU)
RTT(PD)
ODT
Chip in termination mode
VDDQ
DQ
VSSQ
IOUT = IPD - IPU
IPU
IPD
IOUT
VOUT
Toothercircuitrysuch as RCV, . . .
Table 31: On-Die Termination DC Electrical Characteristics
Parameter/Condition Symbol Min Nom Max Unit Notes
RTT effective impedance RTT(EFF) See Table 32 (page 58) 1, 2
Deviation of VM with respect toVDDQ/2
ΔVM –5 5 % 1, 2, 3
Notes: 1. Tolerance limits are applicable after proper ZQ calibration has been performed at astable temperature and voltage (VDDQ = VDD, VSSQ = VSS). Refer to ODT Sensitivity(page 59) if either the temperature or voltage changes after calibration.
2. Measurement definition for RTT: Apply VIH(AC) to pin under test and measure currentI[VIH(AC)], then apply VIL(AC) to pin under test and measure current I[VIL(AC)]:
RTT = VIH(AC) - VIL(AC)
I(VIH(AC)) - I(VIL(AC))
3. Measure voltage (VM) at the tested pin with no load:
VM = – 12 × VMVDDQ
× 100
4. For IT and AT devices, the minimum values are derated by 6% when the device operatesbetween –40°C and 0°C (TC).
1Gb: x4, x8, x16 DDR3 SDRAMODT Characteristics
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Table 15: On-Die Termination DC Electrical Characteristics
Parameter/Condition Symbol Min Nom Max Unit Notes
RTT effective impedance RTT(EFF) See Table 16 (page 18) 1, 2
Deviation of VM with respect to VDDQ/2 ΔVM -5 - 5 % 1, 2, 3
3. Measurevoltage(VM)atthetestedpinwithnoload:
Figure 7: ODT Levels and I-V Characteristics
RTT=VIH(AC)-VIL(AC)
I(VIH(AC))-I(VIL(AC))
ΔVM= x100-1)(2xVMVDDQ
4. ForITdevices,theminimumvaluesarederatedby6%whenthedeviceoperatesbetween-40°Cand0°C(TC).
TheODTeffectiveresistanceRTTisdefinedbyMR1[9,6,and2].ODT isapplied to theDQ,DM,DQS,DQS#,andTDQS,TDQS#balls (x8devicesonly).TheODTtargetvaluesandafunctional representationare listed inTable15andTable16(page 18). The individual pull-up and pull-down resistors(RTT(PU)andRTT(PD))aredefinedasfollows:
• RTT(PU)=(VDDQ-VOUT)/|IOUT|,undertheconditionthatRTT(PD)isturnedoff
• RTT(PD)=(VOUT)/|IOUT|,undertheconditionthatRTT(PU)isturnedoff
Notes:
1. TolerancelimitsareapplicableafterproperZQcalibrationhasbeenperformedatastabletemperatureandvoltage(VDDQ=VDD,VSSQ=VSS).
2. MeasurementdefinitionforRTT:ApplyVIH(AC)topinundertestandmeasurecurrentI[VIH(AC)],thenapplyVIL(AC)topinundertestandmeasurecurrentI[VIL(AC)]:
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Form #: CSI-D-685 Document 007
1.35V ODT Resistors
Table 16 provides an overview of the ODT DC electricalcharacteristics. The values provided are not specificationrequirements;however,theycanbeusedasdesignguidelinestoindicatewhatRTTistargetedtoprovide:
• RTT120ΩismadeupofRTT120(PD240)andRTT120(PU240)
• RTT60ΩismadeupofRTT60(PD120)andRTT60(PU120)
• RTT40ΩismadeupofRTT40(PD80)andRTT40(PU80)
• RTT30ΩismadeupofRTT30(PD60)andRTT30(PU60)
• RTT20ΩismadeupofRTT20(PD40)andRTT20(PU40)
Table 16: RTT Effective Impedance
MR1 [9, 6, 2] RTT Resistor VOUT Min Nom Max Units
0, 1, 0120Ω
RTT120(PD240)
0.2 × VDDQ 0.6 1.0 1.1 RZQ/1
0.5 × VDDQ 0.9 1.0 1.1 RZQ/1
0.8 × VDDQ 0.9 1.0 1.4 RZQ/1
RTT120(PU240)
0.2 × VDDQ 0.9 1.0 1.4 RZQ/1
0.5 × VDDQ 0.9 1.0 1.1 RZQ/1
0.8 × VDDQ 0.6 1.0 1.1 RZQ/1
120Ω VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/2
0, 0, 160Ω
RTT60(PD120)
0.2 × VDDQ 0.6 1.0 1.1 RZQ/2
0.5 × VDDQ 0.9 1.0 1.1 RZQ/2
0.8 × VDDQ 0.9 1.0 1.4 RZQ/2
RTT60(PU120)
0.2 × VDDQ 0.9 1.0 1.4 RZQ/2
0.5 × VDDQ 0.9 1.0 1.1 RZQ/2
0.8 × VDDQ 0.6 1.0 1.1 RZQ/2
60Ω VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/4
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MR1 [9, 6, 2] RTT Resistor VOUT Min Nom Max Units
0, 1, 140Ω
RTT40(PD80)
0.2 × VDDQ 0.6 1.0 1.1 RZQ/3
0.5 × VDDQ 0.9 1.0 1.1 RZQ/3
0.8 × VDDQ 0.9 1.0 1.4 RZQ/3
RTT40(PU80)
0.2 × VDDQ 0.9 1.0 1.4 RZQ/3
0.5 × VDDQ 0.9 1.0 1.1 RZQ/3
0.8 × VDDQ 0.6 1.0 1.1 RZQ/3
40Ω VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/6
1, 0, 130Ω
RTT30(PD60)
0.2 × VDDQ 0.6 1.0 1.1 RZQ/4
0.5 × VDDQ 0.9 1.0 1.1 RZQ/4
0.8 × VDDQ 0.9 1.0 1.4 RZQ/4
RTT30(PU60)
0.2 × VDDQ 0.9 1.0 1.4 RZQ/4
0.5 × VDDQ 0.9 1.0 1.1 RZQ/4
0.8 × VDDQ 0.6 1.0 1.1 RZQ/4
30Ω VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/8
1, 0, 020Ω
RTT20(PD40)
0.2 × VDDQ 0.6 1.0 1.1 RZQ/6
0.5 × VDDQ 0.9 1.0 1.1 RZQ/6
0.8 × VDDQ 0.9 1.0 1.4 RZQ/6
RTT20(PU40)
0.2 × VDDQ 0.9 1.0 1.4 RZQ/6
0.5 × VDDQ 0.9 1.0 1.1 RZQ/6
0.8 × VDDQ 0.6 1.0 1.1 RZQ/6
20Ω VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/12
Table 16: RTT Effective Impedance (continued)
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Form #: CSI-D-685 Document 007
Output Driver ImpedanceTheoutputdriver impedance isselectedbyMR1[5,1]duringinitialization. The selected value is able tomaintain the tighttolerances specified if proper ZQ calibration is performed.Outputspecificationsrefertothedefaultoutputdriverunlessspecificallystatedotherwise.Afunctionalrepresentationoftheoutput buffer is shown below. The output driver impedanceRONisdefinedbythevalueoftheexternalreferenceresistorRZQasfollows:
• RON,x=RZQ/y(withRZQ=240Ω±1%;x=34Ωor40Ωwithy=7or6,respectively)
The individual pull-up and pull-down resistors RON(PU) andRON(PD)aredefinedasfollows:
• RON(PU)=(VDDQ-VOUT)/|IOUT|,whenRON(PD)isturnedoff
• RON(PD)=(VOUT)/|IOUT|,whenRON(PU)isturnedoff
Figure 8: Output Driver
Output Driver ImpedanceThe output driver impedance is selected by MR1[5,1] during initialization. The selectedvalue is able to maintain the tight tolerances specified if proper ZQ calibration is per-formed. Output specifications refer to the default output driver unless specifically sta-ted otherwise. A functional representation of the output buffer is shown below. The out-put driver impedance RON is defined by the value of the external reference resistor RZQas follows:
• RON,x = RZQ/y (with RZQ = 240Ω x Ω or 40Ω with y = 7 or 6, respectively)
The individual pull-up and pull-down resistors RON(PU) and RON(PD) are defined as fol-lows:
• RON(PU) = (VDDQ - VOUT)/|IOUT|, when RON(PD) is turned off• RON(PD) = (VOUT)/|IOUT|, when RON(PU) is turned off
Figure 28: Output Driver
RON(PU)
RON(PD)
Output driver
Toothercircuitrysuch asRCV, . . .
Chip in drive mode
VDDQ
VSSQ
IPU
IPD
IOUT
VOUT
DQ
1Gb: x4, x8, x16 DDR3 SDRAMOutput Driver Impedance
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Form #: CSI-D-685 Document 007
MMPUPD= x100RON(PU)-RON(PD)
RON,nom
34 Ohm Output Driver Impedance
The34Ωdriver (MR1[5,1]=01) is thedefaultdriver.Unlessotherwise stated, all timings and specifications listed hereinapply to the 34Ω driver only. Its impedance RON is definedbythevalueoftheexternalreferenceresistorRZQasfollows:RON34 = RZQ/7 (with nominal RZQ = 240Ω ±1%) and isactually34.3Ω±1%
Table 17: 34 Ohm Driver Impedance Characteristics
MR1 [5, 1] RTT Resistor VOUT Min Nom Max Units Notes
0, 1 34.3Ω
RON,34PD
0.2 × VDDQ 0.6 1.0 1.1 RZQ/7
0.5 × VDDQ 0.9 1.0 1.1 RZQ/7
0.8 × VDDQ 0.9 1.0 1.4 RZQ/7
RON,34PU
0.2 × VDDQ 0.9 1.0 1.4 RZQ/7
0.5 × VDDQ 0.9 1.0 1.1 RZQ/7
0.8 × VDDQ 0.6 1.0 1.1 RZQ/7
Pull-up/pull-down mismatch (MMPUPD) 0.5 × VDDQ -10 NA 10 % 2
Notes:
1. TolerancelimitsassumeRZQof240Ω±1%andareapplicableafterproperZQcalibrationhasbeenperformedatastabletemperatureandvoltage:VDDQ=VDD;VSSQ=VSS).
2. Measurementdefinitionformismatchbetweenpull-upandpull-down(MMPUPD).MeasurebothRON(PU)andRON(PD)at0.5×VDDQ:
3. ForITdevices,theminimumvaluesarederatedby6%whenthedeviceoperatesbetween–40°Cand0°C(TC).Alargermaximumlimitwillresultinslightlylowerminimumcurrents.
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Table 18: DDR3-1333 Speed Bins
DDR3L-1333 Speed Bin -151
Units NotesCL-tRCD-tRP 9-9-9
Parameter Symbol Min Max
Internal READ command to first data tAA 13.5 – ns
ACTIVATE to internal READ or WRITE delay time tRCD 13.5 – ns
PRECHARGE command period tRP 13.5 – ns
ACTIVATE-to-ACTIVATE or REFRESH command period tRC 49.5 – ns
ACTIVATE-to-PRECHARGE command period tRAS 36 9 x tREFI ns 2
CL = 5CWL = 5 tCK (AVG) 3.0 3.3 ns 3
CWL = 6, 7 tCK (AVG) Reserved ns 4
CL = 6
CWL = 5 tCK (AVG) 2.5 3.3 ns 3
CWL = 6 tCK (AVG) Reserved ns 4
CWL = 7 tCK (AVG) Reserved ns 4
CL = 7
CWL = 5 tCK (AVG) Reserved ns 4
CWL = 6 tCK (AVG) 1.875 <2.5 ns 3, 4
CWL = 7 tCK (AVG) Reserved ns 4
CL = 8
CWL = 5 tCK (AVG) Reserved ns 4
CWL = 6 tCK (AVG) 1.875 <2.5 ns 3
CWL = 7 tCK (AVG) Reserved ns 4
CL = 9CWL = 5, 6 tCK (AVG) Reserved ns 4
CWL = 7 tCK (AVG) 1.5 <1.875 ns 3, 4
CL = 10CWL = 5, 6 tCK (AVG) Reserved ns 4
CWL = 7 tCK (AVG) 1.5 <1.875 ns 3
Supported CL settings 5, 6, 7, 8, 9, 10 CK
Supported CWL settings 5, 6, 7 CK
Notes:
1. The-15speedgradeisbackwardcompatiblewith1066,CL=7.
2. tREFIdependsonTOPER.
3. TheCLandCWLsettingsresultintCKrequirements.WhenmakingaselectionoftCK,bothCLandCWLrequirementsettingsneedtobefulfilled.
4. Reservedsettingsarenotallowed.
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Electrical Characteristics and AC Operating Conditions
Table 19: Electrical Characteristics and AC Operating Conditions
Notes1-8applytotheentiretable.
Parameter SymbolDDR3L-1333
Units NotesMin Max
Clock Timing
Clock period average: DLL disable mode
TC ≤ 85°CtCK (DLL_DIS)
8 7800 ns 9, 42
TC = >85°C to 95°C 8 3900 ns 42
Clock period average: DLL enable mode tCK (AVG) See Speed Bin Tables for tCK range allowed ns 10, 11
High pulse width average tCH (AVG) 0.47 0.53 CK 12
Low pulse width average tCL (AVG) 0.47 0.53 CK 12
Clock period jitterDLL locked tJITper –80 80 ps 13
DLL locking tJITper,lck –70 70 ps 13
Clock absolute period tCK (ABS)MIN = tCK (AVG) MIN + tJITper MIN
MAX = tCK (AVG) MAX + tJITper MAXps –
Clock absolute high pulse width tCH (ABS) 0.43 – tCK (AVG) 14
Clock absolute low pulse width tCL (ABS) 0.43 – tCK (AVG) 15
Cycle-to-cycle jitterDLL locked tJITcc 160 ps 16
DLL locking tJITcc,lck 140 ps 16
Cumulative error across
2 cycles tERR2per –118 118 ps 17
3 cycles tERR3per –140 140 ps 17
4 cycles tERR4per –155 155 ps 17
5 cycles tERR5per –168 168 ps 17
6 cycles tERR6per –177 177 ps 17
7 cycles tERR7per –186 186 ps 17
8 cycles tERR8per –193 193 ps 17
9 cycles tERR9per –200 200 ps 17
10 cycles tERR10per –205 205 ps 17
11 cycles tERR11per –210 210 ps 17
12 cycles tERR12per –215 215 ps 17
n = 13, 14 . . . 49, 50 cycles tERRnpertERRnper MIN = (1 + 0.68ln[n]) × tJITper MIN
tERRnper MAX = (1 + 0.68ln[n]) × tJITper MAXps 17
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Parameter SymbolDDR3L-1333
Units NotesMin Max
DQ Input Timing
Data setup time to DQS, DQS#
Base (specification)tDS (AC175)
– – ps 18, 19, 44
VREF @ 1 V/ns – – ps 19, 20
Data setup time to DQS, DQS#
Base (specification)tDS (AC150)
30 – ps 18, 19, 44
VREF @ 1 V/ns 180 – ps 19, 20
Data setup time to DQS, DQS#
Base (specification)tDS (AC135)
– – ps 18, 19
VREF @ 1 V/ns – – ps 19, 20
Data hold time from DQS, DQS#
Base (specification)tDH (DC100)
65 – ps 18, 19
VREF @ 1 V/ns 165 – ps 19, 20
Minimum data pulse width tDIPW 400 – ps 41
DQ Output Timing
DQS, DQS# to DQ skew, per access tDQSQ – 125 ps –
DQ output hold time from DQS, DQS# tQH 0.38 – tCK (AVG) 21
DQ Low-Z time from CK, CK# tLZDQ –500 250 ps 22, 23
DQ High-Z time from CK, CK# tHZDQ – 250 ps 22, 23
DQ Strobe Input Timing
DQS, DQS# rising to CK, CK# rising tDQSS –0.25 0.25 CK 25
DQS, DQS# differential input low pulse width tDQSL 0.45 0.55 CK –
DQS, DQS# differential input high pulse width tDQSH 0.45 0.55 CK –
DQS, DQS# falling setup to CK, CK# rising tDSS 0.2 – CK 25
DQS, DQS# falling hold from CK, CK# rising tDSH 0.2 – CK 25
DQS, DQS# differential WRITE preamble tWPRE 0.9 – CK –
DQS, DQS# differential WRITE postamble tWPST 0.3 – CK –
DQ Strobe Output Timing
DQS, DQS# rising to/from rising CK, CK# tDQSCK –255 255 ps 23
DQS, DQS# rising to/from rising CK, CK# when DLL is disabled
tDQSCK (DLL_DIS) 1 10 ns 26
DQS, DQS# differential output high time tQSH 0.40 – CK 21
DQS, DQS# differential output low time tQSL 0.40 – CK 21
DQS, DQS# Low-Z time (RL - 1) tLZDQS –500 250 ps 22, 23
DQS, DQS# High-Z time (RL + BL/2) tHZDQS – 250 ps 22, 23
DQS, DQS# differential READ preamble tRPRE 0.9 Note 24 CK 23, 24
DQS, DQS# differential READ postamble tRPST 0.3 Note 27 CK 23, 27
Table 19: Electrical Characteristics and AC Operating Conditions (continued)
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Parameter SymbolDDR3L-1333
Units NotesMin Max
Command and Address Timing
DLL locking time tDLLK 512 – CK 28
CTRL, CMD, ADDR setup to CK,CK#
Base (specification)tIS (AC175)
65 – ps 29, 30, 44
VREF @ 1 V/ns 240 – ps 20, 30
CTRL, CMD, ADDR setup to CK,CK#
Base (specification)tIS (AC150)
190 – ps 29, 30, 44
VREF @ 1 V/ns 340 – ps 20, 30
CTRL, CMD, ADDR hold from CK,CK#
Base (specification)tIH (DC100)
140 – ps 29, 30
VREF @ 1 V/ns 240 – ps 20, 30
Minimum CTRL, CMD, ADDR pulse width tIPW 620 – ps 41
ACTIVATE to internal READ or WRITE delay tRCD See Speed Bin Tables for tRCD ns 31
PRECHARGE command period tRP See Speed Bin Tables for tRP ns 31
ACTIVATE-to-PRECHARGE command period tRAS See Speed Bin Tables for tRAS ns 31, 32
ACTIVATE-to-ACTIVATE command period tRC See Speed Bin Tables for tRC ns 31, 43
ACTIVATE-to-ACTIVATE minimum command period
x4/x8 (1KB page size)tRRD
MIN = greater of 4CK or 6ns CK 31
x16 (2KB page size) MIN = greater of 4CK or 7.5ns CK 31
Four ACTIVATE windowsx4/x8 (1KB page size)
tFAW30 – ns 31
x16 (2KB page size) 45 – ns 31
Write recovery time tWR MIN = 15ns; MAX = n/a ns 31, 32, 33, 34
Delay from start of internal WRITE transaction to internal READ command
tWTR MIN = greater of 4CK or 7.5ns; MAX = n/a CK 31, 34
READ-to-PRECHARGE time tRTP MIN = greater of 4CK or 7.5ns; MAX = n/a CK 31, 32
CAS#-to-CAS# command delay tCCD MIN = 4CK; MAX = n/a CK –
Auto precharge write recovery + precharge time tDAL MIN = WR + tRP/tCK (AVG); MAX = n/a CK –
MODE REGISTER SET command cycle time tMRD MIN = 4CK; MAX = n/a CK –
MODE REGISTER SET command update delay tMOD MIN = greater of 12CK or 15ns; MAX = n/a CK –
MULTIPURPOSE REGISTER READ burst end to mode register set for multipurpose register exit
tMPRR MIN = 1CK; MAX = n/a CK –
Calibration Timing
ZQCL command: Long calibration time
POWER-UP and RESET operation
tZQinit 512 – CK –
Normal operation tZQoper 256 – CK –
ZQCS command: Short calibration time tZQCS 64 – CK –
Table 19: Electrical Characteristics and AC Operating Conditions (continued)
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Parameter SymbolDDR3L-1333
Units NotesMin Max
Initialization and Reset Timing
Exit reset from CKE HIGH to a valid command tXPR MIN = greater of 5CK or tRFC + 10ns; MAX = n/a CK –
Begin power supply ramp to power supplies stable tVDDPR MIN = n/a; MAX = 200 ms –
RESET# LOW to power supplies stable tRPS MIN = 0; MAX = 200 ms –
RESET# LOW to I/O and RTT High-Z tIOZ MIN = n/a; MAX = 20 ns 35
Refresh Timing
REFRESH-to-ACTIVATE or REFRESH command period
tRFC – 1Gb MIN = 110; MAX = 70,200 ns –
tRFC – 2Gb MIN = 160; MAX = 70,200 ns –
tRFC – 4Gb MIN = 260; MAX = 70,200 ns –
tRFC – 8Gb MIN = 350; MAX = 70,200 ns –
Maximum refresh periodTC ≤ 85°C – 64 (1X) ms 36
TC > 85°C – 32 (2X) ms 36
Maximum average periodic refresh
TC ≤ 85°C tREFI 7.8 (64ms/8192) μs 36
TC > 85°C – 3.9 (32ms/8192) μs 36
Self Refresh Timing
Exit self refresh to commands not requiring a locked DLL tXS MIN = greater of 5CK or tRFC + 10ns; MAX = n/a CK –
Exit self refresh to commands requiring a locked DLL tXSDLL MIN = tDLLK (MIN); MAX = n/a CK 28
Minimum CKE low pulse width for self refresh entry to self refresh exit timing
tCKESR MIN = tCKE (MIN) + CK; MAX = n/a CK –
Valid clocks after self refresh entry or power down entry
tCKSRE MIN = greater of 5CK or 10ns; MAX = n/a CK –
Valid clocks before self refresh exit, power-down exit, or reset exit
tCKSRX MIN = greater of 5CK or 10ns; MAX = n/a CK –
Power-Down Timing
CKE MIN pulse width tCKE (MIN) Greater of 3CK or 5.625ns CK –
Command pass disable delay tCPDED MIN = 1; MAX = n/a CK –
Power-down entry to power-down exit timing tPD MIN = tCKE (MIN); MAX = 9 * tREFI CK –
Begin power-down period prior to CKE registered HIGH tANPD WL - 1CK CK –
Power-down entry period: ODT either synchronous or asynchronous PDE
Greater of tANPD or tRFC - REFRESH command to CKE LOW time
CK –
Power-down exit period: ODT either synchronous or asynchronous PDX tANPD + tXPDLL CK –
Table 19: Electrical Characteristics and AC Operating Conditions (continued)
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Parameter SymbolDDR3L-1333
Units NotesMin Max
Power-Down Entry Minimum Timing
ACTIVATE command to power-down entry tACTPDEN MIN = 1 CK
PRECHARGE/PRECHARGE ALL command to power-down entry
tPRPDEN MIN = 1 CK
REFRESH command to power-down entry tREFPDEN MIN = 1 CK 37
MRS command to power-down entry tMRSPDEN MIN = tMOD (MIN) CK
READ/READ with auto precharge command to power-down entry
tRDPDEN MIN = RL + 4 + 1 CK
WRITE command to power-down entry
BL8 (OTF, MRS) BC4OTF tWRPDEN MIN = WL + 4 + tWR/tCK (AVG) CK
BC4MRS tWRPDEN MIN = WL + 2 + tWR/tCK (AVG) CK
WRITE with auto recharge command to power-down entry
BL8 (OTF, MRS) BC4OTF tWRAP- DEN MIN = WL + 4 + WR + 1 CK
BC4MRS tWRAP- DEN MIN = WL + 2 + WR + 1 CK
Power-Down Exit Timing
DLL on, any valid command, or DLL off to commands not requiring locked DLL
tXP MIN = greater of 3CK or 6ns; MAX = n/a CK
Precharge power-down with DLL off to commands requiring a locked DLL
tXPDLL MIN = greater of 10CK or 24ns; MAX = n/a CK 28
ODT Timing
RTT synchronous turn-on delay ODTLon CWL + AL - 2CK CK 38
RTT synchronous turn-off delay ODTLoff CWL + AL - 2CK CK 40
RTT turn-on from ODTL on reference tAON –250 250 ps 23, 38
RTT turn-off from ODTL off reference tAOF 0.3 0.7 CK 39, 40
Asynchronous RTT turn-on delay (power-down with DLL off)
tAONPD MIN = 2; MAX = 8.5 ns 38
Asynchronous RTT turn-off delay (power-down with DLL off)
tAOFPD MIN = 2; MAX = 8.5 ns 40
ODT HIGH time with WRITE command and BL8 ODTH8 MIN = 6; MAX = n/a CK
ODT HIGH time without WRITE command or with WRITE command and BC4
ODTH4 MIN = 4; MAX = n/a CK
Dynamic ODT Timing
RTT,nom-to-RTT(WR) change skew ODTLcnw WL - 2CK CK
RTT(WR)-to-RTT,nom change skew - BC4 ODTLcwn4 4CK + ODTLoff CK
RTT(WR)-to-RTT,nom change skew - BL8 ODTLcwn8 6CK + ODTLoff CK
RTT dynamic change skew tADC 0.3 0.7 CK 39
Table 19: Electrical Characteristics and AC Operating Conditions (continued)
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Parameter SymbolDDR3L-1333
Units NotesMin Max
Write Leveling Timing
First DQS, DQS# rising edge tWLMRD 40 – CK
DQS, DQS# delay tWLDQSEN 25 – CK
Write leveling setup from rising CK, CK# crossing to rising DQS, DQS# crossing
tWLS 195 – ps
Write leveling hold from rising DQS, DQS# crossing to rising CK, CK# crossing
tWLH 195 – ps
Write leveling output delay tWLO 0 9 ns
Write leveling output error tWLOE 0 2 ns
Table 19: Electrical Characteristics and AC Operating Conditions (continued)
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Table 19: Electrical Characteristics and AC Operating Conditions (continued)
Notes:
1. ACtimingparametersarevalidfromspecifiedTCMINtoTCMAXvalues.
2. AllvoltagesarereferencedtoVSS.
3. OutputtimingsareonlyvalidforRON34outputbufferselection.
4. TheunittCK(AVG)representstheactualtCK(AVG)oftheinputclockunderoperation.TheunitCKrepresentsoneclockcycleoftheinputclock,countingtheactualclockedges.
5. ACtimingandIDDtestsmayuseaVIL-to-VIHswingofupto900mVinthetestenvironment,butinputtimingisstillreferencedtoVREF(excepttIS,tIH,tDS,andtDHusetheAC/DCtrippointsandCK,CK#andDQS,DQS#usetheircrossingpoints).Theminimumslewratefortheinputsignalsusedtotestthedeviceis1V/nsforsingle-endedinputs(DQsareat2V/nsforDDR3-1866andDDR3-2133)and2V/nsfordifferentialinputsintherangebetweenVIL(AC)andVIH(AC).
6. Alltimingsthatusetime-basedvalues(ns,μs,ms)shouldusetCK(AVG)todeterminethecorrectnumberofclocksusesCKortCK[AVG]interchangeably).Inthecaseofnonintegerresults,allminimumlimitsaretoberoundeduptothenearestwholeinteger,andallmaximumlimitsaretoberoundeddowntothenearestwholeinteger.
7. StrobeorDQSdiffreferstotheDQSandDQS#differentialcrossingpointwhenDQSistherisingedge.ClockorCKreferstotheCKandCK#differentialcrossingpointwhenCKistherisingedge.
8. ThisoutputloadisusedforallACtiming(exceptODTreferencetiming)andslewrates.Theactualtestloadmaybedifferent.TheoutputsignalvoltagereferencepointisVDDQ/2forsingle-endedsignalsandthecrossingpointfordifferentialsignals.
9. WhenoperatinginDLLdisablemode,Microndoesnotwarrantcompliancewithnormalmodetimingsorfunctionality.
10. Theclock’stCK(AVG)istheaverageclockoverany200consecutiveclocksandtCK(AVG)MINisthesmallestclockrateallowed,withtheexceptionofadeviationduetoclockjitter.InputclockjitterisallowedprovideditdoesnotexceedvaluesspecifiedandmustbeofarandomGaussiandistributioninnature.
11. Spreadspectrumisnotincludedinthejitterspecificationvalues.However,theinputclockcanaccommodatespread-spectrumatasweeprateintherangeof20–60kHzwithanadditional1%oftCK(AVG)asalong-termjittercomponent;however,thespreadspectrummaynotuseaclockratebelowtCK(AVG)MIN.
12. Theclock’stCH(AVG)andtCL(AVG)aretheaveragehalfclockperiodoverany200consecutiveclocksandisthesmallestclockhalfperiodallowed,withtheexceptionofadeviationduetoclockjitter.InputclockjitterisallowedprovideditdoesnotexceedvaluesspecifiedandmustbeofarandomGaussiandistributioninnature.
13. Theperiodjitter(tJITper)isthemaximumdeviationintheclockperiodfromtheaverageornominalclock.Itisallowedineitherthepositiveornegativedirection.
14. tCH(ABS)istheabsoluteinstantaneousclockhighpulsewidthasmeasuredfromonerisingedgetothefollowingfallingedge.
15. tCL(ABS)istheabsoluteinstantaneousclocklowpulsewidthasmeasuredfromonefallingedgetothefollowingrisingedge.
16. Thecycle-to-cyclejittertJITccistheamounttheclockperiodcandeviatefromonecycletothenext.Itisimportanttokeepcycle-to-cyclejitterataminimumduringtheDLLlockingtime.
17. ThecumulativejittererrortERRnper,wherenisthenumberofclocksbetween2and50,istheamountofclocktimeallowedtoaccumulateconsecutivelyawayfromtheaverageclockovernnumberofclockcycles.
18. tDS(base)andtDH(base)valuesareforasingle-ended1V/nsslewrateDQs(DQsareat2V/nsforDDR3-1866andDDR3-2133)and2V/nsslewratedifferentialDQS,DQS#.
19. Theseparametersaremeasuredfromadatasignal(DM,DQ0,DQ1,andsoforth)transitionedgetoitsrespectivedatastrobesignal(DQS,DQS#)crossing.
20. Thesetupandholdtimesarelistedconvertingthebasespecificationvalues(towhichderatingtablesapply)toVREFwhentheslewrateis1V/ns(DQsareat2V/nsforDDR3-1866andDDR3-2133).Thesevalues,withaslewrateof1V/ns(DQsareat2V/nsforDDR3-1866andDDR3-2133),areforreferenceonly.
21. Whenthedeviceisoperatedwithinputclockjitter,thisparameterneedstobederatedbytheactualtJITper(largeroftJITper(MIN)ortJITper(MAX)oftheinputclock(outputderatingsarerelativetotheSDRAMinputclock).
22. Single-endedsignalparameter.
23. TheDRAMoutputtimingisalignedtothenominaloraverageclock.Mostoutputparametersmustbederatedbytheactualjittererrorwheninputclockjitterispresent,evenwhenwithinspecification.Thisresultsineachparameterbecominglarger.ThefollowingparametersarerequiredtobederatedbysubtractingtERR10per(MAX):tDQSCK(MIN),tLZDQS(MIN),tLZDQ(MIN),andtAON(MIN).Thefollowingparameters
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arerequiredtobederatedbysubtractingtERR10per(MIN):tDQSCK(MAX),tHZ(MAX),tLZDQS(MAX),tLZDQ(MAX),andtAON(MAX).TheparametertRPRE(MIN)isderatedbysubtractingtJITper(MAX),whiletRPRE(MAX)isderatedbysubtractingtJITper(MIN).
24. ThemaximumpreambleisboundbytLZDQS(MAX).
25. Theseparametersaremeasuredfromadatastrobesignal(DQS,DQS#)crossingtoitsrespectiveclocksignal(CK,CK#)crossing.Thespecificationvaluesarenotaffectedbytheamountofclockjitterapplied,asthesearerelativetotheclocksignalcrossing.Theseparametersshouldbemetwhetherclockjitterispresent.
26. ThetDQSCK(DLL_DIS)parameterbeginsCL+AL-1cyclesaftertheREADcommand.
27. ThemaximumpostambleisboundbytHZDQS(MAX).
28. CommandsrequiringalockedDLLare:READ(andRDAP)andsynchronousODTcommands.Inaddition,afteranychangeoflatencytXPDLL,timingmustbemet.
29. tIS(base)andtIH(base)valuesareforasingle-ended1V/nscontrol/command/addressslewrateand2V/nsCK,CK#differentialslewrate.
30. Theseparametersaremeasuredfromacommand/addresssignaltransitionedgetoitsrespectiveclock(CK,CK#)signalcrossing.Thespecificationvaluesarenotaffectedbytheamountofclockjitterappliedasthesetupandholdtimesarerelativetotheclocksignalcrossingthatlatchesthecommand/address.Theseparametersshouldbemetwhetherclockjitterispresent.
31. Fortheseparameters,theDDR3SDRAMdevicesupportstnPARAM(nCK)=RU(tPARAM[ns]/tCK[AVG][ns]),assumingallinputclockjitterspecificationsaresatisfied.Forexample,thedevicewillsupporttnRP(nCK)=RU(tRP/tCK[AVG])ifallinputclockjitterspecificationsaremet.ThismeansthatforDDR3-8006-6-6,ofwhichtRP=5ns,thedevicewillsupporttnRP=RU(tRP/tCK[AVG])=6aslongastheinputclockjitterspecificationsaremet.Thatis,thePRECHARGEcommandatT0andtheACTIVATEcommandatT0+6arevalidevenifsixclocksarelessthan15nsduetoinputclockjitter.
32. DuringREADsandWRITEswithautoprecharge,theDDR3SDRAMwillholdofftheinternalPRECHARGEcommanduntiltRAS(MIN)hasbeensatisfied.
33. WhenoperatinginDLLdisablemode,thegreaterof4CKor15nsissatisfiedfortWR.
34. Thestartofthewriterecoverytimeisdefinedasfollows:
� ForBL8(fixedbyMRSorOTF):RisingclockedgefourclockcyclesafterWL
� ForBC4(OTF):RisingclockedgefourclockcyclesafterWL
� ForBC4(fixedbyMRS):RisingclockedgetwoclockcyclesafterWL
35. RESET#shouldbeLOWassoonaspowerstartstoramptoensuretheoutputsareinHigh-Z.UntilRESET#isLOW,theoutputsareatriskofdrivingandcouldresultinexcessivecurrent,dependingonbusactivity.
36. Therefreshperiodis64mswhenTCislessthanorequalto85°C.Thisequatestoanaveragerefreshrateof7.8125μs.However,nineREFRESHcommandsshouldbeassertedatleastonceevery70.3μs.WhenTCisgreaterthan85°C,therefreshperiodis32ms.
37. AlthoughCKEisallowedtoberegisteredLOWafteraREFRESHcommandwhentREFPDEN(MIN)issatisfied,therearecaseswhereadditionaltimesuchastXPDLL(MIN)isrequired.
38. ODTturn-ontimeMINiswhenthedeviceleavesHigh-ZandODTresistancebeginstoturnon.ODTturn-ontimemaximumiswhentheODTresistanceisfullyon.TheODTreferenceloadisshowninFigure7(page17).DesignsthatwerecreatedpriortoJEDECtighteningthemaximumlimitfrom9nsto8.5nswillbeallowedtohavea9nsmaximum.
39. Half-clockoutputparametersmustbederatedbytheactualtERR10perandtJITdtywheninputclockjitterispresent.Thisresultsineachparameterbecominglarger.TheparameterstADC(MIN)andtAOF(MIN)areeachrequiredtobederatedbysubtractingbothtERR10per(MAX)andtJITdty(MAX).TheparameterstADC(MAX)andtAOF(MAX)arerequiredtobederatedbysubtractingbothtERR10per(MAX)andtJITdty(MAX).
40. ODTturn-offtimeminimumiswhenthedevicestartstoturnoffODTresistance.ODTturn-offtimemaximumiswhentheDRAMbufferisinHigh-Z.TheODTreferenceloadisshownin.ThisoutputloadisusedforODTtimings
41. PulsewidthofainputsignalisdefinedasthewidthbetweenthefirstcrossingofVREF(DC)andtheconsecutivecrossingofVREF(DC).
Table 19: Electrical Characteristics and AC Operating Conditions (continued)
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42. ShouldtheclockratebelargerthantRFC(MIN),anAUTOREFRESHcommandshouldhaveatleastoneNOPcommandbetweenitandanotherAUTOREFRESHcommand.Additionally,iftheclockrateisslowerthan40ns(25MHz),allREFRESHcommandsshouldbefollowedbyaPRECHARGEALLcommand.
43. DRAMdevicesshouldbeevenlyaddressedwhenbeingaccessed.DisproportionateaccessestoaparticularrowaddressmayresultinareductionofREFRESHcharacteristicsorproductlifetime.
44. WhentwoVIH(AC)values(andtwocorrespondingVIL(AC)values)arelistedforaspecificspeedbin,theusermaychooseeithervaluefortheinputAClevel.Whichevervalueisused,theassociatedsetuptimeforthatAClevelmustalsobeused.Additionally,oneVIH(AC)valuemaybeusedforaddress/commandinputsandtheotherVIH(AC)valuemaybeusedfordatainputs.Forexample,forDDR3-800,twoinputAClevelsaredefined:VIH(AC175),minandVIH(AC150),min(correspondingVIL(AC175),minandVIL(AC150),min).ForDDR3-800,theaddress/commandinputsmustuseeitherVIH(AC175),minwithtIS(AC175)of200psorVIH(AC150),minwithtIS(AC150)of350ps;independently,thedatainputsmustuseeitherVIH(AC175),minwithtDS(AC175)of75psorVIH(AC150),minwithtDS(AC150)of125ps.
Table 19: Electrical Characteristics and AC Operating Conditions (continued)
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Commands - Truth Tables
Table 20: Truth Table - Command
Notes1-5applytotheentiretable.
Functions Symbol
CKE
CS# RAS# CAS# WE#BA
[2:0]An A12 A10
A[11, 9:0]
NotesPrev. Cycle
Next Cycle
MODE REGISTER SET MRS H H L L L L BA OP code
REFRESH REF H H L L L H V V V V V
Self refresh entry SRE H L L L L H V V V V V 6
Self refresh exit SRX L HH V V V
V V V V V 6, 7L H H H
Single-bank PRECHARGE PRE H H L L H L BAV
V L V
PRECHARGE all banks PREA H H L L H L V V H V
Bank ACTIVATE ACT H H L L H H BA Row address (RA)
WRITE
BL8MRS, BC4MRS WR H H L H L L BA RFU V L CA 8
BC4OTF WRS4 H H L H L L BA RFU L L CA 8
BL8OTF WRS8 H H L H L L BA RFU H L CA 8
WRITE with auto precharge
BL8MRS, BC4MRS WRAP H H L H L L BA RFU V H CA 8
BC4OTF WRAPS4 H H L H L L BA RFU L H CA 8
BL8OTF WRAPS8 H H L H L L BA RFU H H CA 8
READ
BL8MRS, BC4MRS RD H H L H L H BA RFU V L CA 8
BC4OTF RDS4 H H L H L H BA RFU L L CA 8
BL8OTF RDS8 H H L H L H BA RFU H L CA 8
READ with auto precharge
BL8MRS, BC4MRS RDAP H H L H L H BA RFU V H CA 8
BC4OTF RDAPS4 H H L H L H BA RFU L H CA 8
BL8OTF RDAPS8 H H L H L H BA RFU H H CA 8
NO OPERATION NOP H H H H H V V V V V 9
Device DESELECTED DES H H H X X X X X X X X 10
Power-down entry PDE H LL H H H
V V V V V 6H V V V
Power-down exit PDX L HL H H H
V V V V V6, 11
H V V V
ZQ CALIBRATION LONG ZQCL H H L H H L X X X H X 12
ZQ CALIBRATION SHORT ZQCS H H L H H L X X X L X
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Table 20: Truth Table - Command (continued)
Notes:
1. CommandsaredefinedbythestatesofCS#,RAS#,CAS#,WE#,andCKEattherisingedgeoftheclock.TheMSBofBA,RA,andCAaredevice-,density-,andconfiguration-dependent.
2. RESET#isenabledLOWandusedonlyforasynchronousreset.Thus,RESET#mustbeheldHIGHduringanynormaloperation.
3. ThestateofODTdoesnotaffectthestatesdescribedinthistable.
4. Operationsapplytothebankdefinedbythebankaddress.ForMRS,BAselectsoneoffourmoderegisters.
5. “V”means“H”or“L”(adefinedlogiclevel),and“X”means“Don’tCare.”
6. SeeTable21(page34)foradditionalinformationonCKEtransition.
7. Selfrefreshexitisasynchronous.
8. BurstREADsorWRITEscannotbeterminatedorinterrupted.MRS(fixed)andOTFBL/BCaredefinedinMR0.
9. ThepurposeoftheNOPcommandistopreventtheDRAMfromregisteringanyunwantedcommands.ANOPwillnotterminateanoperationthatisexecuting.
10. TheDESandNOPcommandsperformsimilarly.
11. Thepower-downmodedoesnotperformanyREFRESHoperations.
12. ZQCALIBRATIONLONGisusedforeitherZQinit(firstZQCLcommandduringinitialization)orZQoper(ZQCLcommandafterinitialization).
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Table 21: Truth Table - CKE
Notes1and2applytotheentiretable.
Current State3
CKECommand5
(RAS#, CAS#, WE#, CS#)Action5 NotesPrevious Cycle4
(n - 1)Present Cycle4
(n - 1)
Power-downL L “Don’t Care” Maintain power-down
L H DES or NOP Power-down exit
Self-refreshL L “Don’t Care” Maintain self refresh
L H DES or NOP Self refresh exit
Bank(s) active H L DES or NOP Active power-down entry
Reading H L DES or NOP Power-down entry
Writing H L DES or NOP Power-down entry
Precharging H L DES or NOP Power-down entry
Refreshing H L DES or NOP Precharge power-down entry
All banks idleH L DES or NOP Precharge power-down entry
6H L REFRESH Self refresh
Notes:
1. Allstatesandsequencesnotshownareillegalorreservedunlessexplicitlydescribedelsewhereinthisdocument.
2. tCKE(MIN)meansCKEmustberegisteredatmultipleconsecutivepositiveclockedges.CKEmustremainatthevalidinputleveltheentiretimeittakestoachievetherequirednumberofregistrationclocks.Thus,afteranyCKEtransition,CKEmaynottransitionfromitsvalidlevelduringthetimeperiodoftIS+tCKE(MIN)+tIH.
3. Currentstate=ThestateoftheDRAMimmediatelypriortoclockedgen.
4. CKE(n)isthelogicstateofCKEatclockedgen;CKE(n-1)wasthestateofCKEatthepreviousclockedge.
5. COMMANDisthecommandregisteredattheclockedge(mustbealegalcommandasdefinedinTable20(page32)).ActionisaresultofCOMMAND.ODTdoesnotaffectthestatesdescribedinthistableandisnotlisted.
6. Idlestate=Allbanksareclosed,nodataburstsareinprogress,CKEisHIGH,andalltimingsfrompreviousoperationsaresatisfied.Allselfrefreshexitandpower-downexitparametersarealsosatisfied.
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Form #: CSI-D-685 Document 007
Commands
DESELECT
The DESELT (DES) command (CS# HIGH) prevents newcommands from being executed by the DRAM. Operationsalreadyinprogressarenotaffected.
NO OPERATION
TheNOOPERATION (NOP)command (CS#LOW)preventsunwantedcommandsfrombeingregisteredduringidleorwaitstates.Operationsalreadyinprogressarenotaffected.
ZQ CALIBRATION LONG
The ZQCALIBRATION LONG (ZQCL) command is used toperformtheinitialcalibrationduringapower-upinitializationandreset sequence (see Figure 17 (page 51)). This commandmay be issued at any time by the controller, dependingon the system environment. The ZQCL command triggersthe calibration engine inside the DRAM. After calibrationis achieved, the calibrated values are transferred from thecalibration engine to the DRAM I/O, which are reflected asupdatedRONandODTvalues.
TheDRAMisallowedatimingwindowdefinedbyeithertZQinitortZQopertoperformafullcalibrationandtransferofvalues.WhenZQCL is issuedduring the initialization sequence, thetimingparametertZQinitmustbesatisfied.Wheninitializationiscomplete,subsequentZQCLcommandsrequirethetimingparametertZQopertobesatisfied.
ZQ CALIBRATION SHORT
TheZQCALIBRATIONSHORT(ZQCS)commandisusedtoperformperiodiccalibrationstoaccountforsmallvoltageandtemperature variations. A shorter timingwindow is providedtoperform the reducedcalibrationand transfer of valuesasdefinedbytimingparameter tZQCS.AZQCScommandcaneffectivelycorrectaminimumof0.5%RONandRTTimpedanceerror within 64 clock cycles, assuming the maximumsensitivitiesspecified.
ACTIVATE
TheACTIVATEcommandisusedtoopen(oractivate)arowinaparticularbankforasubsequentaccess.ThevalueontheBA[2:0]inputsselectsthebank,andtheaddressprovidedoninputsA[n:0]selectstherow.Thisrowremainsopen(oractive)foraccessesuntilaPRECHARGEcommandisissuedtothatbank.
APRECHARGEcommandmustbeissuedbeforeopeningadifferentrowinthesamebank.
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READ
TheREADcommandisusedtoinitiateaburstreadaccesstoanactiverow.TheaddressprovidedoninputsA[2:0]selectsthe starting columnaddress, dependingon theburst lengthandburst typeselected (seeBurstOrder table foradditionalinformation).ThevalueoninputA10determineswhetherautoprechargeisused.Ifautoprechargeisselected,therowbeing
accessedwillbeprechargedattheendoftheREADburst.Ifautoprecharge isnotselected, the rowwill remainopen forsubsequentaccesses.ThevalueoninputA12(ifenabledinthemoderegister)whentheREADcommandisissueddetermineswhetherBC4(chop)orBL8isused.AfteraREADcommandisissued,theREADburstmaynotbeinterrupted.
Table 22: READ Command Summary
Functions SymbolCKE
CS# RAS# CAS# WE#BA
[3:0]An A12 A10
A[11, 9:0]Prev. Cycle Next Cycle
READ
BL8MRS, BC4MRS RD
H L H L H BA RFU
V L
CA
BC4OTF RDS4 L L
BL8OTF RDS8 H L
READ with auto precharge
BL8MRS, BC4MRS RDAP V H
BC4OTF RDAPS4 L H
BL8OTF RDAPS8 H H
WRITE
TheWRITEcommandisusedtoinitiateaburstwriteaccesstoanactiverow.ThevalueontheBA[2:0]inputsselectsthebank.ThevalueoninputA10determineswhetherautoprechargeisused.ThevalueoninputA12(ifenabledintheMR)whentheWRITEcommandisissueddetermineswhetherBC4(chop)orBL8isused.
InputdataappearingontheDQiswrittentothememoryarraysubjecttotheDMinputlogiclevelappearingcoincidentwiththedata.IfagivenDMsignalisregisteredLOW,thecorrespondingdatawillbewrittentomemory. If theDMsignal is registeredHIGH, the corresponding data inputs will be ignored and aWRITEwillnotbeexecutedtothatbyte/columnlocation.
Table 23: WRITE Command Summary
Functions SymbolCKE
CS# RAS# CAS# WE#BA
[3:0]An A12 A10
A[11, 9:0]Prev. Cycle Next Cycle
WRITE
BL8MRS, BC4MRS WR
H L H L L BA RFU
V L
CA
BC4OTF WRS4 L L
BL8OTF WRS8 H L
WRITE with auto precharge
BL8MRS, BC4MRS WRAP V H
BC4OTF WRAPS4 L H
BL8OTF WRAPS8 H H
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PRECHARGE
The PRECHARGE command is used to de-activate theopenrowinaparticularbankorinallbanks.Thebank(s)areavailable forasubsequent rowaccessaspecifiedtime (tRP)afterthePRECHARGEcommandisissued,exceptinthecaseofconcurrentautoprecharge.AREADorWRITEcommandtoadifferentbankisallowedduringaconcurrentautoprechargeaslongasitdoesnotinterruptthedatatransferinthecurrentbankanddoesnotviolateanyothertimingparameters.InputA10determineswhetheroneorallbanksareprecharged. Inthecasewhereonlyonebank isprecharged, inputsBA[2:0]selectthebank;otherwise,BA[2:0]aretreatedas“Don’tCare.”
Afterabankisprecharged,itisintheidlestateandmustbeactivatedpriortoanyREADorWRITEcommandsbeingissuedtothatbank.APRECHARGEcommandistreatedasaNOPifthereisnoopenrowinthatbank(idlestate)orifthepreviouslyopenrow isalready intheprocessofprecharging.However,theprechargeperiodisdeterminedbythelastPRECHARGEcommandissuedtothebank.
REFRESH
The REFRESH command is used during normal operationof theDRAMand isanalogoustoCAS#-before-RAS#(CBR)refreshorautorefresh.Thiscommandisnonpersistent,so itmustbeissuedeachtimearefreshisrequired.Theaddressingisgeneratedbytheinternalrefreshcontroller.Thismakestheaddress bits a “Don’t Care” during a REFRESH command.TheDRAM requiresREFRESHcycles at an average intervalof7.8μs(maximumwhenTC≤85°Cor3.9μsmaximumwhenTC≤95°C).TheREFRESHperiodbeginswhentheREFRESHcommandisregisteredandendstRFC(MIN)later.
Toallow for improvedefficiency in schedulingand switchingbetweentasks,someflexibilityintheabsoluterefreshintervalisprovided.Amaximumof eightREFRESHcommandscanbe posted to any givenDRAM,meaning that themaximumabsolute interval betweenanyREFRESHcommandand thenextREFRESHcommandisninetimesthemaximumaverageinterval refresh rate. Self refreshmay be enteredwith up toeight REFRESH commands being posted. After exiting selfrefresh (when entered with posted REFRESH commands),
additional posting of REFRESH commands is allowed tothe extent that themaximum number of cumulative postedREFRESHcommands(bothpreandpost-selfrefresh)doesnotexceedeightREFRESHcommands.
At any given time, amaximumof 16REFRESHcommandscanbeissuedwithin2xtREFI.
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Figure 42: Refresh Mode
NOP1NOP1 NOP1PRE
RA
Bank(s)3 BA
REF NOP5 REF2 NOP5 ACTNOP5
One bank
All banks
tCK tCH tCL
RA
tRFC2tRP tRFC (MIN)
T0 T1 T2 T3 T4 Ta0 Tb0Ta1 Tb1 Tb2
Don’t CareIndicates breakin time scale
Valid5 Valid5 Valid5
CK
CK#
Command
CKE
Address
A10
BA[2:0]
DQ4
DM4
DQS, DQS#4
Notes: 1. NOP commands are shown for ease of illustration; other valid commands may be possi-ble at these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESHcommands, but may be inactive at other times (see Power-Down Mode (page 183)).
2. The second REFRESH is not required, but two back-to-back REFRESH commands areshown.
3. “Don’t Care” if A10 is HIGH at this point; however, A10 must be HIGH if more than onebank is active (must precharge all active banks).
4. For operations shown, DM, DQ, and DQS signals are all “Don’t Care”/High-Z.5. Only NOP and DES commands are allowed after a REFRESH command and until tRFC
(MIN) is satisfied.
SELF REFRESH
The SELF REFRESH command is used to retain data in the DRAM, even if the rest of thesystem is powered down. When in self refresh mode, the DRAM retains data without ex-ternal clocking. Self refresh mode is also a convenient method used to enable/disablethe DLL as well as to change the clock frequency within the allowed synchronous oper-ating range (see Input Clock Frequency Change (page 127)). All power supply inputs(including VREFCA and VREFDQ) must be maintained at valid levels upon entry/exit andduring self refresh mode operation. VREFDQ may float or not drive VDDQ/2 while in selfrefresh mode under the following conditions:
• VSS < VREFDQ < VDD is maintained• VREFDQ is valid and stable prior to CKE going back HIGH• The first WRITE operation may not occur earlier than 512 clocks after V REFDQ is valid• All other self refresh mode exit timing requirements are met
1Gb: x4, x8, x16 DDR3 SDRAMCommands
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Figure 9: Refresh Mode
Notes:
1. NOPcommandsareshownforeaseofillustration;othervalidcommandsmaybepossibleatthesetimes.CKEmustbeactiveduringthePRECHARGE,ACTIVATE,andREFRESHcommands,butmaybeinactiveatothertimes(seePower-DownMode).
2. ThesecondREFRESHisnotrequired,buttwoback-to-backREFRESHcommandsareshown.
3. “Don’tCare”ifA10isHIGHatthispoint;however,A10mustbeHIGHifmorethanonebankisactive(mustprechargeallactivebanks).
4. Foroperationsshown,DM,DQ,andDQSsignalsareall“Don’tCare”/High-Z.
5. OnlyNOPandDEScommandsareallowedafteraREFRESHcommandanduntiltRFC(MIN)issatisfied.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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SELF REFRESH
TheSELFREFRESHcommand isused to retaindata in theDRAM,eveniftherestofthesystemispowereddown.Wheninself refreshmode,theDRAMretainsdatawithoutexternalclocking.Selfrefreshmodeisalsoaconvenientmethodusedto enable/disable the DLL as well as to change the clockfrequency within the allowed synchronous operating range(seeInputClockFrequencyChange).Allpowersupplyinputs(including VREFCA and VREFDQ) must bemaintained at validlevelsuponentry/exitandduringselfrefreshmodeoperation.VREFDQmayfloatornotdriveVDDQ/2whileinselfrefreshmodeunderthefollowingconditions:
• VSS<VREFDQ<VDDismaintained
• VREFDQisvalidandstablepriortoCKEgoingbackHIGH
• ThefirstWRITEoperationmaynotoccurearlierthan512clocksafterVREFDQisvalid
• Allotherselfrefreshmodeexittimingrequirementsaremet
DLL Disable Mode
If theDLL is disabled by themode register (MR1[0] can beswitchedduring initializationor later), theDRAM is targeted,butnotguaranteed,tooperatesimilarlytothenormalmode,withafewnotableexceptions:
• TheDRAMsupportsonlyonevalueofCASlatency(CL=6)andonevalueofCASWRITElatency(CWL=6).
• DLLdisablemodeaffectsthereaddataclock-to-datastroberelationship(tDQSCK),butnotthereaddata-to-datastroberelationship(tDQSQ,tQH).SpecialattentionisrequiredtolineupthereaddatawiththecontrollertimedomainwhentheDLLisdisabled.
• Innormaloperation(DLLon),tDQSCKstartsfromtherisingclockedgeAL+CL
• cyclesaftertheREADcommand.InDLLdisablemode,tDQSCKstartsAL+CL-1cyclesaftertheREADcommand.Additionally,withtheDLLdisabled,thevalueoftDQSCKcouldbelargerthantCK.
The ODT feature (including dynamic ODT) is not supportedduringDLLdisablemode.TheODTresistorsmustbedisabledbycontinuouslyregisteringtheODTballLOWbyprogrammingRTT,nomMR1[9,6,2]andRTT(WR)MR2[10,9]to0whileintheDLLdisablemode.
Specificstepsmustbe followed toswitchbetween theDLLenableandDLLdisablemodesdue toagap in theallowedclockratesbetweenthetwomodes(tCK[AVG]MAXandtCK[DLL_DIS]MIN,respectively).Theonlytimetheclockisallowedtocrossthisclockrategapisduringselfrefreshmode.Thus,the required procedure for switching from the DLL enablemodetotheDLLdisablemodeistochangefrequencyduringselfrefresh:
1.Startingfromtheidlestate(allbanksareprecharged,alltimingsarefulfilled,ODTisturnedoff,andRTT,nomandRTT(WR)areHigh-Z),setMR1[0]to1todisabletheDLL.
2.EnterselfrefreshmodeaftertMODhasbeensatisfied.
3.AftertCKSREissatisfied,changethefrequencytothedesiredclockrate.
4.SelfrefreshmaybeexitedwhentheclockisstablewiththenewfrequencyfortCKSRX.AftertXSissatisfied,updatethemoderegisterswithappropriatevalues.
5.TheDRAMwillbereadyforitsnextcommandintheDLLdisablemodeafterthegreateroftMRDortMODhasbeensatisfied.AZQCLcommandshouldbeissuedwithappropriatetimingsmet.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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Form #: CSI-D-685 Document 007
Figure 43: DLL Enable Mode to DLL Disable Mode
Command
T0 T1 Ta0 Ta1 Tb0 Tc0 Td0 Td1 Te0 Te1 Tf0
CKCK#
ODT9 Valid1
Don’t Care
Valid1
SRE3 NOPMRS2 NOP SRX4 MRS5 Valid1NOP NOP
Indicates breakin time scale
tMOD tCKSRE tMODtXS
tCKESR
CKE
tCKSRX876
Notes: 1. Any valid command.2. Disable DLL by setting MR1[0] to 1.3. Enter SELF REFRESH.4. Exit SELF REFRESH.5. Update the mode registers with the DLL disable parameters setting.6. Starting with the idle state, RTT is in the High-Z state.7. Change frequency.8. Clock must be stable tCKSRX.9. Static LOW in the case that RTT,nom or RTT(WR) is enabled; otherwise, static LOW or HIGH.
A similar procedure is required for switching from the DLL disable mode back to theDLL enable mode. This also requires changing the frequency during self refresh mode(see Figure 44 (page 125)).
1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODTis turned off, and RTT,nom and RTT(WR) are High-Z), enter self refresh mode.
2. After tCKSRE is satisfied, change the frequency to the new clock rate.3. Self refresh may be exited when the clock is stable with the new frequency for
tCKSRX. After tXS is satisfied, update the mode registers with the appropriate val-ues. At a minimum, set MR1[0] to 0 to enable the DLL. Wait tMRD, then set MR0[8]to 1 to enable DLL RESET.
4. After another tMRD delay is satisfied, update the remaining mode registers withthe appropriate values.
5. The DRAM will be ready for its next command in the DLL enable mode after thegreater of tMRD or tMOD has been satisfied. However, before applying any com-mand or function requiring a locked DLL, a delay of tDLLK after DLL RESET mustbe satisfied. A ZQCL command should be issued with the appropriate timings met.
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Figure 10: DLL Enable Mode to DLL Disable Mode
Notes:
1. Anyvalidcommand.
2. DisableDLLbysettingMR1[0]to1.
3. EnterSELFREFRESH.
4. ExitSELFREFRESH.
5. UpdatethemoderegisterswiththeDLLdisableparameterssetting.
6. Startingwiththeidlestate,RTTisintheHigh-Zstate.
7. Changefrequency.
8. ClockmustbestabletCKSRX.
9. StaticLOWinthecasethatRTT,nomorRTT(WR)isenabled;otherwise,staticLOWorHIGH.
A similar procedure is required for switching from the DLLdisablemodebacktotheDLLenablemode.Thisalsorequireschangingthefrequencyduringselfrefreshmode.
1.Startingfromtheidlestate(allbanksareprecharged,alltimingsarefulfilled,ODTisturnedoff,andRTT,nomandRTT(WR)areHigh-Z),enterselfrefreshmode.
2.AftertCKSREissatisfied,changethefrequencytothenewclockrate.
3.SelfrefreshmaybeexitedwhentheclockisstablewiththenewfrequencyfortCKSRX.AftertXSissatisfied,updatethemoderegisterswiththeappropriatevalues.Ataminimum,setMR1[0]to0toenabletheDLL.WaittMRD,thensetMR0[8]to1toenableDLLRESET.
4.AfteranothertMRDdelayissatisfied,updatetheremainingmoderegisterswiththeappropriatevalues.
5.TheDRAMwillbereadyforitsnextcommandintheDLLenablemodeafterthegreateroftMRDortMODhasbeensatisfied.However,beforeapplyinganycommandorfunctionrequiringalockedDLL,adelayoftDLLKafterDLLRESETmustbesatisfied.AZQCLcommandshouldbeissuedwiththeappropriatetimingsmet.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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Figure 44: DLL Disable Mode to DLL Enable Mode
CKE
T0 Ta0 Ta1 Tb0 Tc0 Tc1 Td0 Te0 Tf0 Tg0
CKCK#
ODT10
SRE1 NOPCommand NOP SRX2 MRS3 MRS4 MRS5 Valid6
Valid
Don’t CareIndicates breakin time scale
tCKSRE tCKSRX987 tXS tMRD tMRD
tCKESR
ODTLoff + 1 × tCK
Th0
tDLLK
Notes: 1. Enter SELF REFRESH.2. Exit SELF REFRESH.3. Wait tXS, then set MR1[0] to 0 to enable DLL.4. Wait tMRD, then set MR0[8] to 1 to begin DLL RESET.5. Wait tMRD, update registers (CL, CWL, and write recovery may be necessary).6. Wait tMOD, any valid command.7. Starting with the idle state.8. Change frequency.9. Clock must be stable at least tCKSRX.
10. Static LOW in the case that RTT,nom or RTT(WR) is enabled; otherwise, static LOW or HIGH.
The clock frequency range for the DLL disable mode is specified by the parameter tCK(DLL_DIS). Due to latency counter and timing restrictions, only CL = 6 and CWL = 6 aresupported.
DLL disable mode will affect the read data clock to data strobe relationship (tDQSCK)but not the data strobe to data relationship (tDQSQ, tQH). Special attention is needed toline up read data to the controller time domain.
Compared to the DLL on mode where tDQSCK starts from the rising clock edge AL + CLcycles after the READ command, the DLL disable mode tDQSCK starts AL + CL - 1 cyclesafter the READ command.
WRITE operations function similarly between the DLL enable and DLL disable modes;however, ODT functionality is not allowed with DLL disable mode.
1Gb: x4, x8, x16 DDR3 SDRAMCommands
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Notes:
1. EnterSELFREFRESH.
2. ExitSELFREFRESH.
3. WaittXS,thensetMR1[0]to0toenableDLL.
4. WaittMRD,thensetMR0[8]to1tobeginDLLRESET.
5. WaittMRD,updateregisters(CL,CWL,andwriterecoverymaybenecessary).
6. WaittMOD,anyvalidcommand.
7. Startingwiththeidlestate.
8. Changefrequency.
9. ClockmustbestableatleasttCKSRX.
10. StaticLOWinthecasethatRTT,nomorRTT(WR)isenabled;otherwise,staticLOWorHIGH.
Figure 11: DLL Disable Mode to DLL Enable Mode
The clock frequency range for the DLL disable mode isspecified by the parameter tCK (DLL_DIS). Due to latencycounterandtimingrestrictions,onlyCL=6andCWL=6aresupported.
DLL disable mode will affect the read data clock to datastroberelationship (tDQSCK)butnotthedatastrobetodatarelationship (tDQSQ, tQH).Specialattention isneededto lineupreaddatatothecontrollertimedomain.
ComparedtotheDLLonmodewheretDQSCKstartsfromtherisingclockedgeAL+CLcyclesaftertheREADcommand,theDLLdisablemodetDQSCKstartsAL+CL-1cyclesaftertheREADcommand.
WRITEoperations functionsimilarlybetweentheDLLenableand DLL disable modes; however, ODT functionality is notallowedwithDLLdisablemode.
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Figure 45: DLL Disable tDQSCK
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
Don’t CareTransitioning Data
Valid
NOPREAD NOP NOP NOP NOP NOP NOP NOP NOP NOP
CK
CK#
Command
Address
DIb + 3
DIb + 2
DIb + 1
DIb
DIb + 7
DIb + 6
DIb + 5
DIb + 4
DQ BL8 DLL on
DQS, DQS# DLL on
DQ BL8 DLL disable
DQS, DQS# DLL off
DQ BL8 DLL disable
DQS, DQS# DLL off
RL = AL + CL = 6 (CL = 6, AL = 0)
CL = 6
DIb + 3
DIb + 2
DIb + 1
DIb
DIb + 7
DIb + 6
DIb + 5
DIb + 4
DIb + 3
DIb + 2
DIb + 1
DIb
DIb + 7
DIb + 6
DIb + 5
DIb + 4
tDQSCK (DLL_DIS) MIN
tDQSCK (DLL_DIS) MAX
RL (DLL_DIS) = AL + (CL - 1) = 5
Table 74: READ Electrical Characteristics, DLL Disable Mode
Parameter Symbol Min Max Unit
Access window of DQS from CK, CK# tDQSCK (DLL_DIS) 1 10 ns
1Gb: x4, x8, x16 DDR3 SDRAMCommands
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Figure 12: DLL Disable tDQSCK
Table 24: READ Electrical Characteristics, DLL Disable Mode
Parameter Symbol Min Max Unit
Access window of DQS from CK, CK# tDQSCK (DLL_DIS) 1 10 ns
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
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1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Input Clock Frequency Change
When the DDR3 SDRAM is initialized, the clock must bestable during most normal states of operation. This meansthataftertheclockfrequencyhasbeensettothestablestate,theclockperiodisnotallowedtodeviate,exceptforwhatisallowedbytheclockjitterandspreadspectrumclocking(SSC)specifications.
The input clock frequency canbe changed fromone stableclockratetoanotherundertwoconditions:selfrefreshmodeandprechargepower-downmode. It is illegal tochange theclock frequency outside of those two modes. For the selfrefreshmode condition,when the DDR3SDRAM has beensuccessfully placed into self refreshmode and tCKSRE hasbeensatisfied,thestateoftheclockbecomesa“Don’tCare.”Whentheclockbecomesa“Don’tCare,”changingtheclockfrequency ispermissible if thenewclock frequency isstablepriortotCKSRX.Whenenteringandexitingselfrefreshmodeforthesolepurposeofchangingtheclockfrequency,theselfrefreshentryandexitspecificationsmuststillbemet.
The precharge power-down mode condition is when theDDR3SDRAMisinprechargepower-downmode(eitherfastexitmodeorslowexitmode).EitherODTmustbeatalogicLOWorRTT,nomandRTT(WR)mustbedisabledviaMR1andMR2.ThisensuresRTT,nomandRTT(WR)areinanoffstatepriortoenteringprechargepower-downmode,andCKEmustbeatalogicLOW.AminimumoftCKSREmustoccurafterCKEgoesLOWbeforetheclockfrequencycanchange.TheDDR3SDRAMinputclockfrequencyisallowedtochangeonlywithinthe minimum and maximum operating frequency specifiedfor theparticular speedgrade (tCK [AVG]MIN to tCK [AVG]MAX).Duringtheinputclockfrequencychange,CKEmustbeheldata stableLOW level.When the inputclock frequencyis changed, a stable clockmust be provided to the DRAMtCKSRXbeforeprechargepower-downmaybeexited.Afterprechargepower-down isexitedand tXPhasbeensatisfied,theDLLmustbe resetvia theMRS.Dependingon thenewclockfrequency,additionalMRScommandsmayneedtobeissued.During theDLL lock time,RTT,nomandRTT(WR)mustremain inanoffstate.After theDLL lock time, theDRAM isreadytooperatewithanewclockfrequency.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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Form #: CSI-D-685 Document 007
Figure 13: Change Frequency During Precharge Power-DownFigure 46: Change Frequency During Precharge Power-Down
CK
CK#
Command NOPNOPNOP
Address
CKE
DQ
DM
DQS, DQS#
NOP
tCK
Enter prechargepower-down mode
Exit prechargepower-down mode
T0 T1 Ta0 Tc0Tb0T2
Don’t Care
tCKE
tXP
MRS
DLL RESET
Valid
Valid
NOP
tCH
tIH tIS
tCL
Tc1 Td0 Te1Td1
tCKSRE
tCHbtCLb
tCKb
tCHbtCLb
tCKb
tCHbtCLb
tCKb
tCPDED
ODT
NOP
Te0
Previous clock frequency New clock frequency
Frequencychange
Indicates breakin time scale
tIH tIS
tIH
tIS
tDLLK
tAOFPD/tAOF
tCKSRX
High-Z
High-Z
Notes: 1. Applicable for both SLOW-EXIT and FAST-EXIT precharge power-down modes.2. tAOFPD and tAOF must be satisfied and outputs High-Z prior to T1 (see On-Die Termina-
tion (ODT) (page 193) for exact requirements).3. If the RTT,nom feature was enabled in the mode register prior to entering precharge
power-down mode, the ODT signal must be continuously registered LOW, ensuring RTTis in an off state. If the RTT,nom feature was disabled in the mode register prior to enter-ing precharge power-down mode, RTT will remain in the off state. The ODT signal canbe registered LOW or HIGH in this case.
1Gb: x4, x8, x16 DDR3 SDRAMInput Clock Frequency Change
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Notes:
1. ApplicableforbothSLOW-EXITandFAST-EXITprechargepower-downmodes.
2. tAOFPDandtAOFmustbesatisfiedandoutputsHigh-ZpriortoT1(seeOn-DieTermination(ODT)(page103))forexactrequirements).
3. IftheRTT,nomfeaturewasenabledinthemoderegisterpriortoenteringprechargepower-downmode,theODTsignalmustbecontinuouslyregisteredLOW,ensuringRTTisinanoffstate.IftheRTT,nomfeaturewasdisabledinthemoderegisterpriortoenteringprechargepower-downmode,RTTwillremainintheoffstate.TheODTsignalcanberegisteredLOWorHIGHinthiscase.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
45
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Write Leveling
For better signal integrity, DDR3 SDRAM memory moduleshaveadoptedfly-bytopologyforthecommands,addresses,controlsignals,andclocks.Writelevelingisaschemeforthememorycontrollertoadjustorde-skewtheDQSstrobe(DQS,DQS#)toCKrelationshipattheDRAMwithasimplefeedbackfeatureprovidedbytheDRAM.Writelevelingisgenerallyusedas part of the initialization process, if required. For normalDRAM operation, this featuremust be disabled. This is theonlyDRAMoperationwheretheDQSfunctionsasaninput(tocapture the incomingclock)andtheDQfunctionasoutputs(toreportthestateoftheclock).NotethatnonstandardODTschemesarerequired.
ThememorycontrollerusingthewritelevelingproceduremusthaveadjustabledelaysettingsonitsDQSstrobetoaligntherising edge of DQS to the clock at the DRAM pins. This isaccomplished when the DRAM asynchronously feeds backthe CK status via the DQ bus and samples with the risingedgeofDQS.ThecontrollerrepeatedlydelaystheDQSstrobeuntilaCKtransitionfrom0to1 isdetected.TheDQSdelayestablishedbythisprocedurehelpsensuretDQSS,tDSS,andtDSHspecificationsinsystemsthatusefly-bytopologybyde-skewingthetracelengthmismatch.Aconceptualtimingofthisprocedureisshowninthefigurebelow.
Write LevelingFor better signal integrity, DDR3 SDRAM memory modules have adopted fly-by topolo-gy for the commands, addresses, control signals, and clocks. Write leveling is a schemefor the memory controller to adjust or de-skew the DQS strobe (DQS, DQS#) to CK rela-tionship at the DRAM with a simple feedback feature provided by the DRAM. Write lev-eling is generally used as part of the initialization process, if required. For normalDRAM operation, this feature must be disabled. This is the only DRAM operation wherethe DQS functions as an input (to capture the incoming clock) and the DQ function asoutputs (to report the state of the clock). Note that nonstandard ODT schemes are re-quired.
The memory controller using the write leveling procedure must have adjustable delaysettings on its DQS strobe to align the rising edge of DQS to the clock at the DRAM pins.This is accomplished when the DRAM asynchronously feeds back the CK status via theDQ bus and samples with the rising edge of DQS. The controller repeatedly delays theDQS strobe until a CK transition from 0 to 1 is detected. The DQS delay established bythis procedure helps ensure tDQSS, tDSS, and tDSH specifications in systems that usefly-by topology by de-skewing the trace length mismatch. A conceptual timing of thisprocedure is shown in Figure 47.
Figure 47: Write Leveling Concept
CK
CK#
Source
Differential DQS
Differential DQS
Differential DQS
DQ
DQ
CK
CK#
Destination
Destination
Push DQS to capture 0–1 transition
T0 T1 T2 T3 T4 T5 T6 T7
T0 T1 T2 T3 T4 T5 T6Tn
CK
CK#T0 T1 T2 T3 T4 T5 T6Tn
Don’t Care
1 1
00
1Gb: x4, x8, x16 DDR3 SDRAMWrite Leveling
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Figure 14: Write Leveling Concept
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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Form #: CSI-D-685 Document 007
Whenwritelevelingisenabled,therisingedgeofDQSsamplesCK,andtheprimeDQoutputsthesampledCK’sstatus.TheprimeDQforax4orx8configurationisDQ0withallotherDQ(DQ[7:1])drivingLOW.TheprimeDQforax16configurationisDQ0forthelowerbyteandDQ8fortheupperbyte.ItoutputsthestatusofCKsampledbyLDQSandUDQS.AllotherDQ(DQ[7:1],DQ[15:9])continuetodriveLOW.TwoprimeDQonax16enableeachbytelanetobeleveledindependently.
The write leveling mode register interacts with other moderegisters tocorrectlyconfigure thewrite leveling functionality.
Write Leveling (continued)
BesidesusingMR1[7]todisable/enablewriteleveling,MR1[12]mustbeusedtoenable/disabletheoutputbuffers.TheODTvalue,burstlength,andsoforthneedtobeselectedaswell.Thisinteractionisshowninthetablebelow.Itshouldalsobenotedthatwhentheoutputsareenabledduringwritelevelingmode,theDQSbuffersaresetasinputs,andtheDQaresetasoutputs.Additionally,duringwrite levelingmode,only theDQSstrobeterminationsareactivatedanddeactivatedviatheODTball.TheDQremaindisabledandarenotaffectedbytheODTball.
Table 25: Write Leveling Matrix
MR1[7] MR1[12] MR1[2, 6, 9]DRAM ODT
Ball
DRAM RTT,nom
DRAM State Case NotesWrite Leveling
Output Buffers
RTT,nom Value
DQS DQ
Disabled See normal operations Write leveling not enabled 0
Enabled (1)
Disabled (1)
NA Low Off
Off
DQS not receiving: not terminated Prime DQ High-Z: not terminated Other DQ High-Z: not terminated
1 2
20Ω, 30Ω, 40Ω, 60Ω or
120ΩHigh On
DQS not receiving: terminated by RTT Prime DQ High-Z: not terminated Other DQ High-Z: not terminated
2
Enabled (0)
NA Low OffDQS receiving: not terminated Prime DQ driving CK state: not terminated Other DQ driving LOW: not terminated
3 3
40Ω, 60Ω or 120Ω High On
DQS receiving: terminated by RTTPrime DQ driving CK state: not terminatedOther DQ driving LOW: not terminated
4
Notes:
1. Expectedusageifusedduringwriteleveling:Case1maybeusedwhenDRAMareonadual-rankmoduleandontheranknotbeingleveledoronanyrankofamodulenotbeingleveledonamultislotsystem.Case2maybeusedwhenDRAMareonanyrankofamodulenotbeingleveledonamultislotsystem.Case3isgenerallynotused.Case4isgenerallyusedwhenDRAMareontherankthatisbeingleveled.
2. SincetheDRAMDQSisnotbeingdriven(MR1[12]=1),DQSignorestheinputstrobe,andallRTT,nomvaluesareallowed.ThissimulatesanormalstandbystatetoDQS.
3. SincetheDRAMDQSisbeingdriven(MR1[12]=0),DQScapturestheinputstrobe,andonlysomeRTT,nomvaluesareallowed.ThissimulatesanormalwritestatetoDQS.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Write Leveling Procedure
AmemorycontrollerinitiatestheDRAMwritelevelingmodebysettingMR1[7]to1,assumingtheotherprogramablefeatures(MR0,MR1,MR2,andMR3)arefirstsetandtheDLLisfullyresetandlocked.TheDQballsenterthewritelevelingmodegoing from aHigh-Z state to an undefined driving state, sotheDQbusshouldnotbedriven.Duringwritelevelingmode,only theNOPorDEScommandsare allowed.Thememorycontroller should attempt to level only one rank at a time;thus,theoutputsofotherranksshouldbedisabledbysettingMR1[12]to1 intheotherranks.ThememorycontrollermayassertODTafteratMODdelay,astheDRAMwillbereadytoprocesstheODTtransition.ODTshouldbeturnedonpriortoDQSbeingdrivenLOWbyatleastODTLondelay(WL-2tCK),provided it doesnot violate the aforementioned tMODdelayrequirement.
ThememorycontrollermaydriveDQSLOWandDQS#HIGHafter tWLDQSEN has been satisfied. The controller maybegintotoggleDQSaftertWLMRD(oneDQStoggleisDQStransitioning from a LOW state to a HIGH statewith DQS#transitioning from a HIGH state to a LOW state, then bothtransitionbacktotheiroriginalstates).Ataminimum,ODTLonand tAONmustbesatisfiedat leastoneclockprior toDQStoggling.
AftertWLMRDandaDQSLOWpreamble(tWPRE)havebeensatisfied, thememory controller may provide either a singleDQStoggleormultipleDQStogglestosampleCKforagivenDQS-to-CKskew.EachDQStogglemustnotviolate tDQSL(MIN) and tDQSH (MIN) specifications. tDQSL (MAX) andtDQSH (MAX) specifications are not applicable during writelevelingmode.TheDQSmustbeabletodistinguishtheCK’srisingedgewithintWLSandtWLH.TheprimeDQwilloutputtheCK’sstatusasynchronouslyfromtheassociatedDQSrisingedgeCKcapturewithintWLO.TheremainingDQthatalwaysdriveLOWwhenDQSistogglingmustbeLOWwithintWLOEafterthefirsttWLOissatisfied(theprimeDQgoingLOW).Aspreviouslynoted,DQS is an inputandnotanoutputduringthis process. Figure 15 (page 48) depicts the basic timingparametersfortheoverallwritelevelingprocedure.
Thememorycontrollerwillmostlikelysampleeachapplicableprime DQ state and determine whether to increment ordecrementitsDQSdelaysetting.Afterthememorycontrollerperforms enough DQS toggles to detect the CK’s 0-to-1transition, thememorycontroller should lock theDQSdelaysettingforthatDRAM.AfterlockingtheDQSsettingislocked,leveling for the rankwill have been achieved, and thewritelevelingmodefortherankshouldbedisabledorreprogrammed(ifwritelevelingofanotherrankfollows).
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Figure 15: Write Leveling SequenceFigure 48: Write Leveling Sequence
CKCK#
Command
T1 T2
Early remaining DQ
Late remaining DQ
tWLOE
NOP2 NOPMRS1 NOP NOP NOP NOP NOP NOP NOP NOP NOP
tWLStWLH
Don’t CareUndefined Driving ModeIndicates breakin time scale
Prime DQ5
Differential DQS4
ODT
tMOD
tDQSL3 tDQSL3tDQSH3 tDQSH3
tWLOtWLMRD
tWLDQSEN
tWLO
tWLO
tWLO
Notes: 1. MRS: Load MR1 to enter write leveling mode.2. NOP: NOP or DES.3. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH (MIN) and tDQSL
(MIN) as defined for regular writes. The maximum pulse width is system-dependent.4. Differential DQS is the differential data strobe (DQS, DQS#). Timing reference points are
the zero crossings. The solid line represents DQS; the dotted line represents DQS#.5. DRAM drives leveling feedback on a prime DQ (DQ0 for x4 and x8). The remaining DQ
are driven LOW and remain in this state throughout the leveling procedure.
1Gb: x4, x8, x16 DDR3 SDRAMWrite Leveling
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Notes:
1. MRS:LoadMR1toenterwritelevelingmode.
2. NOP:NOPorDES.
3. DQS,DQS#needstofulfillminimumpulsewidthrequirementstDQSH(MIN)andtDQSL(MIN)asdefinedforregularwrites.Themaximumpulsewidthissystem-dependent.
4. DifferentialDQSisthedifferentialdatastrobe(DQS,DQS#).Timingreferencepointsarethezerocrossings.ThesolidlinerepresentsDQS;thedottedlinerepresentsDQS#.
5. DRAMdriveslevelingfeedbackonaprimeDQ(DQ0forx4andx8).TheremainingDQaredrivenLOWandremaininthisstatethroughoutthelevelingprocedure.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
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1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Write Leveling Mode Exit Procedure
AftertheDRAMareleveled,theymustexitfromwritelevelingmodebeforethenormalmodecanbeused.Figure16depictsageneralprocedureforexitingwrite levelingmode.Afterthelast risingDQS (capturing a1 at T0), thememory controllershouldstopdriving theDQSsignalsafter tWLO (MAX)delayplusenoughdelaytoenablethememorycontrollertocapturetheapplicableprimeDQstate(at~Tb0).TheDQballsbecomeundefinedwhenDQSnolongerremainsLOW,andtheyremainundefineduntil tMODafter theMRScommand (atTe1).The
ODT input should be de-asserted LOW such that ODTLoff(MIN)expiresafter theDQS isno longerdrivingLOW.WhenODT LOW satisfies tIS, ODT must be kept LOW (at ~Tb0)until theDRAMisreadyforeitheranotherranktobe leveledoruntilthenormalmodecanbeused.AfterDQSterminationis switched off,write levelmode should be disabled via theMRScommand(atTc2).After tMODissatisfied(atTe1),anyvalidcommandmayberegisteredbytheDRAM.SomeMRScommandsmaybeissuedaftertMRD(atTd1).
Figure 16: Write Leveling Exit Procedure
Write Leveling Mode Exit Procedure
After the DRAM are leveled, they must exit from write leveling mode before the normalmode can be used. Figure 49 depicts a general procedure for exiting write levelingmode. After the last rising DQS (capturing a 1 at T0), the memory controller should stopdriving the DQS signals after tWLO (MAX) delay plus enough delay to enable the memo-ry controller to capture the applicable prime DQ state (at ~Tb0). The DQ balls becomeundefined when DQS no longer remains LOW, and they remain undefined until tMODafter the MRS command (at Te1).
The ODT input should be de-asserted LOW such that ODTLoff (MIN) expires after theDQS is no longer driving LOW. When ODT LOW satisfies tIS, ODT must be kept LOW (at~Tb0) until the DRAM is ready for either another rank to be leveled or until the normalmode can be used. After DQS termination is switched off, write level mode should bedisabled via the MRS command (at Tc2). After tMOD is satisfied (at Te1), any valid com-mand may be registered by the DRAM. Some MRS commands may be issued after tMRD(at Td1).
Figure 49: Write Leveling Exit Procedure
NOP
CK
T0 T1 T2 Ta0 Tb0 Tc0 Tc1 Tc2 Td0 Td1 Te0 Te1CK#
Command
ODT
RTT(DQ)
NOPNOP NOP NOP NOP NOP MRS NOP NOP
Address MR1
Valid Valid
Valid Valid
Don’t CareTransitioning
RTT DQS, RTT DQS# RTT,nom
Undefined Driving Mode
tAOF (MAX)
tMRD
Indicates breakin time scale
DQS, DQS#
CK = 1DQ
tIS
tAOF (MIN)
tMOD
tWLO + tWLOE
ODTLoff
Note: 1. The DQ result, = 1, between Ta0 and Tc0, is a result of the DQS, DQS# signals capturingCK HIGH just after the T0 state.
1Gb: x4, x8, x16 DDR3 SDRAMWrite Leveling
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Note:
1. TheDQresult,=1,betweenTa0andTc0,isaresultoftheDQS,DQS#signalscapturingCKHIGHjustaftertheT0state.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Initialization
The following sequence is required for power-up andinitialization,asshowninFigure17(page51):
1. Applypower.RESET#isrecommendedtobebelow0.2×VDDQduringpowerramptoensuretheoutputsremaindisabled(High-Z)andODToff(RTTisalsoHigh-Z).Allotherinputs,includingODT,maybeundefined.
Duringpower-up,eitherofthefollowingconditionsmayexistandmustbemet:
• ConditionA:
� VDDandVDDQaredrivenfromasingle-powerconverteroutputandarerampedwithamaximumdeltavoltagebetweenthemofΔV≤300mV.Slopereversalofanypowersupplysignalisallowed.ThevoltagelevelsonallballsotherthanVDD,VDDQ,VSS,VSSQmustbelessthanorequaltoVDDQandVDDononeside,andmustbegreaterthanorequaltoVSSQandVSSontheotherside.
� BothVDDandVDDQpowersuppliesramptoVDD,minandVDDQ,minwithintVDDPR=200ms.
� VREFDQtracksVDD×0.5,VREFCAtracksVDD×0.5.
� VTTislimitedto0.95Vwhenthepowerrampiscompleteandisnotapplieddirectlytothedevice;however,tVTDshouldbegreaterthanorequalto0toavoiddevicelatchup.
• ConditionB:
� VDDmaybeappliedbeforeoratthesametimeasVDDQ.
� VDDQmaybeappliedbeforeoratthesametimeasVTT,VREFDQ,andVREFCA.
� Noslopereversalsareallowedinthepowersupplyrampforthiscondition.
2. Untilstablepower,maintainRESET#LOWtoensuretheoutputsremaindisabled(High-Z).Afterthepowerisstable,RESET#mustbeLOWforatleast200μstobegintheinitializationprocess.ODTwillremainintheHigh-ZstatewhileRESET#isLOWanduntilCKEisregisteredHIGH.
3. CKEmustbeLOW10nspriortoRESET#transitioningHIGH.
4. AfterRESET#transitionsHIGH,wait500μs(minusoneclock)withCKELOW.
5. AftertheCKELOWtime,CKEmaybebroughtHIGH(synchronously)andonlyNOPorDEScommandsmaybeissued.Theclockmustbepresentandvalidforatleast10ns(andaminimumoffiveclocks)andODTmustbedrivenLOWatleasttISpriortoCKEbeingregisteredHIGH.WhenCKEisregisteredHIGH,itmustbecontinuouslyregisteredHIGHuntilthefullinitializationprocessiscomplete.
6. AfterCKEisregisteredHIGHandaftertXPRhasbeensatisfied,MRScommandsmaybeissued.IssueanMRS(LOADMODE)commandtoMR2withtheapplicablesettings(provideLOWtoBA2andBA0andHIGHtoBA1).
7. IssueanMRScommandtoMR3withtheapplicablesettings.
8. IssueanMRScommandtoMR1withtheapplicablesettings,includingenablingtheDLLandconfiguringODT.
9. IssueanMRScommandtoMR0withtheapplicablesettings,includingaDLLRESETcommand.tDLLK(512)cyclesofclockinputarerequiredtolocktheDLL.
10. IssueaZQCLcommandtocalibrateRTTandRONvaluesfortheprocessvoltagetemperature(PVT).Priortonormaloperation,tZQinitmustbesatisfied.
11. WhentDLLKandtZQinithavebeensatisfied,theDDR3SDRAMwillbereadyfornormaloperation.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
51
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Figure 50: Initialization Sequence
CKE
RTT
BA[2:0]
All voltagesupplies validand stable
T = 200μs (MIN)
DM
DQS
Address
A10
CK
CK#
tCL
Command NOP
T0 Ta0
Don’t Care
tCL
tIS
tCK
ODT
DQ
Tb0
tDLLK
MR1 withDLL enable
MR0 withDLL reset
tMRD tMOD
MRSMRS
BA0 = HBA1 = LBA2 = L
BA0 = LBA1 = LBA2 = L
Code Code
Code Code
Valid
Valid
Valid
Valid
Normaloperation
MR2 MR3
tMRD tMRD
MRSMRS
BA0 = LBA1 = HBA2 = L
BA0 = HBA1 = HBA2 = L
Code Code
Code Code
Tc0 Td0
VTT
VREF
VDDQ
VDD
RESET#
T = 500μs (MIN)
tCKSRX
Stable andvalid clock
Valid
Power-upramp
T (MAX) = 200ms
DRAM ready for external commands
T1
tZQinit
ZQ calibration
A10 = H
ZQCL
tIS
See power-upconditions
in the initialization
sequence text, set up 1
tXPR
Valid
tIOZ = 20ns
Indicates breakin time scale
T (MIN) = 10ns
tVTD
1Gb: x4, x8, x16 DDR3 SDRAMInitialization
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Figure 17: Initialization Sequence
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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Form #: CSI-D-685 Document 007
Mode RegistersMode registers (MR0–MR3) are used to define various modes of programmable opera-tions of the DDR3 SDRAM. A mode register is programmed via the mode register set(MRS) command during initialization, and it retains the stored information (except forMR0[8], which is self-clearing) until it is reprogrammed, RESET# goes LOW, the deviceloses power.
Contents of a mode register can be altered by re-executing the MRS command. Even ifthe user wants to modify only a subset of the mode register’s variables, all variablesmust be programmed when the MRS command is issued. Reprogramming the moderegister will not alter the contents of the memory array, provided it is performed cor-rectly.
The MRS command can only be issued (or re-issued) when all banks are idle and in theprecharged state (tRP is satisfied and no data bursts are in progress). After an MRS com-mand has been issued, two parameters must be satisfied: tMRD and tMOD. The control-ler must wait tMRD before initiating any subsequent MRS commands.
Figure 51: MRS to MRS Command Timing (tMRD)
Valid Valid
MRS1 MRS2NOP NOP NOP NOP
T0 T1 T2 Ta0 Ta1 Ta2CK#
CK
Command
Address
CKE3
Don’t CareIndicates breakin time scale
tMRD
Notes: 1. Prior to issuing the MRS command, all banks must be idle and precharged, tRP (MIN)must be satisfied, and no data bursts can be in progress.
2. tMRD specifies the MRS to MRS command minimum cycle time.3. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN) (see Pow-
er-Down Mode (page 183)).4. For a CAS latency change, tXPDLL timing must be met before any non-MRS command.
The controller must also wait tMOD before initiating any non-MRS commands (exclud-ing NOP and DES). The DRAM requires tMOD in order to update the requested features,with the exception of DLL RESET, which requires additional time. Until tMOD has beensatisfied, the updated features are to be assumed unavailable.
1Gb: x4, x8, x16 DDR3 SDRAMMode Registers
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2006 Micron Technology, Inc. All rights reserved.
Mode Registers
Mode registers (MR0–MR3) are used to define variousmodes of programmable operations of the DDR3 SDRAM.A mode register is programmed via the mode register set(MRS)commandduringinitialization,anditretainsthestoredinformation(exceptforMR0[8],whichisself-clearing)untilitisreprogrammed,RESET#goesLOW,thedevicelosespower.
Contentsof amode register canbealteredby re-executingthe MRS command. Even if the user wants to modify onlya subset of the mode register’s variables, all variablesmust be programmed when the MRS command is issued.Reprogrammingthemoderegisterwillnotalterthecontentsofthememoryarray,provideditisperformedcorrectly.
TheMRScommandcanonlybe issued (or re-issued)whenallbanksareidleandintheprechargedstate(tRPissatisfiedandnodataburstsareinprogress).AfteranMRScommandhas been issued, two parameters must be satisfied: tMRDandtMOD.ThecontrollermustwaittMRDbeforeinitiatinganysubsequentMRScommands.
Figure 18: MRS to MRS Command Timing (tMRD)
Notes:
1. PriortoissuingtheMRScommand,allbanksmustbeidleandprecharged,tRP(MIN)mustbesatisfied,andnodataburstscanbeinprogress.
2. tMRDspecifiestheMRStoMRScommandminimumcycletime.
3. CKEmustberegisteredHIGHfromtheMRScommanduntiltMRSPDEN(MIN)
4. ForaCASlatencychange,tXPDLLtimingmustbemetbeforeanynon-MRScommand.
ThecontrollermustalsowaittMODbeforeinitiatinganynon-MRScommands(excludingNOPandDES).TheDRAMrequirestMODinordertoupdatetherequestedfeatures,withtheexceptionofDLLRESET,whichrequiresadditionaltime.UntiltMODhasbeensatisfied,theupdatedfeaturesaretobeassumedunavailable.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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Form #: CSI-D-685 Document 007
Figure 19: MRS to nonMRS Command Timing (tMOD)Figure 52: MRS to nonMRS Command Timing (tMOD)
Valid Valid
MRS nonMRSNOP NOP NOP NOP
T0 T1 T2 Ta0 Ta1 Ta2CK#
CK
Command
Address
CKE Valid
Old setting
New setting
Don’t CareIndicates breakin time scale
tMOD
Updating setting
Notes: 1. Prior to issuing the MRS command, all banks must be idle (they must be precharged, tRPmust be satisfied, and no data bursts can be in progress).
2. Prior to Ta2 when tMOD (MIN) is being satisfied, no commands (except NOP/DES) may beissued.
3. If RTT was previously enabled, ODT must be registered LOW at T0 so that ODTL is satis-fied prior to Ta1. ODT must also be registered LOW at each rising CK edge from T0 untiltMODmin is satisfied at Ta2.
4. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN), at whichtime power-down may occur (see Power-Down Mode (page 183)).
Mode Register 0 (MR0)The base register, MR0, is used to define various DDR3 SDRAM modes of operation.These definitions include the selection of a burst length, burst type, CAS latency, oper-ating mode, DLL RESET, write recovery, and precharge power-down mode, as shown inFigure 53 (page 138).
Burst Length
Burst length is defined by MR0[1: 0]. Read and write accesses to the DDR3 SDRAM areburst-oriented, with the burst length being programmable to 4 (chop mode), 8 (fixed),or selectable using A12 during a READ/WRITE command (on-the-fly). The burst lengthdetermines the maximum number of column locations that can be accessed for a givenREAD or WRITE command. When MR0[1:0] is set to 01 during a READ/WRITE com-mand, if A12 = 0, then BC4 (chop) mode is selected. If A12 = 1, then BL8 mode is selec-ted. Specific timing diagrams, and turnaround between READ/WRITE, are shown in theREAD/WRITE sections of this document.
When a READ or WRITE command is issued, a block of columns equal to the burstlength is effectively selected. All accesses for that burst take place within this block,meaning that the burst will wrap within the block if a boundary is reached. The block isuniquely selected by A[i:2] when the burst length is set to 4 and by A[i:3] when the burstlength is set to 8 (where Ai is the most significant column address bit for a given config-uration). The remaining (least significant) address bit(s) is (are) used to select the start-
1Gb: x4, x8, x16 DDR3 SDRAMMode Register 0 (MR0)
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Notes:
1. PriortoissuingtheMRScommand,allbanksmustbeidle(theymustbeprecharged,tRPmustbesatisfied,andnodataburstscanbeinprogress).
2. PriortoTa2whentMOD(MIN)isbeingsatisfied,nocommands(exceptNOP/DES)maybeissued.
3. IfRTTwaspreviouslyenabled,ODTmustberegisteredLOW
Mode Register 0 (MR0)
Thebaseregister,MR0,isusedtodefinevariousDDR3SDRAMmodesofoperation.Thesedefinitionsincludetheselectionofaburstlength,bursttype,CASlatency,operatingmode,DLLRESET,writerecovery,andprechargepower-downmode,asshowninFigure20(page54).
Burst Length
BurstlengthisdefinedbyMR0[1:0].ReadandwriteaccessestotheDDR3SDRAMareburst-oriented,withtheburstlengthbeingprogrammableto4(chopmode),8(fixed),orselectableusingA12duringaREAD/WRITEcommand(on-the-fly).Theburst length determines the maximum number of columnlocations thatcanbeaccessed foragivenREADorWRITEcommand.WhenMR0[1:0]issetto01duringaREAD/WRITE
command, ifA12=0, thenBC4 (chop)mode isselected. IfA12=1,thenBL8modeisselected.Specifictimingdiagrams,and turnaround between READ/WRITE, are shown in theREAD/WRITEsectionsofthisdocument.
WhenaREADorWRITEcommandisissued,ablockofcolumnsequaltotheburstlengthiseffectivelyselected.Allaccessesforthatbursttakeplacewithinthisblock,meaningthattheburstwillwrapwithintheblockifaboundaryisreached.TheblockisuniquelyselectedbyA[i:2]whentheburstlengthissetto4andbyA[i:3]whentheburstlengthissetto8(whereAiisthemostsignificantcolumnaddressbit foragivenconfiguration).Theremaining(leastsignificant)addressbit(s)is(are)usedtoselectthestartinglocationwithintheblock.TheprogrammedburstlengthappliestobothREADandWRITEbursts.
atT0sothatODTLissatisfiedpriortoTa1.ODTmustalsoberegisteredLOWateachrisingCKedgefromT0untiltMODminissatisfiedatTa2.
4. CKEmustberegisteredHIGHfromtheMRScommanduntiltMRSPDEN(MIN),atwhichtimepower-downmayoccur(seePower-DownMode(page94)).
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ing location within the block. The programmed burst length applies to both READ andWRITE bursts.
Figure 53: Mode Register 0 (MR0) Definitions
BLCAS# latency CLBTPD
A9 A7 A6 A5 A4 A3A8 A2 A1 A0
Mode register 0 (MR0)
Address bus
9 7 6 5 4 38 2 1 0
A10A12 A11BA0BA1
10111213
M3
0
1
READ Burst Type
Sequential (nibble)
Interleaved
CAS Latency
Reserved
5
6
7
8
9
10
11
12
13
14
M2
0
0
0
0
0
0
0
0
1
1
1
M4
0
1
0
1
0
1
0
1
0
1
0
M5
0
0
1
1
0
0
1
1
0
0
1
M6
0
0
0
0
1
1
1
1
0
0
0
15DLL
Write Recovery
16
5
6
7
8
10
12
14
WR00
M12
0
1
Precharge PD
DLL off (slow exit)
DLL on (fast exit)
BA2
16
01
Burst Length
Fixed BL8
4 or 8 (on-the-fly via A12)
Fixed BC4 (chop)
Reserved
M0
0
1
0
1
M1
0
0
1
1
M9
0
1
0
1
0
1
0
1
M10
0
0
1
1
0
0
1
1
M11
0
0
0
0
1
1
1
1
M14
0
1
0
1
M15
0
0
1
1
Mode Register
Mode register 0 (MR0)
Mode register 1 (MR1)
Mode register 2 (MR2)
Mode register 3 (MR3)
A13
14
01 01
M8
0
1
DLL Reset
No
Yes
Note: 1. MR0[16, 13, 7, 2] are reserved for future use and must be programmed to 0.
Burst Type
Accesses within a given burst may be programmed to either a sequential or an inter-leaved order. The burst type is selected via MR0[3] (see Figure 53 (page 138)). The order-ing of accesses within a burst is determined by the burst length, the burst type, and thestarting column address. DDR3 only supports 4-bit burst chop and 8-bit burst accessmodes. Full interleave address ordering is supported for READs, while WRITEs are re-stricted to nibble (BC4) or word (BL8) boundaries.
1Gb: x4, x8, x16 DDR3 SDRAMMode Register 0 (MR0)
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Figure 20: Mode Register 0 (MR0) Definitions
Note:
1. MR0[16,13,7,2]arereservedforfutureuseandmustbeprogrammedto0.
Burst Type
Accesseswithinagivenburstmaybeprogrammedtoeitherasequentialoraninterleavedorder.ThebursttypeisselectedviaMR0[3](seeFigure20).Theorderingofaccesseswithinaburstisdeterminedbytheburstlength,thebursttype,andthestartingcolumnaddress.DDR3onlysupports4-bitburstchopand8-bitburstaccessmodes.FullinterleaveaddressorderingissupportedforREADs,whileWRITEsarerestrictedtonibble(BC4)orword(BL8)boundaries.
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Form #: CSI-D-685 Document 007
Table 26: Burst Order
Burst Length READ/ WRITEStarting Column
Address (A[2, 1, 0])Burst Type =
Sequential (Decimal)Burst Type =
Interleaved (Decimal)Notes
4 chop
READ
0 0 0 0, 1, 2, 3, Z, Z, Z, Z 0, 1, 2, 3, Z, Z, Z, Z 1, 2
0 0 1 1, 2, 3, 0, Z, Z, Z, Z 1, 0, 3, 2, Z, Z, Z, Z 1, 2
0 1 0 2, 3, 0, 1, Z, Z, Z, Z 2, 3, 0, 1, Z, Z, Z, Z 1, 2
0 1 1 3, 0, 1, 2, Z, Z, Z, Z 3, 2, 1, 0, Z, Z, Z, Z 1, 2
1 0 0 4, 5, 6, 7, Z, Z, Z, Z 4, 5, 6, 7, Z, Z, Z, Z 1, 2
1 0 1 5, 6, 7, 4, Z, Z, Z, Z 5, 4, 7, 6, Z, Z, Z, Z 1, 2
1 1 0 6, 7, 4, 5, Z, Z, Z, Z 6, 7, 4, 5, Z, Z, Z, Z 1, 2
1 1 1 7, 4, 5, 6, Z, Z, Z, Z 7, 6, 5, 4, Z, Z, Z, Z 1, 2
WRITE0 V V 0, 1, 2, 3, X, X, X, X 0, 1, 2, 3, X, X, X, X 1, 3, 4
1 V V 4, 5, 6, 7, X, X, X, X 4, 5, 6, 7, X, X, X, X 1, 3, 4
8READ
0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 1
0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 1
0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 1
0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1
1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1
1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1
1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1
1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 1
WRITE V V V 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 1, 3
Notes:
1. InternalREADandWRITEoperationsstartatthesamepointintimeforBC4astheydoforBL8.
2. Z=Dataandstrobeoutputdriversareintri-state.
3. V=Avalidlogiclevel(0or1),buttherespectiveinputbufferignoreslevel-oninputpins.
4. X=“Don’tCare.”
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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DLL RESET
DLLRESET isdefinedbyMR0[8] (seeFigure20 (page54)).ProgrammingMR0[8]to1activatestheDLLRESETfunction.MR0[8]isself-clearing,meaningitreturnstoavalueof0aftertheDLLRESETfunctionhasbeeninitiated.
Anytime the DLL RESET function is initiated, CKEmust beHIGHandtheclockheldstablefor512(tDLLK)clockcyclesbeforeaREADcommandcanbeissued.Thisistoallowtimefor the internal clock to be synchronized with the externalclock.Failingtowaitforsynchronizationtooccurmayresultininvalidoutputtimingspecifications,suchastDQSCKtimings.
Write Recovery
WRITE recovery time is defined by MR0[11:9] (see Figure20 (page 54)). Write recovery values of 5, 6, 7, 8, 10, or12 may be used by programming MR0[11:9]. The user isrequired to program the correct value ofwrite recovery andiscalculatedbydividingtWR(ns)bytCK(ns)androundingupanonintegervaluetothenextinteger:WR(cycles)=roundup(tWR[ns]/tCK[ns]).
Precharge Power-Down (Precharge PD)
The precharge PD bit applies only when precharge power-downmodeisbeingused.WhenMR0[12]issetto0,theDLLisoffduringprechargepower-downprovidingalowerstandbycurrent mode; however, tXPDLL must be satisfied whenexiting.WhenMR0[12] isset to1, theDLLcontinues to runduringprechargepower-downmodetoenableafasterexitofprechargepower-downmode;however,tXPmustbesatisfiedwhenexiting(seePower-DownMode(page94)).
CAS Latency (CL)
TheCLisdefinedbyMR0[6:4],asshowninFigure20(page54). CAS latency is the delay, in clock cycles, between theinternalREADcommandandtheavailabilityof thefirstbitofoutputdata.TheCLcanbesetto5,6,7,8,9,or10.DDR3SDRAMdonotsupporthalf-clocklatencies.
Examples of CL = 6 and CL = 8 are shown below. If aninternalREADcommandisregisteredatclockedgen,andtheCAS latency ismclocks, thedatawillbeavailablenominallycoincidentwithclockedgen+m.onpagethroughTable18(page 22) indicate the CLs supported at various operatingfrequencies.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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quired to program the correct value of write recovery and is calculated by dividing tWR(ns) by tCK (ns) and rounding up a noninteger value to the next integer: WR (cycles) =roundup (tWR [ns]/tCK [ns]).
Precharge Power-Down (Precharge PD)
The precharge PD bit applies only when precharge power-down mode is being used.When MR0[12] is set to 0, the DLL is off during precharge power-down providing a low-er standby current mode; however, tXPDLL must be satisfied when exiting. WhenMR0[12] is set to 1, the DLL continues to run during precharge power-down mode toenable a faster exit of precharge power-down mode; however, tXP must be satisfiedwhen exiting (see Power-Down Mode (page 183)).
CAS Latency (CL)
The CL is defined by MR0[6:4], as shown in Figure 53 (page 138). CAS latency is the de-lay, in clock cycles, between the internal READ command and the availability of the firstbit of output data. The CL can be set to 5, 6, 7, 8, 9, or 10. DDR3 SDRAM do not supporthalf-clock latencies.
Examples of CL = 6 and CL = 8 are shown below. If an internal READ command is regis-tered at clock edge n, and the CAS latency is m clocks, the data will be available nomi-nally coincident with clock edge n + m. on page through Table 52 (page 75) indicate theCLs supported at various operating frequencies.
Figure 54: READ Latency
READ NOP NOP NOP NOP NOP NOPNOP
CK
CK#
Command
DQ
DQS, DQS#
DQS, DQS#
T0 T1 T2 T3 T4 T5 T6 T7 T8
Don’t Care
CK
CK#
Command
DQ
READ NOP NOP NOP NOP NOP NOPNOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
DI n + 3
DI n + 1
DI n + 2
DI n + 4
DIn
DIn
NOP
NOP
AL = 0, CL = 8
AL = 0, CL = 6
Transitioning Data
Notes: 1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible.2. Shown with nominal tDQSCK and nominal tDSDQ.
1Gb: x4, x8, x16 DDR3 SDRAMMode Register 0 (MR0)
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Figure 21: READ Latency
Notes:
1. Forillustrationpurposes,onlyCL=6andCL=8areshown.OtherCLvaluesarepossible.
2. ShownwithnominaltDQSCKandnominaltDSDQ.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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Mode Register 1 (MR1)
Themode register1 (MR1)controlsadditional functionsandfeatures not available in the other mode registers: Q OFF(OUTPUT DISABLE), TDQS (for the x8 configuration only),DLL ENABLE/DLL DISABLE, RTT,nom value (ODT), WRITELEVELING, POSTED CAS ADDITIVE latency, and OUTPUTDRIVESTRENGTH.ThesefunctionsarecontrolledviathebitsshowninFigure22.TheMR1registerisprogrammedviatheMRS command and retains the stored information until it isreprogrammed, untilRESET#goesLOW,or until thedevice
loses power. Reprogramming theMR1 registerwill not alterthe contents of thememory array, provided it is performedcorrectly.
The MR1 register must be loaded when all banks are idleandnoburstsareinprogress.ThecontrollermustsatisfythespecifiedtimingparameterstMRDandtMODbeforeinitiatingasubsequentoperation.
Figure 22: Mode Register 1 (MR1) Definition
Mode Register 1 (MR1)The mode register 1 (MR1) controls additional functions and features not available inthe other mode registers: Q OFF (OUTPUT DISABLE), TDQS (for the x8 configurationonly), DLL ENABLE/DLL DISABLE, RTT,nom value (ODT), WRITE LEVELING, POSTEDCAS ADDITIVE latency, and OUTPUT DRIVE STRENGTH. These functions are control-led via the bits shown in Figure 55 (page 141). The MR1 register is programmed via theMRS command and retains the stored information until it is reprogrammed, until RE-SET# goes LOW, or until the device loses power. Reprogramming the MR1 register willnot alter the contents of the memory array, provided it is performed correctly.
The MR1 register must be loaded when all banks are idle and no bursts are in progress.The controller must satisfy the specified timing parameters tMRD and tMOD before ini-tiating a subsequent operation.
Figure 55: Mode Register 1 (MR1) Definition
AL RTTQ Off
A9 A7 A6 A5 A4 A3A8 A2 A1 A0
Mode register 1 (MR1)
Address bus
9 7 6 5 4 38 2 1 0
A10A12 A11BA0BA1
10111213
M0
0
1
DLL Enable
Enable (normal)
Disable
M5
0
0
1
1
Output Drive Strength
RZQ/6 (40 [NOM])
RZQ/7 (34 [NOM])
Reserved
Reserved
14
WL10 ODS DLLRTTTDQS
M12
0
1
Q Off
Enabled
Disabled
BA2
15
01
M7
0
1
Write Leveling
Disable (normal)
Enable
Additive Latency (AL)
Disabled (AL = 0)
AL = CL - 1
AL = CL - 2
Reserved
M3
0
1
0
1
M4
0
0
1
1
RTT ODS
M1
0
1
0
1
A13
16
01
M11
0
1
TDQS
Disabled
Enabled
01 01
RTT,nom (ODT) 2
Non-Writes
RTT,nom disabled
RZQ/4 (60 [NOM])
RZQ/2 (120 [NOM])
RZQ/6 (40 [NOM])
RZQ/12 (20 [NOM])
RZQ/8 (30 [NOM])
Reserved
Reserved
RTT,nom (ODT) 3
Writes
RTT,nom disabled
RZQ/4 (60 [NOM])
RZQ/2 (120 [NOM])
RZQ/6 (40 [NOM])
n/a
n/a
Reserved
Reserved
M2
0
1
0
1
0
1
0
1
M6
0
0
1
1
0
0
1
1
M9
0
0
0
0
1
1
1
1
Mode Register
Mode register set 0 (MR0)
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
M14
0
1
0
1
M15
0
0
1
1
Notes: 1. MR1[16, 13, 10, 8] are reserved for future use and must be programmed to 0.2. During write leveling, if MR1[7] and MR1[12] are 1, then all RTT,nom values are available
for use.3. During write leveling, if MR1[7] is a 1, but MR1[12] is a 0, then only RTT,nom write values
are available for use.
DLL Enable/DLL Disable
The DLL may be enabled or disabled by programming MR1[0] during the LOAD MODEcommand, as shown in Figure 55 (page 141). The DLL must be enabled for normal oper-ation. DLL enable is required during power-up initialization and upon returning to nor-mal operation after having disabled the DLL for the purpose of debugging or evalua-tion. Enabling the DLL should always be followed by resetting the DLL using the appro-priate LOAD MODE command.
1Gb: x4, x8, x16 DDR3 SDRAMMode Register 1 (MR1)
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Notes:
1. MR1[16,13,10,8]arereservedforfutureuseandmustbeprogrammedto0.
2. Duringwriteleveling,ifMR1[7]andMR1[12]are1,thenallRTT,nomvaluesareavailableforuse.
3. 3.Duringwriteleveling,ifMR1[7]isa1,butMR1[12]isa0,thenonlyRTT,nomwritevaluesareavailableforuse.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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DLL Enable/DLL Disable
TheDLLmaybeenabledordisabledbyprogrammingMR1[0]during the LOADMODE command, as shown in Figure 22(page 58). The DLLmust be enabled for normal operation.DLLenableisrequiredduringpower-upinitializationanduponreturning to normal operation after having disabled the DLLforthepurposeofdebuggingorevaluation.EnablingtheDLLshould always be followed by resetting the DLL using theappropriateLOADMODEcommand.
If theDLL isenabledprior toenteringself refreshmode, theDLLisautomaticallydisabledwhenenteringSELFREFRESHoperationand isautomaticallyreenabledandresetuponexitofSELFREFRESHoperation. If theDLL isdisabledprior toentering self refresh mode, the DLL remains disabled evenupon exit of SELF REFRESH operation until it is reenabledandreset.
TheDRAMisnottestedtocheck—nordoesMicronwarrantcompliancewith—normalmodetimingsorfunctionalitywhentheDLLisdisabled.AnattempthasbeenmadetohavetheDRAMoperateinthenormalmodewherereasonablypossiblewhen the DLL has been disabled; however, by industrystandard,afewknownexceptionsaredefined:
• ODTisnotallowedtobeused
• Theoutputdataisnolongeredge-alignedtotheclock
• CLandCWLcanonlybesixclocks
When theDLL is disabled, timing and functionality can varyfrom the normal operation specifications when the DLL isenabled (see DLL Disable Mode (page 39)). Disabling theDLLalsoimpliestheneedtochangetheclockfrequency(seeInputClockFrequencyChange(page43)).
Output Drive Strength
TheDDR3SDRAMusesaprogrammableimpedanceoutputbuffer.Thedrivestrengthmoderegistersetting isdefinedbyMR1[5, 1]. RZQ/7 (34Ω [NOM]) is the primary output driverimpedancesettingforDDR3SDRAMdevices.Tocalibratetheoutputdriver impedance,anexternalprecisionresistor(RZQ)isconnectedbetweentheZQballandVSSQ.Thevalueoftheresistormustbe240Ω±1%.
The output impedance is set during initialization. Additionalimpedancecalibrationupdatesdonotaffectdeviceoperation,andalldatasheettimingsandcurrentspecificationsaremetduringanupdate.
Tomeetthe34Ωspecification,theoutputdrivestrengthmustbesetto34Ωduringinitialization.Toobtainacalibratedoutputdriverimpedanceafterpower-up,theDDR3SDRAMneedsacalibrationcommandthatispartoftheinitializationandresetprocedure.
OUTPUT ENABLE/DISABLE
The OUTPUT ENABLE function is defined by MR1[12], asshown inFigure22(page58).Whenenabled(MR1[12]=0),alloutputs(DQ,DQS,DQS#)functionwheninthenormalmodeofoperation.Whendisabled(MR1[12]=1),allDDR3SDRAMoutputs(DQandDQS,DQS#)aretri-stated.Theoutputdisablefeature is intended to be used during IDD characterizationof the READ current and during tDQSS margining(writeleveling)only.
TDQS Enable
Terminationdatastrobe (TDQS) isa featureof thex8DDR3SDRAM configuration that provides termination resistance(RTT)andmaybeusefulinsomesystemconfigurations.TDQSisnotsupportedinx4orx16configurations.Whenenabledviathemoderegister(MR1[11]),theRTTthatisappliedtoDQSandDQS#isalsoappliedtoTDQSandTDQS#.IncontrasttotheRDQSfunctionofDDR2SDRAM,DDR3’sTDQSprovidestheterminationresistanceRTTonly.TheOUTPUTDATASTROBEfunctionofRDQS isnotprovidedbyTDQS; thus,RONdoesnotapplytoTDQSandTDQS#.TheTDQSandDMfunctionssharethesameball.WhentheTDQSfunctionisenabledviathemoderegister,theDMfunctionisnotsupported.WhentheTDQSfunction isdisabled, theDMfunction isprovided,andtheTDQS#ballisnotused.TheTDQSfunctionisavailableinthex8DDR3SDRAMconfigurationonlyandmustbedisabledviathemoderegisterforthex4andx16configurations.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
60
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
On-Die Termination
ODTresistanceRTT,nomisdefinedbyMR1[9,6,2](seeFigure22 (page58)). TheRTT termination valueapplies to theDQ,DM,DQS,DQS#,andTDQS,TDQS#balls.DDR3supportsmultipleRTTterminationvaluesbasedonRZQ/nwherencanbe2,4,6,8,or12andRZQis240Ω.
UnlikeDDR2,DDR3ODTmustbeturnedoffpriortoreadingdataoutandmust remainoffduringaREADburst.RTT,nomtermination is allowedany timeafter theDRAM is initialized,calibrated,andnotperformingreadaccess,orwhenitisnotinselfrefreshmode.Additionally,writeaccesseswithdynamicODT enabled (RTT(WR)) temporarily replaces RTT,nom withRTT(WR).
Theactualeffectivetermination,RTT(EFF),maybedifferentfromthe RTT targeted due to nonlinearity of the termination. ForRTT(EFF)valuesandcalculations(seeOn-DieTermination(ODT)(page103)).
TheODTfeatureisdesignedtoimprovesignalintegrityofthememorychannelbyenablingtheDDR3SDRAMcontrollertoindependentlyturnon/offODTforanyoralldevices.TheODTinputcontrolpinisusedtodeterminewhenRTT isturnedon(ODTLon)andoff(ODTLoff),assumingODThasbeenenabledviaMR1[9,6,2].
Timings for ODT are detailed in On-Die Termination (ODT)(page103).
WRITE LEVELING
The WRITE LEVELING function is enabled by MR1[7], asshown in Figure22 (page58).Write leveling is used (duringinitialization) to deskew theDQS strobe to clock offset as aresult of fly-by topology designs. For better signal integrity,DDR3SDRAMmemorymodulesadoptedfly-bytopologyforthecommands,addresses,controlsignals,andclocks.
Thefly-bytopologybenefitsfromareducednumberofstubsand their lengths. However, fly-by topology induces flighttimeskewsbetween theclockandDQSstrobe (andDQ)ateachDRAMontheDIMM.Controllerswillhaveadifficulttimemaintaining tDQSS, tDSS, and tDSH specifications withoutsupportingwritelevelinginsystemswhichusefly-bytopology-
basedmodules.Write leveling timing anddetailed operationinformationisprovidedinWriteLeveling(page45).
POSTED CAS ADDITIVE Latency
POSTEDCASADDITIVElatency(AL)issupportedtomakethecommandanddatabusefficientforsustainablebandwidthsinDDR3SDRAM.MR1[4,3]definethevalueofAL,asshowninFigure 23 (page 61).MR1[4, 3] enable the user to programtheDDR3SDRAMwithAL=0,CL-1,orCL-2.
Withthisfeature,theDDR3SDRAMenablesaREADorWRITEcommandtobeissuedaftertheACTIVATEcommandforthatbank prior to tRCD (MIN). The only restriction is ACTIVATEto READ or WRITE + AL ≥ tRCD (MIN) must be satisfied.Assuming tRCD (MIN) = CL, a typical application using thisfeaturesetsAL=CL-1tCK=tRCD(MIN)-1tCK.TheREADorWRITEcommandisheldforthetimeoftheALbeforeitisreleasedinternallytotheDDR3SDRAMdevice.READlatency(RL)iscontrolledbythesumoftheALandCASlatency(CL),RL=AL+CL.WRITElatency(WL)isthesumofCASWRITElatencyandAL,WL=AL+CWL(seeModeRegister2(MR2)on page 61). Examples of READ and WRITE latencies areshowninFigure23(page61)andFigure25(page62).
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
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1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Figure 57: Mode Register 2 (MR2) Definition
M14
0
1
0
1
M15
0
0
1
1
Mode Register
Mode register set 0 (MR0)
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
A9 A7 A6 A5 A4 A3A8 A2 A1 A0
Mode register 2 (MR2)
Address bus
9 7 6 5 4 38 2 1 0
A10A12 A11BA0BA1
101112131415
1 CWL010
BA2
ASR
16
01
A13
01 01 01 01 0101 SRTRTT(WR)
M6
0
1
Auto Self Refresh(Optional)
Disabled: Manual
Enabled: Automatic
M7
0
1
Self Refresh Temperature
Normal (0°C to 85°C)
Extended (0°C to 95°C)
CAS Write Latency (CWL)
5 CK (tCK 2.5ns)
6 CK (2.5ns tCK 1.875ns)
7 CK (1.875ns tCK 1.5ns)
8 CK (1.5ns tCK 1.25ns)
9 CK (1.25ns tCK 1.07ns)
10 CK (1.071ns tCK 0.938ns)
Reserved
Reserved
M3
0
1
0
1
0
1
0
1
M4
0
0
1
1
0
0
1
1
M5
0
0
0
0
1
1
1
1M9
0
1
0
1
M10
0
0
1
1
Dynamic ODT(RTT(WR) )
RTT(WR) disabled
RZQ/4
RZQ/2
Reserved
Note: 1. MR2[16, 13:11, 8, and 2:0] are reserved for future use and must all be programmed to 0.
CAS Write Latency (CWL)
CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of theinternal write to the latching of the first data in. CWL must be correctly set to the corre-sponding operating clock frequency (see Figure 57 (page 145)). The overall WRITE la-tency (WL) is equal to CWL + AL (Figure 55 (page 141)).
Figure 58: CAS Write Latency
CK
CK#
Command
DQ
DQS, DQS#
ACTIVE n
T0 T1
Don’t Care
NOP NOP
T6 T12
NOPWRITE n
T13
NOP
DI n + 3
DI n + 2
DI n + 1
T14
NOP
DI n
tRCD (MIN)
NOP
AL = 5
T11
Indicates breakin time scale
WL = AL + CWL = 11
Transitioning Data
T2
CWL = 6
AUTO SELF REFRESH (ASR)
Mode register MR2[6] is used to disable/enable the ASR function. When ASR is disabled,the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (some-times referred to as 1x refresh rate). In the disabled mode, ASR requires the user to en-
1Gb: x4, x8, x16 DDR3 SDRAMMode Register 2 (MR2)
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Figure 23: READ Latency (AL = 5, CL = 6)
Figure 24: Mode Register 2 (MR2) Definition
tCK. The READ or WRITE command is held for the time of the AL before it is releasedinternally to the DDR3 SDRAM device. READ latency (RL) is controlled by the sum ofthe AL and CAS latency (CL), RL = AL + CL. WRITE latency (WL) is the sum of CASWRITE latency and AL, WL = AL + CWL (see Mode Register 2 (MR2) (page 144)). Exam-ples of READ and WRITE latencies are shown in Figure 56 (page 144) and Figure 58(page 145).
Figure 56: READ Latency (AL = 5, CL = 6)
CK
CK#
Command
DQ
DQS, DQS#
ACTIVE n
T0 T1
Don’t Care
NOP NOP
T6 T12
NOPREAD n
T13
NOP
DOn + 3
DOn + 2
DOn + 1
RL = AL + CL = 11
T14
NOP
DOn
tRCD (MIN)
AL = 5 CL = 6
T11
BC4
Indicates breakin time scale
Transitioning Data
T2
NOP
Mode Register 2 (MR2)The mode register 2 (MR2) controls additional functions and features not available inthe other mode registers. These additional functions are CAS WRITE latency (CWL), AU-TO SELF REFRESH (ASR), SELF REFRESH TEMPERATURE (SRT), and DYNAMIC ODT(RTT(WR)). These functions are controlled via the bits shown in Figure 57. The MR2 isprogrammed via the MRS command and will retain the stored information until it isprogrammed again or until the device loses power. Reprogramming the MR2 registerwill not alter the contents of the memory array, provided it is performed correctly. TheMR2 register must be loaded when all banks are idle and no data bursts are in progress,and the controller must wait the specified time tMRD and tMOD before initiating a sub-sequent operation.
1Gb: x4, x8, x16 DDR3 SDRAMMode Register 2 (MR2)
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Mode Register 2 (MR2)
Themode register2 (MR2)controlsadditional functionsandfeatures not available in the other mode registers. Theseadditional functions are CAS WRITE latency (CWL), AUTOSELF REFRESH (ASR), SELF REFRESH TEMPERATURE(SRT), and DYNAMIC ODT (RTT(WR)). These functions arecontrolledviathebitsshowninFigure24(below).TheMR2isprogrammedviatheMRScommandandwillretainthestoredinformationuntilitis
programmed again or until the device loses power.Reprogramming theMR2 registerwill not alter the contentsof thememory array, provided it is performed correctly. TheMR2registermustbeloadedwhenallbanksareidleandnodataburstsare inprogress,andthecontrollermustwait thespecifiedtimetMRDandtMODbeforeinitiatingasubsequentoperation.
Note:
1. MR2[16,13:11,8,and2:0]arereservedforfutureuseandmustallbeprogrammedto0.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
CAS Write Latency (CWL)
CWLisdefinedbyMR2[5:3]andisthedelay,inclockcycles,from the releasingof the internalwrite to the latchingof thefirstdatain.CWLmustbecorrectlysettothecorrespondingoperating clock frequency (see Figure 24 (page 61)). TheoverallWRITElatency(WL)isequaltoCWL+AL(seeFigure22(page58)).
Figure 57: Mode Register 2 (MR2) Definition
M14
0
1
0
1
M15
0
0
1
1
Mode Register
Mode register set 0 (MR0)
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
A9 A7 A6 A5 A4 A3A8 A2 A1 A0
Mode register 2 (MR2)
Address bus
9 7 6 5 4 38 2 1 0
A10A12 A11BA0BA1
101112131415
1 CWL010
BA2
ASR
16
01
A13
01 01 01 01 0101 SRTRTT(WR)
M6
0
1
Auto Self Refresh(Optional)
Disabled: Manual
Enabled: Automatic
M7
0
1
Self Refresh Temperature
Normal (0°C to 85°C)
Extended (0°C to 95°C)
CAS Write Latency (CWL)
5 CK (tCK 2.5ns)
6 CK (2.5ns tCK 1.875ns)
7 CK (1.875ns tCK 1.5ns)
8 CK (1.5ns tCK 1.25ns)
9 CK (1.25ns tCK 1.07ns)
10 CK (1.071ns tCK 0.938ns)
Reserved
Reserved
M3
0
1
0
1
0
1
0
1
M4
0
0
1
1
0
0
1
1
M5
0
0
0
0
1
1
1
1M9
0
1
0
1
M10
0
0
1
1
Dynamic ODT(RTT(WR) )
RTT(WR) disabled
RZQ/4
RZQ/2
Reserved
Note: 1. MR2[16, 13:11, 8, and 2:0] are reserved for future use and must all be programmed to 0.
CAS Write Latency (CWL)
CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of theinternal write to the latching of the first data in. CWL must be correctly set to the corre-sponding operating clock frequency (see Figure 57 (page 145)). The overall WRITE la-tency (WL) is equal to CWL + AL (Figure 55 (page 141)).
Figure 58: CAS Write Latency
CK
CK#
Command
DQ
DQS, DQS#
ACTIVE n
T0 T1
Don’t Care
NOP NOP
T6 T12
NOPWRITE n
T13
NOP
DI n + 3
DI n + 2
DI n + 1
T14
NOP
DI n
tRCD (MIN)
NOP
AL = 5
T11
Indicates breakin time scale
WL = AL + CWL = 11
Transitioning Data
T2
CWL = 6
AUTO SELF REFRESH (ASR)
Mode register MR2[6] is used to disable/enable the ASR function. When ASR is disabled,the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (some-times referred to as 1x refresh rate). In the disabled mode, ASR requires the user to en-
1Gb: x4, x8, x16 DDR3 SDRAMMode Register 2 (MR2)
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AUTO SELF REFRESH (ASR)
Mode register MR2[6] is used to disable/enable the ASRfunction.WhenASRisdisabled,theselfrefreshmode’srefreshrate is assumed to be at the normal 85°C limit (sometimesreferred to as 1x refresh rate). In the disabled mode, ASRrequires the user to ensure the DRAM never exceeds a TCof85°CwhileinselfrefreshunlesstheuserenablestheSRTfeaturelistedbelowwhentheTCisbetween85°Cand95°C.
EnablingASRassumestheDRAMselfrefreshrateischangedautomatically from 1x to 2x when the case temperatureexceeds 85°C. This enables the user to operate theDRAMbeyond thestandard85°C limitup to theoptionalextendedtemperaturerangeof95°Cwhileinselfrefreshmode.
Thestandardselfrefreshcurrenttestspecifiestestconditionsto normal case temperature (85°C) only, meaning if ASR isenabled,thestandardselfrefreshcurrentspecificationsdonotapply(seeExtendedTemperatureUsage(page93)).
SELF REFRESH TEMPERATURE (SRT)
Mode register MR2[7] is used to disable/enable the SRTfunction.WhenSRTisdisabled,theselfrefreshmode’srefreshrate is assumed to be at the normal 85°C limit (sometimesreferred to as 1x refresh rate). In the disabled mode, SRTrequirestheusertoensuretheDRAMneverexceedsaTCof85°CwhileinselfrefreshmodeunlesstheuserenablesASR.
When SRT is enabled, the DRAM self refresh is changedinternally from1x to2x, regardlessof thecase temperature.This enables the user to operate the DRAM beyond thestandard85°Climituptotheoptionalextendedtemperaturerange of 95°Cwhile in self refreshmode. The standard selfrefresh current test specifies test conditions to normal casetemperature (85°C) only, meaning if SRT is enabled, thestandardself refreshcurrentspecificationsdonotapply (seeExtendedTemperatureUsage(page93)).
Figure 25: CAS Write Latency
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
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1Gb SDRAM-DDR3MYX4DDR364M16JT*
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SRT vs. ASR
Ifthenormalcasetemperaturelimitof85°Cisnotexceeded,thenneitherSRTnorASRisrequired,andbothcanbedisabledthroughout operation.However, if the extended temperatureoptionof95°Cisneeded,theuserisrequiredtoprovidea2xrefresh rate during (manual) refresh and to enable either theSRTortheASRtoensureselfrefreshisperformedatthe2xrate.
SRT forces theDRAMtoswitch the internalself refresh ratefrom1xto2x.Selfrefreshisperformedatthe2xrefreshrateregardlessofthecasetemperature.
ASR automatically switches theDRAM’s internal self refreshratefrom1xto2x.However,whileinselfrefreshmode,ASRenables the refresh rate to automatically adjust between1x to 2x over the supported temperature range. One otherdisadvantage with ASR is the DRAM cannot always switchfroma1xtoa2xrefreshrateatanexactcasetemperatureof85°C.AlthoughtheDRAMwillsupportdata integritywhen itswitchesfroma1xtoa2xrefreshrate,itmayswitchatalowertemperaturethan85°C.
Sinceonlyonemodeisnecessary,SRTandASRcannotbeenabledatthesametime.
DYNAMIC ODT
ThedynamicODT(RTT(WR))featureisdefinedbyMR2[10,9].DynamicODTisenabledwhenavalueisselected.ThisnewDDR3 SDRAM feature enables the ODT termination valueto change without issuing an MRS command, essentiallychangingtheODTterminationon-the-fly.
With dynamic ODT (RTT(WR)) enabled, the DRAM switchesfrom normalODT (RTT,nom) to dynamicODT (RTT(WR))whenbeginningaWRITEburstandsubsequentlyswitchesbacktoODT(RTT,nom)atthecompletionoftheWRITEburst.IfRTT,nomis disabled, the RTT,nom valuewill beHigh-Z. Special timingparametersmustbeadheredtowhendynamicODT(RTT(WR))is enabled: ODTLcnw, ODTLcnw4, ODTLcnw8, ODTH4,ODTH8,andtADC.
DynamicODTisonlyapplicableduringWRITEcycles.IfODT(RTT,nom)isdisabled,dynamicODT(RTT(WR))isstillpermitted.RTT,nomandRTT(WR)canbeused independentofoneother.Dynamic ODT is not available during write leveling mode,regardlessofthestateofODT(RTT,nom).FordetailsondynamicODToperation,refertoOn-DieTermination(ODT)(page103).
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
64
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Mode Register 3 (MR3)
Themode register3 (MR3)controlsadditional functionsandfeatures not available in the othermode registers. Currentlydefined is the MULTIPURPOSE REGISTER (MPR). ThisfunctioniscontrolledviathebitsshowninFigure26.TheMR3is programmed via the LOADMODE command and retainsthestoredinformationuntilitisprogrammedagainoruntilthedevicelosespower.ReprogrammingtheMR3register
willnotalter thecontentsof thememoryarray,provided it isperformedcorrectly.TheMR3registermustbe loadedwhenallbanksareidleandnodataburstsareinprogress,andthecontrollermustwaitthespecifiedtimetMRDandtMODbeforeinitiatingasubsequentoperation.
Figure 26: Mode Register 3 (MR3) Definition
Notes:
1. MR3[16and13:3]arereservedforfutureuseandmustallbeprogrammedto0.
2. WhenMPRcontrolissetfornormalDRAMoperation,MR3[1,0]willbeignored.
3. IntendedtobeusedforREADsynchronization.
back to ODT (RTT,nom) at the completion of the WRITE burst. If RTT,nom is disabled, theRTT,nom value will be High-Z. Special timing parameters must be adhered to when dy-namic ODT (RTT(WR)) is enabled: ODTLcnw, ODTLcnw4, ODTLcnw8, ODTH4, ODTH8,and tADC.
Dynamic ODT is only applicable during WRITE cycles. If ODT (RTT,nom) is disabled, dy-namic ODT (RTT(WR)) is still permitted. RTT,nom and RTT(WR) can be used independent ofone other. Dynamic ODT is not available during write leveling mode, regardless of thestate of ODT (RTT,nom). For details on dynamic ODT operation, refer to On-Die Termina-tion (ODT) (page 193).
Mode Register 3 (MR3)The mode register 3 (MR3) controls additional functions and features not available inthe other mode registers. Currently defined is the MULTIPURPOSE REGISTER (MPR).This function is controlled via the bits shown in Figure 59 (page 147). The MR3 is pro-grammed via the LOAD MODE command and retains the stored information until it isprogrammed again or until the device loses power. Reprogramming the MR3 registerwill not alter the contents of the memory array, provided it is performed correctly. TheMR3 register must be loaded when all banks are idle and no data bursts are in progress,and the controller must wait the specified time tMRD and tMOD before initiating a sub-sequent operation.
Figure 59: Mode Register 3 (MR3) Definition
A9 A7 A6 A5 A4 A3A8 A2 A1 A0
Mode register 3 (MR3)
Address bus
9 7 6 5 4 38 2 1 0
A10A12 A11BA0BA1
101112131415
A13
1 01 01 01 01 01 01 01 MPR 1
BA2
16
01 01 01 01 01
M2
0
1
MPR Enable
Normal DRAM operations2
Dataflow from MPR
MPR_RF
M14
0
1
0
1
M15
0
0
1
1
Mode Register
Mode register set (MR0)
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
MPR READ Function
Predefined pattern3
Reserved
Reserved
Reserved
M0
0
1
0
1
M1
0
0
1
1
Notes: 1. MR3[16 and 13:3] are reserved for future use and must all be programmed to 0.2. When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored.3. Intended to be used for READ synchronization.
MULTIPURPOSE REGISTER (MPR)
The MULTIPURPOSE REGISTER function is used to output a predefined system timingcalibration bit sequence. Bit 2 is the master bit that enables or disables access to theMPR register, and bits 1 and 0 determine which mode the MPR is placed in. The basicconcept of the multipurpose register is shown in Figure 60 (page 148).
If MR3[2] is a 0, then the MPR access is disabled, and the DRAM operates in normalmode. However, if MR3[2] is a 1, then the DRAM no longer outputs normal read databut outputs MPR data as defined by MR3[0, 1]. If MR3[0, 1] is equal to 00, then a prede-fined read pattern for system calibration is selected.
1Gb: x4, x8, x16 DDR3 SDRAMMode Register 3 (MR3)
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MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
65
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
MULTIPURPOSE REGISTER (MPR)
TheMULTIPURPOSEREGISTERfunctionisusedtooutputapredefinedsystemtimingcalibrationbitsequence.Bit2isthemasterbitthatenablesordisablesaccesstotheMPRregister,andbits1and0determinewhichmode theMPR isplacedin.ThebasicconceptofthemultipurposeregisterisshowninFigure27(page65).
IfMR3[2] is a 0, then theMPRaccess is disabled, and theDRAMoperates innormalmode.However, ifMR3[2] isa1,thentheDRAMnolongeroutputsnormalreaddatabutoutputsMPRdataasdefinedbyMR3[0,1]. IfMR3[0,1] isequal to00, then a predefined read pattern for system calibration isselected.
ToenabletheMPR,theMRScommandisissuedtoMR3,andMR3[2]=1.PriortoissuingtheMRScommand,allbanksmustbeintheidlestate(allbanksareprecharged,andtRPismet).When theMPR isenabled,anysubsequentREADorRDAPcommands are redirected to the multipurpose register. TheresultingoperationwheneitheraREADoraRDAPcommandis issued, isdefinedbyMR3[1:0]when theMPR is enabled(see Table 28 (page 66)). When the MPR is enabled, onlyREAD or RDAP commands are allowed until a subsequentMRScommand is issuedwith theMPRdisabled (MR3[2] =0).Power-downmode,selfrefresh,andanyothernonREAD/RDAPcommandsarenotallowedduringMPRenablemode.TheRESETfunctionissupportedduringMPRenablemode.
Figure 27: Multipurpose Register (MPR) Block Diagram
To enable the MPR, the MRS command is issued to MR3, and MR3[2] = 1. Prior to issu-ing the MRS command, all banks must be in the idle state (all banks are precharged,and tRP is met). When the MPR is enabled, any subsequent READ or RDAP commandsare redirected to the multipurpose register. The resulting operation when either a READor a RDAP command is issued, is defined by MR3[1:0] when the MPR is enabled (seeTable 78 (page 149)). When the MPR is enabled, only READ or RDAP commands are al-lowed until a subsequent MRS command is issued with the MPR disabled (MR3[2] = 0).Power-down mode, self refresh, and any other nonREAD/RDAP commands are not al-lowed during MPR enable mode. The RESET function is supported during MPR enablemode.
Figure 60: Multipurpose Register (MPR) Block Diagram
Memory core
MR3[2] = 0 (MPR off)
DQ, DM, DQS, DQS#
Multipurpose registerpredefined data for READs
MR3[2] = 1 (MPR on)
Notes: 1. A predefined data pattern can be read out of the MPR with an external READ com-mand.
2. MR3[2] defines whether the data flow comes from the memory core or the MPR. Whenthe data flow is defined, the MPR contents can be read out continuously with a regularREAD or RDAP command.
Table 77: MPR Functional Description of MR3 Bits
MR3[2] MR3[1:0]
FunctionMPR MPR READ Function
0 “Don’t Care” Normal operation, no MPR transactionAll subsequent READs come from the DRAM memory array
All subsequent WRITEs go to the DRAM memory array
1 A[1:0](see Table 78 (page 149))
Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and2
MPR Functional Description
The MPR JEDEC definition enables either a prime DQ (DQ0 on a x4 and a x8; on a x16,DQ0 = lower byte and DQ8 = upper byte) to output the MPR data with the remainingDQs driven LOW, or for all DQs to output the MPR data. The MPR readout supports
1Gb: x4, x8, x16 DDR3 SDRAMMode Register 3 (MR3)
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Notes:
1. ApredefineddatapatterncanbereadoutoftheMPRwithanexternalREADcommand.
2. MR3[2]defineswhetherthedataflowcomesfromthememorycoreortheMPR.Whenthedataflowisdefined,theMPRcontentscanbereadoutcontinuouslywitharegularREADorRDAPcommand.
Table 27: MPR Functional Description of MR3 Bits
MR3[2] MR3[1:0]Function
MPR MPR READ Function
0 “Don’t Care”Normal operation, no MPR transaction
All subsequent READs come from the DRAM memory arrayAll subsequent WRITEs go to the DRAM memory array
1A[1:0]
(see Table 28 (page 66))Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and 2
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
MPR Functional Description
TheMPRJEDECdefinitionenableseitheraprimeDQ(DQ0onax4andax8;onax16,DQ0=lowerbyteandDQ8=upperbyte)tooutputtheMPRdatawiththeremainingDQsdrivenLOW,orforallDQstooutputtheMPRdata.TheMPRreadoutsupportsfixedREADburstandREADburstchop(MRSandOTFviaA12/BC#)withregularREADlatenciesandACtimingsapplicable,providedtheDLLislockedasrequired.
MPRaddressingforavalidMPRreadisasfollows:
• A[1:0]mustbesetto00astheburstorderisfixedpernibble
• A2selectstheburstorder:
• BL8,A2issetto0,andtheburstorderisfixedto0,1,2,3,4,5,6,7
• Forburstchop4cases,theburstorderisswitchedonthenibblebasealongwiththefollowing:
• A2=0;burstorder=0,1,2,3
• A2=1;burstorder=4,5,6,7
• Burstorderbit0(thefirstbit)isassignedtoLSB,andburstorderbit7(thelastbit)isassignedtoMSB
• A[9:3]area“Don’tCare”
• A10isa“Don’tCare”
• A11isa“Don’tCare”
• A12:Selectsburstchopmodeon-the-fly,ifenabledwithinMR0
• A13isa“Don’tCare”
• BA[2:0]area“Don’tCare”
MPR Register Address Definitions and Bursting Order
TheMPRcurrently supports a singledata format. This dataformat is a predefined read pattern for system calibration.Thepredefinedpatternisalwaysarepeating0–1bitpattern.Examples of the different types of predefinedREADpatternburstsareshowninthefollowingfigures.
Table 28: MPR Readouts and Burst Order Bit Mapping
MR3[2] MR3[1:0] FunctionBurst
LengthRead A[2:0]
Burst Order and Data Pattern
1 00 READ predefined pattern for system calibration
BL8000
Burst order: 0, 1, 2, 3, 4, 5, 6, 7; Predefined pattern: 0, 1, 0, 1, 0, 1, 0, 1
BC4 Burst order: 0, 1, 2, 3; Predefined pattern: 0, 1, 0, 1
BC4 100 Burst order: 4, 5, 6, 7; Predefined pattern: 0, 1, 0, 1
1 01
RFU N/A N/A N/A1 10
1 11
Note:
1. Burstorderbit0isassignedtoLSB,andburstorderbit7isassignedtoMSBoftheselectedMPRagent.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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67
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
MPR Read Predefined Pattern
Thepredeterminedreadcalibrationpattern isafixedpatternof0,1,0,1,0,1,0,1.Thefollowingisanexampleofusingthe read out predetermined read calibration pattern. Theexample is to performmultiple reads from themultipurposeregistertodosystemlevelreadtimingcalibrationbasedonthepredeterminedandstandardizedpattern.
Thefollowingprotocoloutlinesthestepsusedtoperformthereadcalibration:
1. Prechargeallbanks
2. AftertRPissatisfied,setMRS,MR3[2]=1andMR3[1:0]=00.ThisredirectsallsubsequentreadsandloadsthepredefinedpatternintotheMPR.AssoonastMRDandtMODaresatisfied,theMPRisavailable
3. DataWRITEoperationsarenotalloweduntiltheMPRreturnstothenormalDRAMstate
4. Issueareadwithburstorderinformation(allotheraddresspinsare“Don’tCare”):
• A[1:0]=00(databurstorderisfixedstartingatnibble)
• A2=0(forBL8,burstorderisfixedas0,1,2,3,4,5,6,7)
• A12=1(useBL8)
5. AfterRL=AL+CL,theDRAMburstsoutthepredefinedreadcalibrationpattern(0,1,0,1,0,1,0,1)
6. Thememorycontrollerrepeatsthecalibrationreadsuntilreaddatacaptureatmemorycontrollerisoptimized
7. AfterthelastMPRREADburstandaftertMPRRhasbeensatisfied,issueMRS,MR3[2]=0,andMR3[1:0]=“Don’tCare”tothenormalDRAMstate.Allsubsequentreadandwriteaccesseswillberegularreadsandwritesfrom/totheDRAMarray
8. WhentMRDandtMODaresatisfiedfromthelastMRS,theregularDRAMcommands(suchasactivateamemorybankforregularreadorwriteaccess)arepermitted
MODE REGISTER SET (MRS) CommandThe mode registers are loaded via inputs BA[2:0], A[13:0].BA[2:0]determinewhichmoderegisterisprogrammed:
• BA2=0,BA1=0,BA0=0forMR0
• BA2=0,BA1=0,BA0=1forMR1
• BA2=0,BA1=1,BA0=0forMR2
• BA2=0,BA1=1,BA0=1forMR3
TheMRScommandcanonlybeissued(orre-issued)whenallbanksareidleandintheprechargedstate(tRPissatisfiedandnodataburstsare inprogress).Thecontrollermustwait thespecified time tMRDbefore initiatingasubsequentoperationsuch as an ACTIVATE command (see Figure 18 (page 52)).There is also a restriction after issuing an MRS commandwithregardtowhentheupdatedfunctionsbecomeavailable.Thisparameter isspecifiedby tMOD.Both tMRDand tMODparametersareshown inFigure18 (page52)andFigure19(page53).Violatingeitherof these requirementswill result inunspecifiedoperation.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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68
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
ZQ CALIBRATION Operation
The ZQ CALIBRATION command is used to calibrate theDRAMoutputdrivers(RON)andODTvalues(RTT)overprocess,voltage,andtemperature,providedadedicated240Ω (±1%)external resistor is connected from the DRAM’s ZQ ball toVSSQ.
DDR3SDRAMrequirealongertimetocalibrateRONandODTatpower-up initializationandself refreshexit,andarelativelyshorter time toperformperiodic calibrations.DDR3SDRAMdefinestwoZQCALIBRATIONcommands:ZQCLandZQCS.AnexampleofZQcalibrationtimingisshownbelow.
Allbanksmustbeprechargedand tRPmustbemetbeforeZQCLorZQCScommandscanbeissuedtotheDRAM.No
other activities (other than issuing another ZQCL or ZQCScommand) canbeperformedon theDRAMchannel by thecontrollerforthedurationoftZQinitortZQoper.ThequiettimeontheDRAMchannelhelpsaccuratelycalibrateRONandODT.AfterDRAMcalibrationisachieved,theDRAMshoulddisabletheZQball’scurrentconsumptionpathtoreducepower.
ZQCALIBRATIONcommandscanbeissuedinparalleltoDLLRESET and locking time. Upon self refresh exit, an explicitZQCLisrequiredifZQcalibrationisdesired.
In dual-rank systems that share the ZQ resistor betweendevices, the controller must not enable overlap of tZQinit,tZQoper,ortZQCSbetweenranks.
ZQ CALIBRATION OperationThe ZQ CALIBRATION command is used to calibrate the DRAM output drivers (RON)and ODT values (RTT) over process, voltage, and temperature, provided a dedicated240Ω (±1%) external resistor is connected from the DRAM’s ZQ ball to VSSQ.
DDR3 SDRAM require a longer time to calibrate RON and ODT at power-up initializationand self refresh exit, and a relatively shorter time to perform periodic calibrations.DDR3 SDRAM defines two ZQ CALIBRATION commands: ZQCL and ZQCS. An exampleof ZQ calibration timing is shown below.
All banks must be precharged and tRP must be met before ZQCL or ZQCS commandscan be issued to the DRAM. No other activities (other than issuing another ZQCL orZQCS command) can be performed on the DRAM channel by the controller for the du-ration of tZQinit or tZQoper. The quiet time on the DRAM channel helps accurately cali-brate RON and ODT. After DRAM calibration is achieved, the DRAM should disable theZQ ball’s current consumption path to reduce power.
ZQ CALIBRATION commands can be issued in parallel to DLL RESET and locking time.Upon self refresh exit, an explicit ZQCL is required if ZQ calibration is desired.
In dual-rank systems that share the ZQ resistor between devices, the controller must notenable overlap of tZQinit, tZQoper, or tZQCS between ranks.
Figure 65: ZQ CALIBRATION Timing (ZQCL and ZQCS)
NOPZQCL NOP NOP Valid Valid ZQCS NOP NOP NOP ValidCommand
Indicates breakin time scale
T0 T1 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tc0 Tc1 Tc2
Address Valid ValidValid
A10 Valid ValidValid
CK
CK#
Don’t Care
DQ High-Z High-Z33 Activities Activ-ities
Valid ValidODT 2 2 Valid
1CKE 1 Valid Valid Valid
tZQCStZQinit or tZQoper
Notes: 1. CKE must be continuously registered HIGH during the calibration procedure.2. ODT must be disabled via the ODT signal or the MRS during the calibration procedure.3. All devices connected to the DQ bus should be High-Z during calibration.
1Gb: x4, x8, x16 DDR3 SDRAMZQ CALIBRATION Operation
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2006 Micron Technology, Inc. All rights reserved.
Figure 28: ZQ CALIBRATION Timing (ZQCL and ZQCS)
Notes:
1. CKEmustbecontinuouslyregisteredHIGHduringthecalibrationprocedure.
2. ODTmustbedisabledviatheODTsignalortheMRSduringthecalibrationprocedure.
3. AlldevicesconnectedtotheDQbusshouldbeHigh-Zduringcalibration.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
ACTIVATE OperationBefore anyREADorWRITEcommandscanbe issued to abankwithin theDRAM,a row in thatbankmustbeopened(activated).ThisisaccomplishedviatheACTIVATEcommand,whichselectsboththebankandtherowtobeactivated.
AfterarowisopenedwithanACTIVATEcommand,aREADorWRITE commandmay be issued to that row, subject tothe tRCD specification. However, if the additive latency isprogrammedcorrectly,aREADorWRITEcommandmaybeissuedpriortotRCD(MIN).Inthisoperation,theDRAMenablesaREADorWRITEcommandtobeissuedaftertheACTIVATEcommand for that bank, but prior to tRCD (MIN) with therequirement that (ACTIVATE-to-READ/WRITE) + AL ≥ tRCD(MIN)(seePostedCASAdditiveLatency).tRCD(MIN)shouldbedividedby the clockperiod and roundedup to the nextwholenumber todetermine theearliestclockedgeafter theACTIVATEcommandonwhichaREADorWRITEcommandcanbeentered.Thesameprocedureisusedtoconvertotherspecificationlimitsfromtimeunitstoclockcycles.
Whenatleastonebankisopen,anyREAD-to-READcommanddelay or WRITE-to-WRITE command delay is restricted totCCD(MIN).
AsubsequentACTIVATEcommand toadifferent row in thesamebankcanonlybe issuedafter thepreviousactive rowhas been closed (precharged). The minimum time intervalbetween successive ACTIVATE commands to the samebank isdefinedby tRC.AsubsequentACTIVATEcommandto another bank canbe issuedwhile the first bank is beingaccessed, which results in a reduction of total row-accessoverhead. The minimum time interval between successiveACTIVATEcommandstodifferentbanks isdefinedby tRRD.NomorethanfourbankACTIVATEcommandsmaybeissuedinagiventFAW(MIN)period,andthetRRD(MIN)restrictionstillapplies.ThetFAW(MIN)parameterapplies,regardlessofthenumberofbanksalreadyopenedorclosed.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
READ OperationREAD bursts are initiated with a READ command. The starting column and bank ad-dresses are provided with the READ command and auto precharge is either enabled ordisabled for that burst access. If auto precharge is enabled, the row being accessed isautomatically precharged at the completion of the burst. If auto precharge is disabled,the row will be left open after the completion of the burst.
During READ bursts, the valid data-out element from the starting column address isavailable READ latency (RL) clocks later. RL is defined as the sum of posted CAS additivelatency (AL) and CAS latency (CL) (RL = AL + CL). The value of AL and CL is programma-ble in the mode register via the MRS command. Each subsequent data-out element isvalid nominally at the next positive or negative clock edge (that is, at the next crossingof CK and CK#). Figure 68 shows an example of RL based on a CL setting of 8 and an ALsetting of 0.
Figure 68: READ Latency
CK
CK#
Command READ NOP NOP NOP NOP NOP NOP NOP
AddressBank a,Col n
CL = 8, AL = 0
DQ
DQS, DQS#
DOn
T0 T7 T8 T9 T10 T11
Don’t CareTransitioning Data
T12 T12
Indicates breakin time scale
Notes: 1. DO n = data-out from column n.2. Subsequent elements of data-out appear in the programmed order following DO n.
DQS, DQS# is driven by the DRAM along with the output data. The initial LOW state onDQS and HIGH state on DQS# is known as the READ preamble (tRPRE). The LOW stateon DQS and the HIGH state on DQS#, coincident with the last data-out element, isknown as the READ postamble (tRPST). Upon completion of a burst, assuming no othercommands have been initiated, the DQ goes High-Z. A detailed explanation of tDQSQ(valid data-out skew), tQH (data-out window hold), and the valid data window are de-picted in Figure 79 (page 167). A detailed explanation of tDQSCK (DQS transition skewto CK) is also depicted in Figure 79 (page 167).
Data from any READ burst may be concatenated with data from a subsequent READcommand to provide a continuous flow of data. The first data element from the newburst follows the last element of a completed burst. The new READ command should beissued tCCD cycles after the first READ command. This is shown for BL8 in Figure 69(page 161). If BC4 is enabled, tCCD must still be met, which will cause a gap in the dataoutput, as shown in Figure 70 (page 161). Nonconsecutive READ data is reflected in
1Gb: x4, x8, x16 DDR3 SDRAMREAD Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 159 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
READ Operation
READburstsareinitiatedwithaREADcommand.Thestartingcolumn and bank addresses are provided with the READcommandandautoprechargeiseitherenabledordisabledforthatburstaccess.Ifautoprechargeisenabled,therowbeingaccessedisautomaticallyprechargedatthecompletionoftheburst. Ifautoprecharge isdisabled,therowwillbe leftopenafterthecompletionoftheburst.
During READ bursts, the valid data-out element from thestarting column address is available READ latency (RL)
clockslater.RLisdefinedasthesumofpostedCASadditivelatency(AL)andCASlatency(CL)(RL=AL+CL).ThevalueofALandCL isprogrammable in themode register via theMRScommand.Each subsequentdata-out element is validnominallyatthenextpositiveornegativeclockedge(thatis,atthenextcrossingofCKandCK#).Figure29showsanexampleofRLbasedonaCLsettingof8andanALsettingof0.
Figure 29: READ Latency
Notes:
1. DOn=data-outfromcolumnn.
2. Subsequentelementsofdata-outappearintheprogrammedorderfollowingDOn.
DQS,DQS#isdrivenbytheDRAMalongwiththeoutputdata.The initial LOW state on DQS andHIGH state on DQS# isknownastheREADpreamble(tRPRE).TheLOWstateonDQSandtheHIGHstateonDQS#,coincidentwith the lastdata-outelement,isknownastheREADpostamble(tRPST).Uponcompletion of a burst, assuming no other commands havebeeninitiated,theDQgoesHigh-Z.AdetailedexplanationoftDQSQ(validdata-outskew),tQH(data-outwindowhold),andthevaliddatawindowaredepictedinFigure40(page78).AdetailedexplanationoftDQSCK(DQStransitionskewtoCK)isalsodepictedinFigure40(page78).
Data fromanyREADburstmaybe concatenatedwith datafromasubsequentREADcommandtoprovideacontinuousflow of data. The first data element from the new burstfollowsthelastelementofacompletedburst.ThenewREADcommandshouldbeissuedtCCDcyclesafterthefirstREADcommand. This is shown for BL8 in Figure 30 (page 72).IfBC4isenabled,tCCDmuststillbemet,whichwillcauseagap in the data output, as shown in Figure 31 (page 72).Nonconsecutive READ data is reflected in Figure 32 (page73).DDR3SDRAMdoesnotallow interruptingor truncatinganyREADburst.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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71
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Data from any READ burst must be completed before asubsequentWRITEburst isallowed.AnexampleofaREADburstfollowedbyaWRITEburstforBL8isshowninFigure33(page 73) (BC4 is shown in Figure 34 (page 74). To ensuretheREADdataiscompletedbeforetheWRITEdataisonthebus,theminimumREAD-to-WRITEtimingisRL+tCCD-WL+2tCK.
AREADburstmaybefollowedbyaPRECHARGEcommandto thesamebank,providedautoprecharge isnotactivated.Theminimum READ-to-PRECHARGE command spacing tothesamebankisfourclocksandmustalsosatisfyaminimumanalogtimefromtheREADcommand.ThistimeiscalledtRTP(READ-to-PRECHARGE).tRTPstartsALcycleslaterthantheREADcommand.Examples forBL8areshown inFigure35(page 74) and BC4 in Figure 36 (page 75). Following thePRECHARGEcommand,asubsequentcommandtothesamebank cannot be issued until tRP is met. The PRECHARGEcommand followed by another PRECHARGE command tothesamebankisallowed.However,theprechargeperiodwillbedeterminedbythelastPRECHARGEcommandissuedtothebank.
IfA10isHIGHwhenaREADcommandisissued,theREADwithautoprechargefunctionisengaged.TheDRAMstartsanautoprechargeoperationon the rising edge,which isAL+tRTPcyclesaftertheREADcommand.DRAMsupportatRASlockout feature Figure 38 (page 75). If tRAS (MIN) is notsatisfiedattheedge,thestartingpointoftheautoprechargeoperationwillbedelayeduntil tRAS(MIN) issatisfied. If tRTP(MIN)isnotsatisfiedattheedge,thestartingpointoftheautoprechargeoperationisdelayeduntiltRTP(MIN)issatisfied.IncasetheinternalprechargeispushedoutbytRTP,tRPstartsatthepointatwhichtheinternalprechargehappens(notatthenext risingclockedgeafter thisevent).The time fromREADwithautoprecharge to thenextACTIVATEcommand to thesamebankisAL+(tRTP+tRP)*,where*meansroundeduptothenext integer. Inanyevent, internalprechargedoesnotstartearlierthanfourclocksafterthelast8n-bitprefetch.
READ Operation (continued)
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Fig
ure
69: C
on
secu
tive R
EA
D B
urs
ts (
BL8
)
T0T1
T2T3
T4T5
T6T7
T8T9
T10
T11
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
T12
T13
T14
t RPS
T
NO
PRE
AD
REA
DN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
P
CKCK#
Com
man
d1
DQ
3
DQ
S, D
QS#
Bank
,Co
l nBa
nk,
Col b
Add
ress
2
RL
= 5
t RPR
E
t CC
D
RL
= 5
DO
n +
3D
O n
+ 2
DO
n +
1D
O nD
O n
+ 7
DO
n +
6D
O n
+ 5
DO
n
+ 4
DO
b +
3D
O b
+ 2
DO
b +
1D
O bD
O b
+ 7
DO
b +
6D
O b
+ 5
DO
b
+ 4
No
tes:
1.N
OP
com
man
ds
are
sho
wn
fo
r ea
se o
f ill
ust
rati
on
; oth
er c
om
man
ds
may
be
valid
at
thes
e ti
mes
.2.
The
BL8
set
tin
g is
act
ivat
ed b
y ei
ther
MR
0[1:
0] =
00
or
MR
0[1:
0] =
01
and
A12
= 1
du
rin
g R
EAD
co
mm
and
at
T0an
d T
4.3.
DO
n (
or
b)
= d
ata-
ou
t fr
om
co
lum
n n
(o
r co
lum
n b
).4.
BL8
, RL
= 5
(C
L =
5, A
L =
0).
Fig
ure
70: C
on
secu
tive R
EA
D B
urs
ts (
BC
4)
NO
P
CKCK#
Com
man
d1
DQ
3
DQ
S, D
QS#
T0T1
T2T3
T4T5
T6T7
T8T9
Add
ress
2
T10
T11
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
T12
T13
T14
REA
DRE
AD
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
Bank
,Co
l nBa
nk,
Col b
t RPS
Tt R
PRE
t RPS
Tt R
PRE
RL
= 5
DO
n +
3D
O n
+ 2
DO
n +
1D
O nD
O b
+ 3
DO
b +
2D
O b
+ 1
DO b
RL
= 5
t CC
D
No
tes:
1.N
OP
com
man
ds
are
sho
wn
fo
r ea
se o
f ill
ust
rati
on
; oth
er c
om
man
ds
may
be
valid
at
thes
e ti
mes
.2.
The
BC
4 se
ttin
g is
act
ivat
ed b
y ei
ther
MR
0[1:
0] =
10
or
MR
0[1:
0] =
01
and
A12
= 0
du
rin
g R
EAD
co
mm
and
at
T0an
d T
4.3.
DO
n (
or
b)
= d
ata-
ou
t fr
om
co
lum
n n
(o
r co
lum
n b
).4.
BC
4, R
L =
5 (
CL
= 5
, AL
= 0
).
1Gb: x4, x8, x16 DDR3 SDRAMREAD Operation
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2006 Micron Technology, Inc. All rights reserved.
Fig
ure
69: C
on
secu
tive R
EA
D B
urs
ts (
BL8
)
T0T1
T2T3
T4T5
T6T7
T8T9
T10
T11
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
T12
T13
T14
t RPS
T
NO
PRE
AD
REA
DN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
P
CKCK#
Com
man
d1
DQ
3
DQ
S, D
QS#
Bank
,Co
l nBa
nk,
Col b
Add
ress
2
RL
= 5
t RPR
E
t CC
D
RL
= 5
DO
n +
3D
O n
+ 2
DO
n +
1D
O nD
O n
+ 7
DO
n +
6D
O n
+ 5
DO
n
+ 4
DO
b +
3D
O b
+ 2
DO
b +
1D
O bD
O b
+ 7
DO
b +
6D
O b
+ 5
DO
b
+ 4
No
tes:
1.N
OP
com
man
ds
are
sho
wn
fo
r ea
se o
f ill
ust
rati
on
; oth
er c
om
man
ds
may
be
valid
at
thes
e ti
mes
.2.
The
BL8
set
tin
g is
act
ivat
ed b
y ei
ther
MR
0[1:
0] =
00
or
MR
0[1:
0] =
01
and
A12
= 1
du
rin
g R
EAD
co
mm
and
at
T0an
d T
4.3.
DO
n (
or
b)
= d
ata-
ou
t fr
om
co
lum
n n
(o
r co
lum
n b
).4.
BL8
, RL
= 5
(C
L =
5, A
L =
0).
Fig
ure
70: C
on
secu
tive R
EA
D B
urs
ts (
BC
4)
NO
P
CKCK#
Com
man
d1
DQ
3
DQ
S, D
QS#
T0T1
T2T3
T4T5
T6T7
T8T9
Add
ress
2
T10
T11
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
T12
T13
T14
REA
DRE
AD
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
Bank
,Co
l nBa
nk,
Col b
t RPS
Tt R
PRE
t RPS
Tt R
PRE
RL
= 5
DO
n +
3D
O n
+ 2
DO
n +
1D
O nD
O b
+ 3
DO
b +
2D
O b
+ 1
DO b
RL
= 5
t CC
D
No
tes:
1.N
OP
com
man
ds
are
sho
wn
fo
r ea
se o
f ill
ust
rati
on
; oth
er c
om
man
ds
may
be
valid
at
thes
e ti
mes
.2.
The
BC
4 se
ttin
g is
act
ivat
ed b
y ei
ther
MR
0[1:
0] =
10
or
MR
0[1:
0] =
01
and
A12
= 0
du
rin
g R
EAD
co
mm
and
at
T0an
d T
4.3.
DO
n (
or
b)
= d
ata-
ou
t fr
om
co
lum
n n
(o
r co
lum
n b
).4.
BC
4, R
L =
5 (
CL
= 5
, AL
= 0
).
1Gb: x4, x8, x16 DDR3 SDRAMREAD Operation
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2006 Micron Technology, Inc. All rights reserved.
Figu
re 3
0: C
onse
cutiv
e RE
AD B
urst
s (B
L8)
Figu
re 3
1: C
onse
cutiv
e RE
AD B
urst
s (B
C4)
Notes:
1.NOPcom
mandsareshownfore
aseofillustration;othercom
mandsm
aybevalidatthesetimes.
2.TheBL8settingisactivatedbyeitherM
R0[1:0]=00orM
R0[1:0]=01andA12
=1duringREA
Dcom
mandatT0andT4
.
3.DOn(orb
)=data-outfromcolum
nn(orc
olum
nb).
4.BL8,R
L=5(CL=5,AL=0).
Notes:
1.NOPcom
mandsareshownfore
aseofillustration;othercom
mandsm
aybevalidatthesetimes.
2.TheBC4settingisactivatedbyeitherM
R0[1:0]=10orM
R0[1:0]=01andA12
=0duringREA
Dcom
mandatT0andT4
.
3.DOn(orb
)=data-outfromcolum
nn(orc
olum
nb).
4.BC4,RL=5(CL=5,AL=0).
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
73
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Fig
ure
71: N
on
con
secu
tive R
EA
D B
urs
ts
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
T0T1
T2T3
T4T5
T6T7
T8T9
T10
T11
T12
T13
T14
T15
T16
T17
DQ
S, D
QS#
Com
man
dN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
REA
DN
OP
REA
D
Add
ress
Bank
a,
Col n
Bank
a,
Col b
CKCK#
DQ
DO n
DO b
CL
= 8
C
L =
8
No
tes:
1.A
L =
0, R
L =
8.
2.D
O n
(o
r b
) =
dat
a-o
ut
fro
m c
olu
mn
n (
or
colu
mn
b).
3.Se
ven
su
bse
qu
ent
elem
ents
of
dat
a-o
ut
app
ear
in t
he
pro
gra
mm
ed o
rder
fo
llow
ing
DO
n.
4.Se
ven
su
bse
qu
ent
elem
ents
of
dat
a-o
ut
app
ear
in t
he
pro
gra
mm
ed o
rder
fo
llow
ing
DO
b.
Fig
ure
72: R
EA
D (
BL8
) to
WR
ITE (
BL8
)
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
T0T1
T2T3
T4T5
T6T7
T8T9
T10
T11
T12
T13
T14
T15
CKCK#
Com
man
d1N
OP
NO
PN
OP
NO
PN
OP
WRI
TEN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
t WPS
Tt R
PRE
t WPR
Et R
PST
DQ
S, D
QS#
DQ
3
WL
= 5
t WR
t WR
REA
D
DO n
DO
n +
1D
O n
+ 2
DO
n +
3D
O n
+ 4
DO
n +
5D
O n
+ 6
DO
n +
7D
I n
DI
n +
1D
I n
+ 2
DI
n +
3D
I n
+ 4
DI
n +
5D
I n
+ 6
DI
n +
7
REA
D-t
o-W
RIT
E co
mm
and
del
ay =
RL
+ t C
CD
+ 2
t CK
- W
Lt B
L =
4 c
lock
s
Add
ress
2Ba
nk,
Col b
Bank
,Co
l n
RL
= 5
No
tes:
1.N
OP
com
man
ds
are
sho
wn
fo
r ea
se o
f ill
ust
rati
on
; oth
er c
om
man
ds
may
be
valid
at
thes
e ti
mes
.2.
The
BL8
set
tin
g is
act
ivat
ed b
y ei
ther
MR
0[1:
0] =
00
or
MR
0[1:
0] =
01
and
A12
= 1
du
rin
g t
he
REA
D c
om
man
d a
tT0
, an
d t
he
WR
ITE
com
man
d a
t T6
.3.
DO
n =
dat
a-o
ut
fro
m c
olu
mn
, DI b
= d
ata-
in f
or
colu
mn
b.
4.B
L8, R
L =
5 (
AL
= 0
, CL
= 5
), W
L =
5 (
AL
= 0
, CW
L =
5).
1Gb: x4, x8, x16 DDR3 SDRAMREAD Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 162 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Fig
ure
71: N
on
con
secu
tive R
EA
D B
urs
ts
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
T0T1
T2T3
T4T5
T6T7
T8T9
T10
T11
T12
T13
T14
T15
T16
T17
DQ
S, D
QS#
Com
man
dN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
REA
DN
OP
REA
D
Add
ress
Bank
a,
Col n
Bank
a,
Col b
CKCK#
DQ
DO n
DO b
CL
= 8
C
L =
8
No
tes:
1.A
L =
0, R
L =
8.
2.D
O n
(o
r b
) =
dat
a-o
ut
fro
m c
olu
mn
n (
or
colu
mn
b).
3.Se
ven
su
bse
qu
ent
elem
ents
of
dat
a-o
ut
app
ear
in t
he
pro
gra
mm
ed o
rder
fo
llow
ing
DO
n.
4.Se
ven
su
bse
qu
ent
elem
ents
of
dat
a-o
ut
app
ear
in t
he
pro
gra
mm
ed o
rder
fo
llow
ing
DO
b.
Fig
ure
72: R
EA
D (
BL8
) to
WR
ITE (
BL8
)
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
T0T1
T2T3
T4T5
T6T7
T8T9
T10
T11
T12
T13
T14
T15
CKCK#
Com
man
d1N
OP
NO
PN
OP
NO
PN
OP
WRI
TEN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
t WPS
Tt R
PRE
t WPR
Et R
PST
DQ
S, D
QS#
DQ
3
WL
= 5
t WR
t WR
REA
D
DO n
DO
n +
1D
O n
+ 2
DO
n +
3D
O n
+ 4
DO
n +
5D
O n
+ 6
DO
n +
7D
I n
DI
n +
1D
I n
+ 2
DI
n +
3D
I n
+ 4
DI
n +
5D
I n
+ 6
DI
n +
7
REA
D-t
o-W
RIT
E co
mm
and
del
ay =
RL
+ t C
CD
+ 2
t CK
- W
Lt B
L =
4 c
lock
s
Add
ress
2Ba
nk,
Col b
Bank
,Co
l n
RL
= 5
No
tes:
1.N
OP
com
man
ds
are
sho
wn
fo
r ea
se o
f ill
ust
rati
on
; oth
er c
om
man
ds
may
be
valid
at
thes
e ti
mes
.2.
The
BL8
set
tin
g is
act
ivat
ed b
y ei
ther
MR
0[1:
0] =
00
or
MR
0[1:
0] =
01
and
A12
= 1
du
rin
g t
he
REA
D c
om
man
d a
tT0
, an
d t
he
WR
ITE
com
man
d a
t T6
.3.
DO
n =
dat
a-o
ut
fro
m c
olu
mn
, DI b
= d
ata-
in f
or
colu
mn
b.
4.B
L8, R
L =
5 (
AL
= 0
, CL
= 5
), W
L =
5 (
AL
= 0
, CW
L =
5).
1Gb: x4, x8, x16 DDR3 SDRAMREAD Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 162 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Figu
re 3
2: N
onco
nsec
utiv
e RE
AD B
urst
s
Figu
re 3
3: R
EAD
(BL8
) to
WRI
TE (B
L8)
Notes:
1.AL=0,RL=8.
2.DOn(orb
)=data-outfromcolum
nn(orc
olum
nb).
3.Sevensub
sequ
entelementsofd
ata-outapp
earintheprog
rammedorderfollowingDOn.
4.Sevensub
sequ
entelementsofd
ata-outapp
earintheprog
rammedorderfollowingDOb.
Notes:
1.NOPcom
mandsareshownfore
aseofillustration;othercom
mandsm
aybevalidatthesetimes.
2.TheBL8settingisactivatedbyeitherM
R0[1:0]=00orM
R0[1:0]=01andA12
=1duringtheREA
Dcom
mandatT0,and
theWRITEcommandatT6.
3.DOn=data-outfromcolum
n,DIb=data-inforc
olum
nb.
4.BL8,R
L=5(AL=0,CL=5),W
L=5(AL=0,CWL=5).
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
74
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Fig
ure
73: R
EA
D (
BC
4)
to W
RIT
E (
BC
4)
OTF
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
T0T1
T2T3
T4T5
T6T7
T8T9
T10
T11
T12
T13
T14
T15
CKCK#
Add
ress
2
Com
man
d1
t WPS
Tt W
PRE
t RPS
T
DQ
S, D
QS#
DQ
3
WL
= 5
t WR
t WTR
t BL
= 4
clo
cks
t RPR
E
RL
= 5
REA
D-t
o-W
RIT
E co
mm
and
del
ay =
RL
+ t C
CD
/2 +
2t C
K -
WL
REA
D
DO n
DO
n +
1D
On
+ 2
DO
n +
3D
I nD
In
+ 1
DI
n +
2D
In
+ 3
Bank
,Co
l bBa
nk,
Col n
NO
PN
OP
NO
PW
RITE
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
P
No
tes:
1.N
OP
com
man
ds
are
sho
wn
fo
r ea
se o
f ill
ust
rati
on
; oth
er c
om
man
ds
may
be
valid
at
thes
e ti
mes
.2.
The
BC
4 O
TF s
etti
ng
is a
ctiv
ated
by
MR
0[1:
0] a
nd
A12
= 0
du
rin
g R
EAD
co
mm
and
at
T0 a
nd
WR
ITE
com
man
d a
tT4
.3.
DO
n =
dat
a-o
ut
fro
m c
olu
mn
n; D
I n =
dat
a-in
fro
m c
olu
mn
b.
4.B
C4,
RL
= 5
(A
L -
0, C
L =
5),
WL
= 5
(A
L =
0, C
WL
= 5
).
Fig
ure
74: R
EA
D t
o P
REC
HA
RG
E (
BL8
)
t RA
St RTP
CKCK#
Com
man
dN
OP
NO
PN
OP
NO
P
Add
ress
DQ
DQ
S, D
QS#
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
NO
PN
OP
NO
PN
OP
NO
PA
CTN
OP
NO
PN
OP
NO
P
T0T1
T2T3
T4T5
T6T7
T8T9
T10
T11
T12
T13
T14
T15
T16
T17
NO
PRE
AD
Bank
a,
Col n
NO
PPR
E
Bank
a,
(or
all)
Bank
a,
Row
b
t RP
DO n
DO
n +
1D
On
+ 2
DO
n +
3D
On
+ 4
DO
n +
5D
On
+ 6
DO
n +
7
1Gb: x4, x8, x16 DDR3 SDRAMREAD Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 163 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Fig
ure
73: R
EA
D (
BC
4)
to W
RIT
E (
BC
4)
OTF
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
T0T1
T2T3
T4T5
T6T7
T8T9
T10
T11
T12
T13
T14
T15
CKCK#
Add
ress
2
Com
man
d1
t WPS
Tt W
PRE
t RPS
T
DQ
S, D
QS#
DQ
3
WL
= 5
t WR
t WTR
t BL
= 4
clo
cks
t RPR
E
RL
= 5
REA
D-t
o-W
RIT
E co
mm
and
del
ay =
RL
+ t C
CD
/2 +
2t C
K -
WL
REA
D
DO n
DO
n +
1D
On
+ 2
DO
n +
3D
I nD
In
+ 1
DI
n +
2D
In
+ 3
Bank
,Co
l bBa
nk,
Col n
NO
PN
OP
NO
PW
RITE
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
P
No
tes:
1.N
OP
com
man
ds
are
sho
wn
fo
r ea
se o
f ill
ust
rati
on
; oth
er c
om
man
ds
may
be
valid
at
thes
e ti
mes
.2.
The
BC
4 O
TF s
etti
ng
is a
ctiv
ated
by
MR
0[1:
0] a
nd
A12
= 0
du
rin
g R
EAD
co
mm
and
at
T0 a
nd
WR
ITE
com
man
d a
tT4
.3.
DO
n =
dat
a-o
ut
fro
m c
olu
mn
n; D
I n =
dat
a-in
fro
m c
olu
mn
b.
4.B
C4,
RL
= 5
(A
L -
0, C
L =
5),
WL
= 5
(A
L =
0, C
WL
= 5
).
Fig
ure
74: R
EA
D t
o P
REC
HA
RG
E (
BL8
)
t RA
St RTP
CKCK#
Com
man
dN
OP
NO
PN
OP
NO
P
Add
ress
DQ
DQ
S, D
QS#
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
NO
PN
OP
NO
PN
OP
NO
PA
CTN
OP
NO
PN
OP
NO
P
T0T1
T2T3
T4T5
T6T7
T8T9
T10
T11
T12
T13
T14
T15
T16
T17
NO
PRE
AD
Bank
a,
Col n
NO
PPR
E
Bank
a,
(or
all)
Bank
a,
Row
b
t RP
DO n
DO
n +
1D
On
+ 2
DO
n +
3D
On
+ 4
DO
n +
5D
On
+ 6
DO
n +
7
1Gb: x4, x8, x16 DDR3 SDRAMREAD Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 163 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Figu
re 3
4: R
EAD
(BC4
) to
WRI
TE (B
C4) O
TF
Figu
re 3
5: R
EAD
to P
RECH
ARGE
(BL8
)
Notes:
1.NOPcom
mandsareshownfore
aseofillustration;othercom
mandsm
aybevalidatthesetimes.
2.TheBC4OTFsettingisactivatedbyMR0[1:0]and
A12
=0duringREA
Dcom
mandatT0andWRITEcommandatT4.
3.DOn=data-outfromcolum
nn;DIn=data-infrom
colum
nb.
4.BC4,RL=5(AL-0,CL=5),W
L=5(AL=0,CWL=5).
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
75
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Fig
ure
75: R
EA
D t
o P
REC
HA
RG
E (
BC
4)
CKCK#
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
T0T1
T2T3
T4T5
T6T7
T8T9
T10
T11
T12
T13
T14
T15
T16
T17
Com
man
dN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
ACT
NO
PN
OP
NO
PN
OP
NO
PRE
AD
NO
PPR
E
Add
ress
Bank
a,
Col n
Bank
a,
(or
all)
Bank
a,
Row
b
t RP
t RTP
DQ
S, D
QS# DQ
DO n
DO
n +
1D
On
+ 2
DO
n +
3
t RA
S
Fig
ure
76: R
EA
D t
o P
REC
HA
RG
E (
AL
= 5, C
L =
6)
CKCK#
Com
man
dN
OP
NO
PN
OP
NO
P
Add
ress
DQ
DQ
S, D
QS#
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
NO
PN
OP
NO
PN
OP
NO
P
T0T1
T2T3
T4T5
T6T7
T8T9
T10
T11
T12
T13
T14
T15
NO
PRE
AD
Bank
a,
Col n
NO
PPR
E
Bank
a,
(or
all)
ACT
Bank
a,
Row
b
NO
PN
OP
t RA
S
CL
= 6
AL
= 5
t RTP
t RP
DO
n +
3D
On
+ 2
DO n
DO
n +
1
Fig
ure
77: R
EA
D w
ith
Au
to P
rech
arg
e (
AL
= 4, C
L =
6)
CKCK#
Com
man
dN
OP
NO
PN
OP
NO
P
Add
ress
DQ
DQ
S, D
QS#
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
NO
PN
OP
NO
PN
OP
NO
P
T0T1
T2T3
T4T5
T6T7
T8T9
T10
T11
T12
T13
Ta0
t RTP
(M
IN)
NO
PRE
AD
NO
P
AL
= 4
NO
PN
OP
CL
= 6
NO
P
t RA
S (M
IN)
ACT
Ind
icat
es b
reak
in t
ime
scal
e
t RP
Bank
a,
Col n
Bank
a,
Row
b
DO n
DO
n +
1D
On
+ 2
DO
n +
3
1Gb: x4, x8, x16 DDR3 SDRAMREAD Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 164 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Fig
ure
75: R
EA
D t
o P
REC
HA
RG
E (
BC
4)
CKCK#
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
T0T1
T2T3
T4T5
T6T7
T8T9
T10
T11
T12
T13
T14
T15
T16
T17
Com
man
dN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
ACT
NO
PN
OP
NO
PN
OP
NO
PRE
AD
NO
PPR
E
Add
ress
Bank
a,
Col n
Bank
a,
(or
all)
Bank
a,
Row
b
t RP
t RTP
DQ
S, D
QS# DQ
DO n
DO
n +
1D
On
+ 2
DO
n +
3
t RA
S
Fig
ure
76: R
EA
D t
o P
REC
HA
RG
E (
AL
= 5, C
L =
6)
CKCK#
Com
man
dN
OP
NO
PN
OP
NO
P
Add
ress
DQ
DQ
S, D
QS#
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
NO
PN
OP
NO
PN
OP
NO
P
T0T1
T2T3
T4T5
T6T7
T8T9
T10
T11
T12
T13
T14
T15
NO
PRE
AD
Bank
a,
Col n
NO
PPR
E
Bank
a,
(or
all)
ACT
Bank
a,
Row
b
NO
PN
OP
t RA
S
CL
= 6
AL
= 5
t RTP
t RP
DO
n +
3D
On
+ 2
DO n
DO
n +
1
Fig
ure
77: R
EA
D w
ith
Au
to P
rech
arg
e (
AL
= 4, C
L =
6)
CKCK#
Com
man
dN
OP
NO
PN
OP
NO
P
Add
ress
DQ
DQ
S, D
QS#
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
NO
PN
OP
NO
PN
OP
NO
P
T0T1
T2T3
T4T5
T6T7
T8T9
T10
T11
T12
T13
Ta0
t RTP
(M
IN)
NO
PRE
AD
NO
P
AL
= 4
NO
PN
OP
CL
= 6
NO
P
t RA
S (M
IN)
ACT
Ind
icat
es b
reak
in t
ime
scal
e
t RP
Bank
a,
Col n
Bank
a,
Row
b
DO n
DO
n +
1D
On
+ 2
DO
n +
3
1Gb: x4, x8, x16 DDR3 SDRAMREAD Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 164 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Fig
ure
75: R
EA
D t
o P
REC
HA
RG
E (
BC
4)
CKCK#
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
T0T1
T2T3
T4T5
T6T7
T8T9
T10
T11
T12
T13
T14
T15
T16
T17
Com
man
dN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
ACT
NO
PN
OP
NO
PN
OP
NO
PRE
AD
NO
PPR
E
Add
ress
Bank
a,
Col n
Bank
a,
(or
all)
Bank
a,
Row
b
t RP
t RTP
DQ
S, D
QS# DQ
DO n
DO
n +
1D
On
+ 2
DO
n +
3
t RA
S
Fig
ure
76: R
EA
D t
o P
REC
HA
RG
E (
AL
= 5, C
L =
6)
CKCK#
Com
man
dN
OP
NO
PN
OP
NO
P
Add
ress
DQ
DQ
S, D
QS#
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
NO
PN
OP
NO
PN
OP
NO
P
T0T1
T2T3
T4T5
T6T7
T8T9
T10
T11
T12
T13
T14
T15
NO
PRE
AD
Bank
a,
Col n
NO
PPR
E
Bank
a,
(or
all)
ACT
Bank
a,
Row
b
NO
PN
OP
t RA
S
CL
= 6
AL
= 5
t RTP
t RP
DO
n +
3D
On
+ 2
DO n
DO
n +
1
Fig
ure
77: R
EA
D w
ith
Au
to P
rech
arg
e (
AL
= 4, C
L =
6)
CKCK#
Com
man
dN
OP
NO
PN
OP
NO
P
Add
ress
DQ
DQ
S, D
QS#
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
NO
PN
OP
NO
PN
OP
NO
P
T0T1
T2T3
T4T5
T6T7
T8T9
T10
T11
T12
T13
Ta0
t RTP
(M
IN)
NO
PRE
AD
NO
P
AL
= 4
NO
PN
OP
CL
= 6
NO
P
t RA
S (M
IN)
ACT
Ind
icat
es b
reak
in t
ime
scal
e
t RP
Bank
a,
Col n
Bank
a,
Row
b
DO n
DO
n +
1D
On
+ 2
DO
n +
3
1Gb: x4, x8, x16 DDR3 SDRAMREAD Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 164 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Figu
re 3
6: R
EAD
to P
RECH
ARGE
(BC4
)
Figu
re 3
7: R
EAD
to P
RECH
ARGE
(AL
= 5
, CL
= 6
)
Figu
re 3
8: R
EAD
with
Aut
o Pr
echa
rge
(AL
= 4
, CL
= 6
)
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
76
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
DQS toDQ output timing is shown in Figure 39 (page 77).TheDQtransitionsbetweenvaliddataoutputsmustbewithintDQSQofthecrossingpointofDQS,DQS#.DQSmustalsomaintainaminimumHIGHandLOWtimeoftQSHandtQSL.PriortotheREADpreamble,theDQballswilleitherbefloatingorterminated,dependingonthestatusoftheODTsignal.
Figure40 (page78)showsthestrobe-to-clock timingduringaREAD.ThecrossingpointDQS,DQS#musttransitionwithin±tDQSCKof the clock crossing point. The data out has notimingrelationshiptoCK,onlytoDQS,asshowninFigure40(page78).
Figure 40 (page 78) also shows the READ preamble andpostamble.Typically,bothDQSandDQS#areHigh-Ztosavepower (VDDQ). Prior todataoutput from theDRAM,DQS isdrivenLOWandDQS#isHIGHfortRPRE.This isknownastheREADpreamble.
TheREADpostamble, tRPST, isonehalfclock fromthe lastDQS,DQS# transition.During theREADpostamble,DQS isdrivenLOWandDQS# isHIGH.Whencomplete, theDQ isdisabledorcontinuesterminating,dependingonthestateoftheODTsignal.onpagedemonstrateshowtomeasuretRPST.
READ Operation (continued)
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
77
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Fig
ure
78
: D
ata
Ou
tpu
t Ti
min
g –
tD
QSQ
an
d D
ata
Vali
d W
ind
ow
T0T1
T2T3
T4T5
T6T7
T8T9
T10
Bank
,Co
l n
t RPS
T
NO
PRE
AD
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
P
CKCK#
Com
man
d1
Add
ress
2
t DQ
SQ (
MA
X)
DQ
S, D
QS#
DQ
3 (la
st d
ata
valid
)
DQ
3 (f
irst
dat
a no
long
er v
alid
)
All
DQ
col
lect
ivel
y
DO n
DO
n +
3D
On
+ 2
DO
n +
1D
On
+ 7
DO
n +
6D
On
+ 5
DO
n +
4D
On
+ 2
DO
n +
1D
On
+ 7
DO
n +
6D
On
+ 5
DO
n +
4
DO
n +
3D
O n
+ 2
DO
n +
1D
O nD
O n
+ 7
DO
n +
6D
O n
+ 5
DO n
DO
n +
3
t RPR
E
Do
n’t
Car
e
Dat
a va
lidD
ata
valid
t QH
t QH
t HZD
Q (M
AX
)
DO
n
+ 4
RL
= A
L +
CL
t DQ
SQ (
MA
X)
t LZD
Q (M
IN)
No
tes:
1.N
OP
com
man
ds
are
sho
wn
fo
r ea
se o
f ill
ust
rati
on
; oth
er c
om
man
ds
may
be
valid
at
thes
e ti
mes
.2.
The
BL8
set
tin
g is
act
ivat
ed b
y ei
ther
MR
0[1,
0]
= 0
, 0 o
r M
R0[
0, 1
] =
0, 1
an
d A
12 =
1 d
uri
ng
REA
D c
om
man
d a
tT0
.3.
DO
n =
dat
a-o
ut
fro
m c
olu
mn
n.
4.B
L8, R
L =
5 (
AL
= 0
, CL
= 5
).5.
Ou
tpu
t ti
min
gs
are
refe
ren
ced
to
VD
DQ
/2 a
nd
DLL
on
an
d lo
cked
.6.
t DQ
SQ d
efin
es t
he
skew
bet
wee
n D
QS,
DQ
S# t
o d
ata
and
do
es n
ot
def
ine
DQ
S, D
QS#
to
CK
.7.
Earl
y d
ata
tran
siti
on
s m
ay n
ot
alw
ays
hap
pen
at
the
sam
e D
Q. D
ata
tran
siti
on
s o
f a
DQ
can
be
earl
y o
r la
te w
ith
ina
bu
rst.
1Gb: x4, x8, x16 DDR3 SDRAMREAD Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 166 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Figu
re 3
9: D
ata
Outp
ut T
imin
g –
t DQS
Q an
d Da
ta V
alid
Win
dow
Notes:
1.NOPcom
mandsareshownfore
aseofillustration;othercom
mandsm
aybe
validatthesetimes.
2.TheBL8settingisactivatedbyeitherM
R0[1,0]=
0,0
orM
R0[0,1]=
0,1
and
A12
=1duringREA
Dcom
mandatT0.
3.DOn=data-outfromcolum
nn.
4.BL8,R
L=5(AL=0,CL=5).
5.Outpu
ttimingsarereferencedto
VD
DQ/2and
DLLonandlocked.
6.
t DQSQdefinestheskew
betweenDQS,D
QS#todataanddo
esnotdefine
DQS,D
QS#toCK.
7.Ea
rlydatatransitionsm
aynotalwayshapp
enatthesam
eDQ.D
atatransitions
ofaDQcanbeearlyorlatewithinaburst.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
78
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
tHZandtLZtransitionsoccurinthesameaccesstimeasvaliddatatransitions.TheseparametersarereferencedtoaspecificvoltagelevelthatspecifieswhenthedeviceoutputisnolongerdrivingtHZDQSandtHZDQ,orbeginsdrivingtLZDQS,tLZDQ.Figure41(page79)showsamethodofcalculatingthepointwhenthedeviceisnolongerdrivingtHZDQSandtHZDQ,orbeginsdrivingtLZDQS,tLZDQ,bymeasuringthesignalattwodifferent voltages. The actual voltage measurement pointsare not critical as long as the calculation is consistent. TheparameterstLZDQS,tLZDQ,tHZDQS,andtHZDQaredefinedassingle-ended.
Figure 40: Data Strobe Timing – READs
tHZ and tLZ transitions occur in the same access time as valid data transitions. Theseparameters are referenced to a specific voltage level that specifies when the device out-put is no longer driving tHZDQS and tHZDQ, or begins driving tLZDQS, tLZDQ. Fig-ure 80 (page 168) shows a method of calculating the point when the device is no longerdriving tHZDQS and tHZDQ, or begins driving tLZDQS, tLZDQ, by measuring the signalat two different voltages. The actual voltage measurement points are not critical as longas the calculation is consistent. The parameters tLZDQS, tLZDQ, tHZDQS, and tHZDQare defined as single-ended.
Figure 79: Data Strobe Timing – READs
RL measuredto this point
DQS, DQS#early strobe
CK
tLZDQS (MIN)
tHZDQS (MIN)
DQS, DQS#late strobe
tLZDQS (MAX) tHZDQS (MAX)tDQSCK (MAX) tDQSCK (MAX) tDQSCK (MAX) tDQSCK (MAX)
tDQSCK (MIN) tDQSCK (MIN) tDQSCK (MIN) tDQSCK (MIN)
CK#
tRPRE
tQSH tQSHtQSL tQSL
tQSL tQSLtQSH tQSH
Bit 0 Bit 1 Bit 2 Bit 7
tRPRE
Bit 0 Bit 1 Bit 2 Bit 7Bit 6Bit 3 Bit 4 Bit 5
Bit 6Bit 4Bit 3 Bit 5
tRPST
tRPST
T0 T1 T2 T3 T4 T5 T6
1Gb: x4, x8, x16 DDR3 SDRAMREAD Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 167 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
79
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Figure 41: Method for Calculating tLZ and tHZ
Figure 42: tRPRE Timing
Notes:
1. Withinaburst,therisingstrobeedgeisnotnecessarilyfixedattDQSCK(MIN)ortDQSCK(MAX).Instead,therisingstrobeedgecanvarybetweentDQSCK(MIN)andtDQSCK(MAX).
2. TheDQSHIGHpulsewidthisdefinedbytQSH,andtheDQSLOWpulsewidthisdefinedbytQSL.Likewise,tLZDQS(MIN)andtHZDQS(MIN)arenottiedtotDQSCK(MIN)(earlystrobe
Figure 80: Method for Calculating tLZ and tHZ
tHZDQS, tHZDQ
tHZDQS, tHZDQ end point = 2 × T1 - T2
VOH - xmV
VTT - xmV
VOL + xmV
VTT + xmVVOH - 2xmV
VTT - 2xmV
VOL + 2xmV
VTT + 2xmV
tLZDQS, tLZDQ
tLZDQS, tLZDQ begin point = 2 × T1 - T2
T1
T1T2
T2
Notes: 1. Within a burst, the rising strobe edge is not necessarily fixed at tDQSCK (MIN) or tDQSCK(MAX). Instead, the rising strobe edge can vary between tDQSCK (MIN) and tDQSCK(MAX).
2. The DQS HIGH pulse width is defined by tQSH, and the DQS LOW pulse width is definedby tQSL. Likewise, tLZDQS (MIN) and tHZDQS (MIN) are not tied to tDQSCK (MIN) (earlystrobe case), and tLZDQS (MAX) and tHZDQS (MAX) are not tied to tDQSCK (MAX) (latestrobe case); however, they tend to track one another.
3. The minimum pulse width of the READ preamble is defined by tRPRE (MIN). The mini-mum pulse width of the READ postamble is defined by tRPST (MIN).
Figure 81: tRPRE Timing
tRPREDQS - DQS#
DQS
DQS#
T1tRPRE begins
T2tRPRE ends
CK
CK#
VTT
Resulting differential signal relevant for tRPRE specification
tC
tA tB
tD
Single-ended signal providedas background information
0V
Single-ended signal providedas background information
VTT
VTT
1Gb: x4, x8, x16 DDR3 SDRAMREAD Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 168 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Figure 80: Method for Calculating tLZ and tHZ
tHZDQS, tHZDQ
tHZDQS, tHZDQ end point = 2 × T1 - T2
VOH - xmV
VTT - xmV
VOL + xmV
VTT + xmVVOH - 2xmV
VTT - 2xmV
VOL + 2xmV
VTT + 2xmV
tLZDQS, tLZDQ
tLZDQS, tLZDQ begin point = 2 × T1 - T2
T1
T1T2
T2
Notes: 1. Within a burst, the rising strobe edge is not necessarily fixed at tDQSCK (MIN) or tDQSCK(MAX). Instead, the rising strobe edge can vary between tDQSCK (MIN) and tDQSCK(MAX).
2. The DQS HIGH pulse width is defined by tQSH, and the DQS LOW pulse width is definedby tQSL. Likewise, tLZDQS (MIN) and tHZDQS (MIN) are not tied to tDQSCK (MIN) (earlystrobe case), and tLZDQS (MAX) and tHZDQS (MAX) are not tied to tDQSCK (MAX) (latestrobe case); however, they tend to track one another.
3. The minimum pulse width of the READ preamble is defined by tRPRE (MIN). The mini-mum pulse width of the READ postamble is defined by tRPST (MIN).
Figure 81: tRPRE Timing
tRPREDQS - DQS#
DQS
DQS#
T1tRPRE begins
T2tRPRE ends
CK
CK#
VTT
Resulting differential signal relevant for tRPRE specification
tC
tA tB
tD
Single-ended signal providedas background information
0V
Single-ended signal providedas background information
VTT
VTT
1Gb: x4, x8, x16 DDR3 SDRAMREAD Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 168 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
case),andtLZDQS(MAX)andtHZDQS(MAX)arenottiedtotDQSCK(MAX)(latestrobecase);however,theytendtotrackoneanother.
3. TheminimumpulsewidthoftheREADpreambleisdefinedbytRPRE(MIN).TheminimumpulsewidthoftheREADpostambleisdefinedbytRPST(MIN).
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
80
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Figure 82: tRPST Timing
tRPSTDQS - DQS#
DQS
DQS#
T1tRPST begins
T2tRPST ends
Resulting differential signal relevant for tRPST specification
CK
CK#
VTT
tC
tA
tB
tD
Single-ended signal, providedas background information
Single-ended signal, providedas background information
0V
VTT
VTT
1Gb: x4, x8, x16 DDR3 SDRAMREAD Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 169 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Figure 43: tRPST Timing
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
81
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
WRITE OperationWRITE bursts are initiated with a WRITE command. Thestarting column and bank addresses are provided with theWRITE command, and auto precharge is either enabled ordisabled for that access. If auto precharge is selected, therowbeingaccessed isprechargedat theendof theWRITEburst. If auto precharge is not selected, the rowwill remainopenforsubsequentaccesses.AfteraWRITEcommandhasbeen issued, theWRITE burst may not be interrupted. Forthe genericWRITE commands used in Figure 46 (page 83)throughFigure54(page88),autoprechargeisdisabled.
DuringWRITEbursts,thefirstvaliddata-inelementisregisteredon a rising edge of DQS following theWRITE latency (WL)clocks laterandsubsequentdataelementswillberegisteredonsuccessiveedgesofDQS.WRITElatency(WL)isdefinedasthesumofpostedCASadditivelatency(AL)andCASWRITElatency(CWL):WL=AL+CWL.ThevaluesofALandCWLareprogrammedintheMR0andMR2registers,respectively.PriortothefirstvalidDQSedge,afullcycleisneeded(includingadummycrossoverofDQS,DQS#)andspecifiedastheWRITEpreamble shown in Figure 46 (page 83). The half cycle onDQSfollowingthelastdata-inelementisknownastheWRITEpostamble.
The time between the WRITE command and the first validedge of DQS is WL clocks ±tDQSS. Figure 47 (page 84)through Figure 54 (page 88) show the nominal case wheretDQSS=0ns;however,Figure46 (page83) includes tDQSS(MIN)andtDQSS(MAX)cases.
Datamaybemasked fromcompleting aWRITE using datamask.Thedatamaskoccurson theDMball aligned to theWRITEdata.IfDMisLOW,theWRITEcompletesnormally.IfDMisHIGH,thatbitofdataismasked.
Uponcompletionof aburst, assumingnoother commandshave been initiated, the DQ will remain High-Z, and anyadditionalinputdatawillbeignored.
Data for any WRITE burst may be concatenated with asubsequent WRITE command to provide a continuousflowof inputdata.ThenewWRITEcommandcanbe tCCDclocksfollowingthepreviousWRITEcommand.Thefirstdataelement from thenewburst isappliedafter the lastelement
of a completed burst. Figure 47 (page 84) and Figure 48(page 84) show concatenated bursts. An example ofnonconsecutiveWRITEsisshowninFigure49(page85).
DataforanyWRITEburstmaybefollowedbyasubsequentREADcommandaftertWTRhasbeenmet(seeFigure50(page85),Figure51(page86),andFigure52(page87)).
DataforanyWRITEburstmaybefollowedbyasubsequentPRECHARGE command, providing tWR has been met, asshowninFigure53(page88)andFigure54(page88).
BothtWTRandtWRstartingtimemayvary,dependingonthemoderegistersettings(fixedBC4,BL8versusOTF).
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
82
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Figure 44: tWPRE Timing
Figure 45: tWPST Timing
Figure 83: tWPRE Timing
DQS - DQS#
T1tWPRE begins
T2tWPRE ends
tWPREResulting differential
signal relevant for tWPRE specification
0V
CK
CK#
VTT
Figure 84: tWPST Timing
tWPSTDQS - DQS#
T1tWPST begins
T2tWPST ends
Resulting differential signal relevant for tWPST specification
0V
CK
CK#
VTT
1Gb: x4, x8, x16 DDR3 SDRAMWRITE Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 171 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Figure 83: tWPRE Timing
DQS - DQS#
T1tWPRE begins
T2tWPRE ends
tWPREResulting differential
signal relevant for tWPRE specification
0V
CK
CK#
VTT
Figure 84: tWPST Timing
tWPSTDQS - DQS#
T1tWPST begins
T2tWPST ends
Resulting differential signal relevant for tWPST specification
0V
CK
CK#
VTT
1Gb: x4, x8, x16 DDR3 SDRAMWRITE Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 171 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
83
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Figure 85: WRITE Burst
DIn + 3
DI n + 2
DIn + 1
DIn
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
Don’t CareTransitioning Data
DIn + 7
DI n + 6
DIn + 5
DIn + 4
Bank,Col n
NOPWRITE NOPNOP NOP NOP NOP NOP NOP NOP NOP
CK
CK#
Command1
DQ3
DQS, DQS#
Address2
tWPST
tWPRE tWPST
tDQSL
DQ3
DQ3
tWPST
DQS, DQS#
DQS, DQS#
tDQSL
tWPRE
tDQSS
tDQSS tDSH tDSH tDSH tDSH
tDSS tDSS tDSS tDSS tDSS
tDSS tDSS tDSS tDSS tDSS
tDSH tDSH tDSH tDSH
tDQSLtDQSH tDQSLtDQSH tDQSLtDQSH tDQSH tDQSL
tDQSL
tDQSL
tDQSLtDQSHtDQSH
tDQSH
tDQSH
tDQSLtDQSH tDQSLtDQSH tDQSH
tDQSLtDQSH tDQSLtDQSH tDQSLtDQSH tDQSH
WL = AL + CWL
tDQSS (MIN)
tDQSS (NOM)
tDQSS (MAX)
tDQSL
tWPRE
DI n + 3
DI n + 2
DI n + 1
DI n
DIn + 7
DI n + 6
DI n + 5
DIn + 4
DIn + 3
DIn + 2
DIn + 1
DI n
DIn + 7
DIn + 6
DIn + 5
DIn + 4
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid atthese times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 duringthe WRITE command at T0.
3. DI n = data-in for column n.4. BL8, WL = 5 (AL = 0, CWL = 5).5. tDQSS must be met at each rising clock edge.6. tWPST is usually depicted as ending at the crossing of DQS, DQS#; however, tWPST ac-
tually ends when DQS no longer drives LOW and DQS# no longer drives HIGH.
1Gb: x4, x8, x16 DDR3 SDRAMWRITE Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 172 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Figure 46: WRITE Burst
Notes:
1. NOPcommandsareshownforeaseofillustration;othercommandsmaybevalidatthesetimes.
2. TheBL8settingisactivatedbyeitherMR0[1:0]=00orMR0[1:0]=01andA12=1duringtheWRITEcommandatT0.
3. DIn=data-inforcolumnn.
4. BL8,WL=5(AL=0,CWL=5).
5. tDQSSmustbemetateachrisingclockedge.
6. tWPSTisusuallydepictedasendingatthecrossingofDQS,DQS#;however,tWPSTactuallyendswhenDQSnolongerdrivesLOWandDQS#nolongerdrivesHIGH.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
84
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Fig
ure
86: C
on
secu
tive W
RIT
E (
BL8
) to
WR
ITE (
BL8
)
WL
= 5
WL
= 5
T0T1
T2T3
T4T5
T6T7
T8T9
t CC
D
t WPR
E
T10
T11
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
T12
T13
T14
Valid
Valid
NO
PW
RITE
WRI
TEN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
P
CKCK#
Com
man
d1
DQ
3
DQ
S, D
QS#
Add
ress
2
t WPS
T
t WR
t WTR
t BL
= 4
clo
cks
DI
n +
3D
I n
+ 2
DI
n +
1D
I n
DI
n +
7D
I n
+ 6
DI
n +
5D
In
+ 4
DI
b +
3D
I b
+ 2
DI
b +
1D
I b
DI
b +
7D
I b
+ 6
DI
b +
5D
Ib
+ 4
No
tes:
1.N
OP
com
man
ds
are
sho
wn
fo
r ea
se o
f ill
ust
rati
on
; oth
er c
om
man
ds
may
be
valid
at
thes
e ti
mes
.2.
The
BL8
set
tin
g is
act
ivat
ed b
y ei
ther
MR
0[1:
0] =
00
or
MR
0[1:
0] =
01
and
A12
= 1
du
rin
g t
he
WR
ITE
com
man
ds
atT0
an
d T
4.3.
DI n
(o
r b
) =
dat
a-in
fo
r co
lum
n n
(o
r co
lum
n b
).4.
BL8
, WL
= 5
(A
L =
0, C
WL
= 5
).
Fig
ure
87: C
on
secu
tive W
RIT
E (
BC
4)
to W
RIT
E (
BC
4)
via
OTF
WL
= 5
WL
= 5
T0T1
T2T3
T4T5
T6T7
T8T9
t CC
D
t WPR
E
T10
T11
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
T12
T13
T14
Valid
Valid
NO
PW
RITE
WRI
TEN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
P
CKCK#
Com
man
d1
DQ
3
DQ
S, D
QS#
Add
ress
2
t WPS
T
t WR
t WTR
t WPS
Tt W
PRE
DI
n +
3D
I n
+ 2
DI
n +
1D
I nD
I b
+ 3
DI
b +
2D
I b
+ 1
DI
b
t BL
= 4
clo
cks
No
tes:
1.N
OP
com
man
ds
are
sho
wn
fo
r ea
se o
f ill
ust
rati
on
; oth
er c
om
man
ds
may
be
valid
at
thes
e ti
mes
.2.
BC
4, W
L =
5 (
AL
= 0
, CW
L =
5).
3.D
I n (
or
b)
= d
ata-
in f
or
colu
mn
n (
or
colu
mn
b).
4.Th
e B
C4
sett
ing
is a
ctiv
ated
by
MR
0[1:
0] =
01
and
A12
= 0
du
rin
g t
he
WR
ITE
com
man
d a
t T0
an
d T
4.5.
If s
et v
ia M
RS
(fix
ed)
t WR
an
d t W
TR w
ou
ld s
tart
T11
(2
cycl
es e
arlie
r).
1Gb: x4, x8, x16 DDR3 SDRAMWRITE Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 173 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Fig
ure
86: C
on
secu
tive W
RIT
E (
BL8
) to
WR
ITE (
BL8
)
WL
= 5
WL
= 5
T0T1
T2T3
T4T5
T6T7
T8T9
t CC
D
t WPR
E
T10
T11
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
T12
T13
T14
Valid
Valid
NO
PW
RITE
WRI
TEN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
P
CKCK#
Com
man
d1
DQ
3
DQ
S, D
QS#
Add
ress
2
t WPS
T
t WR
t WTR
t BL
= 4
clo
cks
DI
n +
3D
I n
+ 2
DI
n +
1D
I n
DI
n +
7D
I n
+ 6
DI
n +
5D
In
+ 4
DI
b +
3D
I b
+ 2
DI
b +
1D
I b
DI
b +
7D
I b
+ 6
DI
b +
5D
Ib
+ 4
No
tes:
1.N
OP
com
man
ds
are
sho
wn
fo
r ea
se o
f ill
ust
rati
on
; oth
er c
om
man
ds
may
be
valid
at
thes
e ti
mes
.2.
The
BL8
set
tin
g is
act
ivat
ed b
y ei
ther
MR
0[1:
0] =
00
or
MR
0[1:
0] =
01
and
A12
= 1
du
rin
g t
he
WR
ITE
com
man
ds
atT0
an
d T
4.3.
DI n
(o
r b
) =
dat
a-in
fo
r co
lum
n n
(o
r co
lum
n b
).4.
BL8
, WL
= 5
(A
L =
0, C
WL
= 5
).
Fig
ure
87: C
on
secu
tive W
RIT
E (
BC
4)
to W
RIT
E (
BC
4)
via
OTF
WL
= 5
WL
= 5
T0T1
T2T3
T4T5
T6T7
T8T9
t CC
D
t WPR
E
T10
T11
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
T12
T13
T14
Valid
Valid
NO
PW
RITE
WRI
TEN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
P
CKCK#
Com
man
d1
DQ
3
DQ
S, D
QS#
Add
ress
2
t WPS
T
t WR
t WTR
t WPS
Tt W
PRE
DI
n +
3D
I n
+ 2
DI
n +
1D
I nD
I b
+ 3
DI
b +
2D
I b
+ 1
DI
b
t BL
= 4
clo
cks
No
tes:
1.N
OP
com
man
ds
are
sho
wn
fo
r ea
se o
f ill
ust
rati
on
; oth
er c
om
man
ds
may
be
valid
at
thes
e ti
mes
.2.
BC
4, W
L =
5 (
AL
= 0
, CW
L =
5).
3.D
I n (
or
b)
= d
ata-
in f
or
colu
mn
n (
or
colu
mn
b).
4.Th
e B
C4
sett
ing
is a
ctiv
ated
by
MR
0[1:
0] =
01
and
A12
= 0
du
rin
g t
he
WR
ITE
com
man
d a
t T0
an
d T
4.5.
If s
et v
ia M
RS
(fix
ed)
t WR
an
d t W
TR w
ou
ld s
tart
T11
(2
cycl
es e
arlie
r).
1Gb: x4, x8, x16 DDR3 SDRAMWRITE Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 173 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Figu
re 4
7: C
onse
cutiv
e W
RITE
(BL8
) to
WRI
TE (B
L8)
Figu
re 4
8: C
onse
cutiv
e W
RITE
(BC4
) to
WRI
TE (B
C4) v
ia O
TF
Notes:
1.NOPcom
mandsareshownfore
aseofillustration;othercom
mandsm
aybevalidatthesetimes.
2.TheBL8settingisactivatedbyeitherM
R0[1:0]=00orM
R0[1:0]=01andA12
=1duringtheWRITEcommandsatT
0andT4
.
3.DIn(orb
)=data-inforc
olum
nn(orc
olum
nb).
4.BL8,W
L=5(AL=0,CWL=5).
Notes:
1.NOPcom
mandsareshownfore
aseofillustration;othercom
mandsm
aybevalidatthesetimes.
2.BC4,W
L=5(AL=0,CWL=5).
3.DIn(orb
)=data-inforc
olum
nn(orc
olum
nb).
4.TheBC4settingisactivatedbyMR0[1:0]=01andA12
=0duringtheWRITEcommandatT0andT4
.
5.IfsetviaM
RS(fixed)t W
Rand
t WTR
wouldstartT11
(2cyclesearlier).
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
85
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Fig
ure
88: N
on
con
secu
tive W
RIT
E t
o W
RIT
E
CKCK#
Com
man
dN
OP
NO
PN
OP
Add
ress
DQ
DM
DQ
S, D
QS#
Tran
siti
on
ing
Dat
a
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
T0T1
T2T3
T4T5
T6T7
T8T9
T10
T11
T12
T13
T14
T15
T16
T17
NO
PW
RITE
NO
PW
RITE
Valid
Valid
NO
P
DI n
DI
n +
1D
In
+ 2
DI
n +
3D
In
+ 4
DI
n +
5D
In
+ 6
Do
n't
Car
e
DI
n +
7D
I bD
Ib
+ 1
DI
b +
2D
Ib
+ 3
DI
b +
4D
Ib
+ 5
DI
b +
6D
Ib
+ 7
WL
= C
WL
+ A
L =
7W
L =
CW
L +
AL
= 7
No
tes:
1.D
I n (
or
b)
= d
ata-
in f
or
colu
mn
n (
or
colu
mn
b).
2.Se
ven
su
bse
qu
ent
elem
ents
of
dat
a-in
are
ap
plie
d in
th
e p
rog
ram
med
ord
er f
ollo
win
g D
O n
.3.
Each
WR
ITE
com
man
d m
ay b
e to
an
y b
ank.
4.Sh
ow
n f
or
WL
= 7
(C
WL
= 7
, AL
= 0
).
Fig
ure
89: W
RIT
E (
BL8
) to
REA
D (
BL8
)
WL
= 5
T0T1
T2T3
T4T5
T6T7
T8T9
t WPR
E
T10
T11
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
Ta0
NO
PW
RITE
REA
D
Valid
Valid
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
CKCK#
Com
man
d1
DQ
4
DQ
S, D
QS#
Add
ress
3
t WPS
T
t WTR
2
Ind
icat
es b
reak
in t
ime
scal
e
DI
n +
3D
In
+ 2
DI
n +
1D
I nD
In
+ 7
DI
n +
6D
In
+ 5
DI
n +
4
No
tes:
1.N
OP
com
man
ds
are
sho
wn
fo
r ea
se o
f ill
ust
rati
on
; oth
er c
om
man
ds
may
be
valid
at
thes
e ti
mes
.2.
t WTR
co
ntr
ols
th
e W
RIT
E-to
-REA
D d
elay
to
th
e sa
me
dev
ice
and
sta
rts
wit
h t
he
firs
t ri
sin
g c
lock
ed
ge
afte
r th
e la
stw
rite
dat
a sh
ow
n a
t T9
.3.
The
BL8
set
tin
g is
act
ivat
ed b
y ei
ther
MR
0[1:
0] =
00
or
MR
0[1:
0] =
01
and
MR
0[12
] =
1 d
uri
ng
th
e W
RIT
E co
mm
and
at T
0. T
he
REA
D c
om
man
d a
t Ta
0 ca
n b
e ei
ther
BC
4 o
r B
L8, d
epen
din
g o
n M
R0[
1:0]
an
d t
he
A12
sta
tus
at T
a0.
4.D
I n =
dat
a-in
fo
r co
lum
n n
.5.
RL
= 5
(A
L =
0, C
L =
5),
WL
= 5
(A
L =
0, C
WL
= 5
).
1Gb: x4, x8, x16 DDR3 SDRAMWRITE Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 174 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Fig
ure
88: N
on
con
secu
tive W
RIT
E t
o W
RIT
E
CKCK#
Com
man
dN
OP
NO
PN
OP
Add
ress
DQ
DM
DQ
S, D
QS#
Tran
siti
on
ing
Dat
a
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
T0T1
T2T3
T4T5
T6T7
T8T9
T10
T11
T12
T13
T14
T15
T16
T17
NO
PW
RITE
NO
PW
RITE
Valid
Valid
NO
P
DI n
DI
n +
1D
In
+ 2
DI
n +
3D
In
+ 4
DI
n +
5D
In
+ 6
Do
n't
Car
e
DI
n +
7D
I bD
Ib
+ 1
DI
b +
2D
Ib
+ 3
DI
b +
4D
Ib
+ 5
DI
b +
6D
Ib
+ 7
WL
= C
WL
+ A
L =
7W
L =
CW
L +
AL
= 7
No
tes:
1.D
I n (
or
b)
= d
ata-
in f
or
colu
mn
n (
or
colu
mn
b).
2.Se
ven
su
bse
qu
ent
elem
ents
of
dat
a-in
are
ap
plie
d in
th
e p
rog
ram
med
ord
er f
ollo
win
g D
O n
.3.
Each
WR
ITE
com
man
d m
ay b
e to
an
y b
ank.
4.Sh
ow
n f
or
WL
= 7
(C
WL
= 7
, AL
= 0
).
Fig
ure
89: W
RIT
E (
BL8
) to
REA
D (
BL8
)
WL
= 5
T0T1
T2T3
T4T5
T6T7
T8T9
t WPR
E
T10
T11
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
Ta0
NO
PW
RITE
REA
D
Valid
Valid
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
CKCK#
Com
man
d1
DQ
4
DQ
S, D
QS#
Add
ress
3
t WPS
T
t WTR
2
Ind
icat
es b
reak
in t
ime
scal
e
DI
n +
3D
In
+ 2
DI
n +
1D
I nD
In
+ 7
DI
n +
6D
In
+ 5
DI
n +
4
No
tes:
1.N
OP
com
man
ds
are
sho
wn
fo
r ea
se o
f ill
ust
rati
on
; oth
er c
om
man
ds
may
be
valid
at
thes
e ti
mes
.2.
t WTR
co
ntr
ols
th
e W
RIT
E-to
-REA
D d
elay
to
th
e sa
me
dev
ice
and
sta
rts
wit
h t
he
firs
t ri
sin
g c
lock
ed
ge
afte
r th
e la
stw
rite
dat
a sh
ow
n a
t T9
.3.
The
BL8
set
tin
g is
act
ivat
ed b
y ei
ther
MR
0[1:
0] =
00
or
MR
0[1:
0] =
01
and
MR
0[12
] =
1 d
uri
ng
th
e W
RIT
E co
mm
and
at T
0. T
he
REA
D c
om
man
d a
t Ta
0 ca
n b
e ei
ther
BC
4 o
r B
L8, d
epen
din
g o
n M
R0[
1:0]
an
d t
he
A12
sta
tus
at T
a0.
4.D
I n =
dat
a-in
fo
r co
lum
n n
.5.
RL
= 5
(A
L =
0, C
L =
5),
WL
= 5
(A
L =
0, C
WL
= 5
).
1Gb: x4, x8, x16 DDR3 SDRAMWRITE Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 174 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Figu
re 4
9: N
onco
nsec
utiv
e W
RITE
to W
RITE
Figu
re 5
0: W
RITE
(BL8
) to
READ
(BL8
)
Notes:
1.DIn(orb
)=data-inforc
olum
nn(orc
olum
nb).
2.Sevensub
sequ
entelementsofd
ata-inareapp
liedinth
eprog
rammedorderfollowingDOn.
3.Ea
chW
RITEcommandmaybetoanybank.
4.ShownforW
L=7(CWL=7,AL=0).
Notes:
1.NOPcom
mandsareshownfore
aseofillustration;othercom
mandsm
aybevalidatthesetimes.
2.
t WTR
contro
lsth
eWRITE-to-REA
Ddelayto
thesamedeviceand
startswithth
efirstrisingclockedg
eafterthelastwritedatashownatT9.
3.TheBL8settingisactivatedbyeitherM
R0[1:0]=00orM
R0[1:0]=01andMR0[12
]=1duringtheWRITEcommandatT0.TheREA
Dcom
mandat
Ta0canbeeitherBC4orBL8,d
ependingonMR0[1:0]and
theA12
statusatTa0.
4.DIn=data-inforc
olum
nn.
5.RL=5(AL=0,CL=5),W
L=5(AL=0,CWL=5).
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
86
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Fig
ure
90: W
RIT
E t
o R
EA
D (
BC
4 M
od
e R
eg
iste
r Sett
ing
)
WL
= 5
T0T1
T2T3
T4T5
T6T7
T8T9
Ta0
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
NO
PW
RITE
Valid
REA
D
Valid
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
CKCK#
Com
man
d1
DQ
4
DQ
S, D
QS#
Add
ress
3
t WPS
T
t WTR
2
t WPR
E
Ind
icat
es b
reak
in t
ime
scal
e
DI
n +
3D
In
+ 2
DI
n +
1D
I n
No
tes:
1.N
OP
com
man
ds
are
sho
wn
fo
r ea
se o
f ill
ust
rati
on
; oth
er c
om
man
ds
may
be
valid
at
thes
e ti
mes
.2.
t WTR
co
ntr
ols
th
e W
RIT
E-to
-REA
D d
elay
to
th
e sa
me
dev
ice
and
sta
rts
wit
h t
he
firs
t ri
sin
g c
lock
ed
ge
afte
r th
e la
stw
rite
dat
a sh
ow
n a
t T7
.3.
The
fixe
d B
C4
sett
ing
is a
ctiv
ated
by
MR
0[1:
0] =
10
du
rin
g t
he
WR
ITE
com
man
d a
t T0
an
d t
he
REA
D c
om
man
d a
tTa
0.4.
DI n
= d
ata-
in f
or
colu
mn
n.
5.B
C4
(fix
ed),
WL
= 5
(A
L =
0, C
WL
= 5
), R
L =
5 (
AL
= 0
, CL
= 5
).
1Gb: x4, x8, x16 DDR3 SDRAMWRITE Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 175 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Figu
re 5
1: W
RITE
to R
EAD
(BC4
Mod
e Re
gist
er S
ettin
g)
Notes:
1.NOPcom
mandsareshownfore
aseofillustration;othercom
mandsm
aybevalidatthesetimes.
2.
t WTR
contro
lsth
eWRITE-to-REA
Ddelayto
thesamedeviceand
startswithth
efirstrisingclock
edgeafterthelastwritedatashownatT7.
3.ThefixedBC4settingisactivatedbyMR0[1:0]=10du
ringtheWRITEcommandatT0andthe
REA
Dcom
mandatTa0.
4.DIn=data-inforc
olum
nn.
5.BC4(fixed),W
L=5(AL=0,CWL=5),R
L=5(AL=0,CL=5).
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
87
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Figu
re 5
2: W
RITE
(BC4
OTF
) to
READ
(BC4
OTF
)
Notes:
1.NOPcom
mandsareshownfore
aseofillustration;othercom
mandsm
aybevalidatthesetimes.
2.
t WTR
contro
lsth
eWRITE-to-REA
Ddelayto
thesamedeviceand
startsaftertBL.
3.TheBC4OTFsettingisactivatedbyMR0[1:0]=01andA12
=0duringtheWRITEcommandat
T0and
theREA
Dcom
mandatT
n.
4.DIn=data-inforc
olum
nn.
5.BC4,RL=5(AL=0,CL=5),W
L=5(AL=0,CWL=5).
Fig
ure
91: W
RIT
E (
BC
4 O
TF)
to R
EA
D (
BC
4 O
TF)
WL
= 5
RL
= 5
T0T1
T2T3
T4T5
T6T7
T8T9
t WPR
E
T10
T11
Do
n’t
Car
eTr
ansi
tio
nin
g D
ata
Tn
NO
PW
RITE
REA
D
Valid
Valid
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
P
CKCK#
Com
man
d1
DQ
4
DQ
S, D
QS#
Add
ress
3
t WPS
T
t BL
= 4
clo
cks
NO
P
t WTR
2
Ind
icat
es b
reak
in t
ime
scal
e
DI
n +
3D
In
+ 2
DI
n +
1D
I n
No
tes:
1.N
OP
com
man
ds
are
sho
wn
fo
r ea
se o
f ill
ust
rati
on
; oth
er c
om
man
ds
may
be
valid
at
thes
e ti
mes
.2.
t WTR
co
ntr
ols
th
e W
RIT
E-to
-REA
D d
elay
to
th
e sa
me
dev
ice
and
sta
rts
afte
r t B
L.3.
The
BC
4 O
TF s
etti
ng
is a
ctiv
ated
by
MR
0[1:
0] =
01
and
A12
= 0
du
rin
g t
he
WR
ITE
com
man
d a
t T0
an
d t
he
REA
Dco
mm
and
at
Tn.
4.D
I n =
dat
a-in
fo
r co
lum
n n
.5.
BC
4, R
L =
5 (
AL
= 0
, CL
= 5
), W
L =
5 (
AL
= 0
, CW
L =
5).
1Gb: x4, x8, x16 DDR3 SDRAMWRITE Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 176 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
88
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Figure 92: WRITE (BL8) to PRECHARGE
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 Ta0 Ta1
DIn + 3
DIn + 2
DIn + 1
DIn
DIn + 6
DIn + 7
DIn + 5
DIn + 4
NOPWRITE
Valid
NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP PRE
CK
CK#
Command
DQ BL8
DQS, DQS#
Address
Don’t CareTransitioning DataIndicates breakin time scale
tWRWL = AL + CWL
Valid
Notes: 1. DI n = data-in from column n.2. Seven subsequent elements of data-in are applied in the programmed order following
DO n.3. Shown for WL = 7 (AL = 0, CWL = 7).
Figure 93: WRITE (BC4 Mode Register Setting) to PRECHARGE
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 Ta0 Ta1
DIn + 3
DIn + 2
DIn + 1
DIn
NOPWRITE
Valid
NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP PRE
CK
CK#
Command
DQ BC4
DQS, DQS#
Address
Don’t CareTransitioning DataIndicates breakin time scale
tWRWL = AL + CWL
Valid
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid atthese times.
2. The write recovery time (tWR) is referenced from the first rising clock edge after the lastwrite data is shown at T7. tWR specifies the last burst WRITE cycle until the PRECHARGEcommand can be issued to the same bank.
3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0.4. DI n = data-in for column n.5. BC4 (fixed), WL = 5, RL = 5.
1Gb: x4, x8, x16 DDR3 SDRAMWRITE Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 177 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Figure 92: WRITE (BL8) to PRECHARGE
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 Ta0 Ta1
DIn + 3
DIn + 2
DIn + 1
DIn
DIn + 6
DIn + 7
DIn + 5
DIn + 4
NOPWRITE
Valid
NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP PRE
CK
CK#
Command
DQ BL8
DQS, DQS#
Address
Don’t CareTransitioning DataIndicates breakin time scale
tWRWL = AL + CWL
Valid
Notes: 1. DI n = data-in from column n.2. Seven subsequent elements of data-in are applied in the programmed order following
DO n.3. Shown for WL = 7 (AL = 0, CWL = 7).
Figure 93: WRITE (BC4 Mode Register Setting) to PRECHARGE
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 Ta0 Ta1
DIn + 3
DIn + 2
DIn + 1
DIn
NOPWRITE
Valid
NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP PRE
CK
CK#
Command
DQ BC4
DQS, DQS#
Address
Don’t CareTransitioning DataIndicates breakin time scale
tWRWL = AL + CWL
Valid
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid atthese times.
2. The write recovery time (tWR) is referenced from the first rising clock edge after the lastwrite data is shown at T7. tWR specifies the last burst WRITE cycle until the PRECHARGEcommand can be issued to the same bank.
3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0.4. DI n = data-in for column n.5. BC4 (fixed), WL = 5, RL = 5.
1Gb: x4, x8, x16 DDR3 SDRAMWRITE Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 177 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Figure 53: WRITE (BL8) to PRECHARGE
Figure 54: WRITE (BC4 Mode Register Setting) to PRECHARGE
Notes:
1. DIn=data-infromcolumnn.
2. Sevensubsequentelementsofdata-inareappliedintheprogrammedorderfollowingDOn.
3. ShownforWL=7(AL=0,CWL=7).
Notes:
1. NOPcommandsareshownforeaseofillustration;othercommandsmaybevalidatthesetimes.
2. Thewriterecoverytime(tWR)isreferencedfromthefirstrisingclockedgeafterthelastwritedataisshownatT7.tWRspecifiesthelastburstWRITEcycleuntilthePRECHARGEcommandcanbeissuedtothesamebank.
3. ThefixedBC4settingisactivatedbyMR0[1:0]=10duringtheWRITEcommandatT0.
4. DIn=data-inforcolumnn.
5. BC4(fixed),WL=5,RL=5.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
89
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Figure 55: WRITE (BC4 OTF) to PRECHARGEFigure 94: WRITE (BC4 OTF) to PRECHARGE
WL = 5
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Tn
Don’t CareTransitioning Data
Bank,Col n
NOPWRITE PRENOP NOP NOP NOP NOP NOP NOPNOP
CK
CK#
Command1
DQ4
DQS, DQS#
Address3
tWPSTtWPRE
Indicates breakin time scale
DIn + 3
DIn + 2
DIn + 1
DIn
tWR2
Valid
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid atthese times.
2. The write recovery time (tWR) is referenced from the rising clock edge at T9. tWR speci-fies the last burst WRITE cycle until the PRECHARGE command can be issued to the samebank.
3. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE commandat T0.
4. DI n = data-in for column n.5. BC4 (OTF), WL = 5, RL = 5.
DQ Input Timing
Figure 85 (page 172) shows the strobe-to-clock timing during a WRITE burst. DQS,DQS# must transition within 0.25tCK of the clock transitions, as limited by tDQSS. Alldata and data mask setup and hold timings are measured relative to the DQS, DQS#crossing, not the clock crossing.
The WRITE preamble and postamble are also shown in Figure 85 (page 172). One clockprior to data input to the DRAM, DQS must be HIGH and DQS# must be LOW. Then fora half clock, DQS is driven LOW (DQS# is driven HIGH) during the WRITE preamble,tWPRE. Likewise, DQS must be kept LOW by the controller after the last data is writtento the DRAM during the WRITE postamble, tWPST.
Data setup and hold times are also shown in Figure 85 (page 172). All setup and holdtimes are measured from the crossing points of DQS and DQS#. These setup and holdvalues pertain to data input and data mask input.
Additionally, the half period of the data input strobe is specified by tDQSH and tDQSL.
1Gb: x4, x8, x16 DDR3 SDRAMWRITE Operation
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2006 Micron Technology, Inc. All rights reserved.
Notes:
1. NOPcommandsareshownforeaseofillustration;othercommandsmaybevalidatthesetimes.
2. Thewriterecoverytime(tWR)isreferencedfromtherisingclockedgeatT9.tWRspecifiesthelastburstWRITEcycleuntilthePRECHARGEcommandcanbeissuedtothesamebank.
3. TheBC4settingisactivatedbyMR0[1:0]=01andA12=0duringtheWRITEcommandatT0.
4. DIn=data-inforcolumnn.
5. BC4(OTF),WL=5,RL=5.
DQ Input Timing
Figure46 (page83)showsthestrobe-to-clock timingduringaWRITEburst.DQS,DQS#musttransitionwithin0.25tCKoftheclock transitions,as limitedby tDQSS.Alldataanddatamask setup and hold timings are measured relative to theDQS,DQS#crossing,nottheclockcrossing.
TheWRITEpreambleandpostamblearealsoshowninFigure46 (page 83). One clock prior to data input to the DRAM,DQSmustbeHIGHandDQS#mustbeLOW.Thenforahalfclock,DQSisdrivenLOW(DQS# isdrivenHIGH)duringtheWRITEpreamble,tWPRE.Likewise,DQSmustbekeptLOWby the controller after the last data is written to the DRAMduringtheWRITEpostamble,tWPST.
DatasetupandholdtimesarealsoshowninFigure46(page83).AllsetupandholdtimesaremeasuredfromthecrossingpointsofDQSandDQS#.Thesesetupandholdvaluespertaintodatainputanddatamaskinput.Additionally,thehalfperiodofthedatainputstrobeisspecifiedbytDQSHandtDQSL.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
90
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Figure 56: Data Input TimingFigure 95: Data Input Timing
tDH tDHtDS tDS
DM
DQ DIb
DQS, DQS#
Don’t CareTransitioning Data
tDQSH tDQSLtWPRE tWPST
1Gb: x4, x8, x16 DDR3 SDRAMWRITE Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 179 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
91
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
PRECHARGE OperationInputA10determineswhetheronebankor all banksare tobeprechargedand,inthecasewhereonlyonebankistobeprecharged,inputsBA[2:0]selectthebank.
When all banks are to be precharged, inputs BA[2:0] aretreatedas“Don’tCare.”Afterabankisprecharged,itisintheidlestateandmustbeactivatedpriortoanyREADorWRITEcommandsbeingissued.
SELF REFRESH OperationThe SELF REFRESH operation is initiated like a REFRESHcommand except CKE is LOW. The DLL is automaticallydisableduponenteringSELFREFRESHand isautomaticallyenabledandresetuponexitingSELFREFRESH.
Allpowersupply inputs (includingVREFCAandVREFDQ)mustbemaintained at valid levels upon entry/exit andduring selfrefreshmodeoperation.VREFDQmayfloatornotdriveVDDQ/2whileinselfrefreshmodeundercertainconditions:
• VSS<VREFDQ<VDDismaintained.
• VREFDQisvalidandstablepriortoCKEgoingbackHIGH.
• ThefirstWRITEoperationmaynotoccurearlierthan512clocksafterVREFDQisvalid.
• Allotherselfrefreshmodeexittimingrequirementsaremet.
TheDRAMmustbeidlewithallbanksintheprechargestate(tRP is satisfiedandnobursts are inprogress)beforea selfrefresh entry command can be issued. ODT must also beturned off before self refresh entry by registering the ODTball LOW prior to the self refresh entry command (see On-DieTermination (ODT) (page103) for timing requirements). IfRTT,nomandRTT(WR)aredisabledinthemoderegisters,ODTcanbea“Don’tCare.”Aftertheselfrefreshentrycommandisregistered,CKEmustbeheldLOWtokeeptheDRAMinselfrefreshmode.
After the DRAM has entered self refresh mode, all externalcontrol signals, exceptCKEandRESET#, are “Don’tCare.”TheDRAM initiatesaminimumofoneREFRESHcommandinternally within the tCKE period when it enters self refreshmode.
The requirements for entering and exiting self refreshmodedepend on the state of the clock during self refreshmode.First and foremost, the clock must be stable (meeting tCKspecifications)whenselfrefreshmodeisentered.Iftheclockremains stable and the frequency is not alteredwhile in selfrefreshmode, then theDRAM is allowed to exit self refreshmodeafter tCKESR is satisfied (CKE is allowed to transitionHIGHtCKESRlaterthanwhenCKEwasregisteredLOW).Sincethe clock remains stable in self refreshmode (no frequencychange), tCKSREand tCKSRXare not required.However, iftheclockisalteredduringselfrefreshmode(if it isturned-offoritsfrequencychanges),thentCKSREandtCKSRXmustbesatisfied.Whenenteringself refreshmode, tCKSREmustbesatisfiedpriortoalteringtheclock'sfrequency.Priortoexitingselfrefreshmode,tCKSRXmustbesatisfiedpriortoregisteringCKEHIGH.
WhenCKEisHIGHduringselfrefreshexit,NOPorDESmustbe issued for tXS time. tXS is required for thecompletionofanyinternalrefreshalreadyinprogressandmustbesatisfiedbefore a valid commandnot requiringa lockedDLLcanbeissuedto thedevice. tXS isalso theearliest timeself refreshre-entrymayoccur.BeforeacommandrequiringalockedDLLcanbeapplied,aZQCLcommandmustbeissued,tZQOPERtimingmustbemet,andtXSDLLmustbesatisfied.ODTmustbeoffduringtXSDLL.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
92
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Figure 57: Self Refresh Entry/Exit Timing
Notes:
1. Theclockmustbevalidandstable,meetingtCKspecificationsatleasttCKSREafterenteringselfrefreshmode,andatleasttCKSRXpriortoexitingselfrefreshmode,iftheclockisstoppedoralteredbetweenstatesTa0andTb0.Iftheclockremainsvalidandunchangedfromentryandduringselfrefreshmode,thentCKSREandtCKSRXdonotapply;however,tCKESRmustbesatisfiedpriortoexitingatSRX.
2. ODTmustbedisabledandRTToffpriortoenteringselfrefreshatstateT1.IfbothRTT,nomandRTT(WR)aredisabledinthemoderegisters,ODTcanbea“Don’tCare.”
3. Selfrefreshentry(SRE)issynchronousviaaREFRESHcommandwithCKELOW.
4. ANOPorDEScommandisrequiredatT2aftertheSREcommandisissuedpriortotheinputsbecoming“Don’tCare.”
Figure 96: Self Refresh Entry/Exit Timing
CK
CK#
Command NOP NOP4SRE (REF)3
Address
CKE
ODT2
RESET#2
Valid
Valid6SRX (NOP) NOP5
tRP8
tXSDLL7, 9
ODTL
tIStCPDEDtIS
tIS
Enter self refresh mode(synchronous)
Exit self refresh mode(asynchronous)
T0 T1 T2 Tc0 Tc1 Td0Tb0
Don’t Care
Te0
Valid
Valid7
Valid
Valid Valid
tIH
Ta0 Tf0
Indicates breakin time scale
tCKSRX1tCKSRE1
tXS6, 9
tCKESR (MIN)1
Notes: 1. The clock must be valid and stable, meeting tCK specifications at least tCKSRE after en-tering self refresh mode, and at least tCKSRX prior to exiting self refresh mode, if theclock is stopped or altered between states Ta0 and Tb0. If the clock remains valid andunchanged from entry and during self refresh mode, then tCKSRE and tCKSRX do notapply; however, tCKESR must be satisfied prior to exiting at SRX.
2. ODT must be disabled and RTT off prior to entering self refresh at state T1. If bothRTT,nom and RTT(WR) are disabled in the mode registers, ODT can be a “Don’t Care.”
3. Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW.4. A NOP or DES command is required at T2 after the SRE command is issued prior to the
inputs becoming “Don’t Care.”5. NOP or DES commands are required prior to exiting self refresh mode until state Te0.6. tXS is required before any commands not requiring a locked DLL.7. tXSDLL is required before any commands requiring a locked DLL.8. The device must be in the all banks idle state prior to entering self refresh mode. For
example, all banks must be precharged, tRP must be met, and no data bursts can be inprogress.
9. Self refresh exit is asynchronous; however, tXS and tXSDLL timings start at the first risingclock edge where CKE HIGH satisfies tISXR at Tc1. tCKSRX timing is also measured so thattISXR is satisfied at Tc1.
1Gb: x4, x8, x16 DDR3 SDRAMSELF REFRESH Operation
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 181 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
5. NOPorDEScommandsarerequiredpriortoexitingselfrefreshmodeuntilstateTe0.
6. tXSisrequiredbeforeanycommandsnotrequiringalockedDLL.
7. tXSDLLisrequiredbeforeanycommandsrequiringalockedDLL.
8. Thedevicemustbeintheallbanksidlestatepriortoenteringselfrefreshmode.Forexample,allbanksmustbeprecharged,tRPmustbemet,andnodataburstscanbeinprogress.
9. Selfrefreshexitisasynchronous;however,tXSandtXSDLLtimingsstartatthefirstrisingclockedgewhereCKEHIGHsatisfiestISXRatTc1.tCKSRXtimingisalsomeasuredsothattISXRissatisfiedatTc1.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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Form #: CSI-D-685 Document 007
Extended Temperature Usage
Table 29: Self Refresh Temperature and Auto Self Refresh Description
FieldMR2 Bits
Description
Self Refresh Temperature (SRT)
SRT 7
If ASR is disabled (MR2[6] = 0), SRT must be programmed to indicate TOPER during self refresh:• MR2[7] = 0: Normal operating temperature range (0°C to 85°C)• MR2[7] = 1: Extended operating temperature range (0°C to 95°C)
If ASR is enabled (MR2[7] = 1), SRT must be set to 0, even if the extended temperature range is supported• MR2[7] = 0: SRT is disabled
Auto Self Refresh (ASR)
ASR 6
When ASR is enabled, the DRAM automatically provides SELF REFRESH power management functions, (refresh rate for all supported operating temperature values).
• MR2[6] = 1: ASR is enabled (M7 must = 0)
When ASR is not enabled, the SRT bit must be programmed to indicate TOPER during SELF REFRESH operation.• MR2[6] = 0: ASR is disabled; must use manual self refresh temperature (SRT)
Table 30: Self Refresh Mode Summary
MR2[6](ASR)
MR2[7](SRT)
SELF REFRESH Operation Permitted Operating Temperature Range for Self Refresh Mode
0 0 Self refresh mode is supported in the normal temperature range Normal (0°C to 85°C)
0 1Self refresh mode is supported in normal and extended temperature ranges; When SRT is enabled, it increases self refresh power consumption
Normal and extended (0°C to 95°C)
1 0Self refresh mode is supported in normal and extended temperature ranges; Self refresh power consumption may be temperature-dependent
Normal and extended (0°C to 95°C)
1 1 Illegal
Micron’sDDR3SDRAMsupport theoptionalextendedcasetemperature (TC) range of 0°C to 95°C. Thus, theSRT andASRoptionsmustbeusedataminimum.
The extended temperature range DRAMmust be refreshedexternallyat2x(doublerefresh)anytimethecasetemperatureisabove85°C(anddoesnotexceed95°C).Theexternalrefreshrequirement is accomplished by reducing the refresh period
from64msto32ms.However,selfrefreshmoderequireseitherASRorSRTtosupporttheextendedtemperature.Thus,eitherASRorSRTmustbeenabledwhenTCisabove85°CorselfrefreshcannotbeuseduntilTCisatorbelow85°C.Table29summarizesthetwoextendedtemperatureoptionsandTable30 summarizes how the two extended temperature optionsrelatetooneanother.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
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1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Power-Down ModePower-downissynchronouslyenteredwhenCKEisregisteredLOWcoincidentwith aNOPorDEScommand.CKE is notallowed to go LOW while an MRS, MPR, ZQCAL, READ,or WRITE operation is in progress. CKE is allowed to goLOWwhile anyof theother legal operations (such asROWACTIVATION, PRECHARGE, auto precharge, or REFRESH)are inprogress.However, thepower-down IDDspecificationsare not applicable until such operations have completed.Depending on the previous DRAM state and the commandissuedpriortoCKEgoingLOW,certaintimingconstraintsmustbesatisfied(asnotedinTable31).Timingdiagramsdetailingthedifferentpower-downmodeentryandexitsareshowninFigure58(page96)throughFigure67(page100).
Table 31: Command to Power-Down Entry Parameters
DRAM Status Last Command Prior to CKE LOW1 Parameter (Min) Parameter Value Figure
Idle or active ACTIVATE tACTPDEN 1tCK Figure 65 (page 99)
Idle or active PRECHARGE tPRPDEN 1tCK Figure 66 (page 100)
Active READ or READAP tRDPDEN RL + 4tCK + 1tCK Figure 61 (page 97)
Active WRITE: BL8OTF, BL8MRS, BC4OTFtWRPDEN
WL + 4tCK + tWR/tCK Figure 62 (page 98)
Active WRITE: BC4MRS WL + 2tCK + tWR/tCK Figure 62 (page 98)
Active WRITEAP: BL8OTF, BL8MRS, BC4OTFtWRAPDEN
WL + 4tCK + WR + 1tCK Figure 63 (page 98)
Active WRITEAP: BC4MRS WL + 2tCK + WR + 1tCK Figure 63 (page 98)
Idle REFRESH tREFPDEN 1tCK Figure 64 (page 99)
Power-down REFRESH tXPDLL Greater of 10tCK or 24ns Figure 68 (page 101)
Idle MODE REGISTER SET tMRSPDEN tMOD Figure 67 (page 100)
Notes:
1. Ifslow-exitmodeprechargepower-downisenabledandentered,ODTbecomesasynchronoustANPDpriortoCKEgoingLOWandremainsasynchronousuntiltANPD+tXPDLLafterCKEgoesHIGH.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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Form #: CSI-D-685 Document 007
Power-Down Mode (continued)
Entering power-down disables the input and output buffers,excludingCK,CK#,ODT,CKE, andRESET#.NOP orDEScommandsare requireduntil tCPDEDhasbeen satisfied, atwhichtimeallspecifiedinput/outputbuffersaredisabled.TheDLLshouldbeinalockedstatewhenpower-downisenteredforthefastestpower-downexittiming.IftheDLLisnotlockedduringpower-downentry,theDLLmustberesetafterexitingpower-down mode for proper READ operation as well assynchronousODToperation.
Duringpower-downentry,ifanybankremainsopenafterallin-progresscommandsarecomplete,theDRAMwillbeinactivepower-downmode.Ifallbanksareclosedafterallin-progresscommands are complete, the DRAM will be in prechargepower-downmode. Precharge power-downmodemust beprogrammedtoexitwitheitheraslowexitmodeorafastexitmode.Whenenteringprechargepower-donmode,theDLListurnedoffinslowexitmodeorkeptoninfastexitmode.
TheDLLalsoremainsonwhenenteringactivepower-down.ODT has special timing constraints when slow exit modeprecharge power-down is enabled and entered. Refer toAsynchronousODTMode(page114)fordetailedODTusagerequirements in slow exit mode precharge power-down. Asummaryofthetwopower-downmodesislistedinTable32(page95).
Whileineitherpower-downstate,CKEisheldLOW,RESET#isheldHIGH,andastableclocksignalmustbemaintained.
ODTmust be in a valid state but all other input signals are“Don’tCare.” IfRESET#goesLOWduringpower-down, theDRAMwill switchoutofpower-downmodeandgo into thereset state. AfterCKE is registered LOW,CKEmust remainLOWuntil tPD (MIN) hasbeen satisfied.Themaximum timeallowedforpowerdowndurationistPD(MAX)(9×tREFI).
Thepower-downstatesaresynchronouslyexitedwhenCKEis registeredHIGH (witha requiredNOPorDEScommand).CKEmustbemaintainedHIGHuntiltCKEhasbeensatisfied.Avalid,executablecommandmaybeappliedafterpower-downexitlatency,tXP,andtXPDLLhavebeensatisfied.Asummaryofthepower-downmodesislistedbelow.
For specific CKE-intensive operations, such as repeating apower-down-exit-to-refreshto-power-down-entry sequence,the number of clock cycles between power-down exit andpower-down entry may not be sufficient to keep the DLLproperly updated. In addition to meeting tPD when theREFRESHcommand isusedbetweenpower-downexitandpower-downentry, twoother conditionsmust bemet. First,tXPmustbesatisfiedbeforeissuingtheREFRESHcommand.Second, tXPDLL must be satisfied before the next power-downmaybeentered.AnexampleisshowninFigure68(page101).
Table 32: Power-Down Modes
DRAM State MR0[12] DLL State Power-Down Exit Relevant Parameters
Active (any bank open) “Don’t Care” On Fast tXP to any other valid command
Precharged(all banks precharged)
1 On Fast tXP to any other valid command
0 Off SlowtXPDLL to commands that require the DLL to be locked (READ, RDAP, or ODT on); tXP to any other valid command
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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Form #: CSI-D-685 Document 007
Figure 98: Precharge Power-Down (Fast-Exit Mode) Entry and Exit
CK
CK#
Command NOP NOP NOP NOP
CKE
tCK
tCH
tCL
Enter power-downmode
Exit power-downmode
tPD
Valid
tCPDED
tIS
tIHt
IS
T0 T1 T2 T3 T4 T5 Ta0 Ta1
NOP
Don’t CareIndicates breakin time scale
tXP
tCKE (MIN)
Figure 99: Precharge Power-Down (Slow-Exit Mode) Entry and Exit
CK
CK#
Command NOP NOP NOP
CKE
tCK tCH tCL
Enter power-downmode
Exit power-downmode
tPD
Valid2Valid1PRE
tXPDLL
tCPDED
tIS
tIHtIS
T0 T1 T2 T3 T4 Ta Ta1 Tb
NOP
Don’t CareIndicates breakin time scale
tXP
tCKE (MIN)
Notes: 1. Any valid command not requiring a locked DLL.2. Any valid command requiring a locked DLL.
1Gb: x4, x8, x16 DDR3 SDRAMPower-Down Mode
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Figure 97: Active Power-Down Entry and Exit
CK
CK#
Command NOP NOP NOP NOP
Address
CKE
tCK tCH tCL
Enter power-downmode
Exit power-downmode
Don’t Care
ValidValid
Valid
tCPDED
Valid
tIS
tIH
tIH
tIS
T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4
NOP
tXP
tCKE (MIN)
Indicates breakin time scale
tPD
1Gb: x4, x8, x16 DDR3 SDRAMPower-Down Mode
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Figure 58: Active Power-Down Entry and Exit
Figure 59: Precharge Power-Down (Fast-Exit Mode) Entry and Exit
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Form #: CSI-D-685 Document 007
Figure 60: Precharge Power-Down (Slow-Exit Mode) Entry and Exit
Figure 61: Power-Down Entry After READ or READ with Auto Precharge (RDAP)
Figure 98: Precharge Power-Down (Fast-Exit Mode) Entry and Exit
CK
CK#
Command NOP NOP NOP NOP
CKE
tCK
tCH
tCL
Enter power-downmode
Exit power-downmode
tPD
Valid
tCPDED
tIS
tIHt
IS
T0 T1 T2 T3 T4 T5 Ta0 Ta1
NOP
Don’t CareIndicates breakin time scale
tXP
tCKE (MIN)
Figure 99: Precharge Power-Down (Slow-Exit Mode) Entry and Exit
CK
CK#
Command NOP NOP NOP
CKE
tCK tCH tCL
Enter power-downmode
Exit power-downmode
tPD
Valid2Valid1PRE
tXPDLL
tCPDED
tIS
tIHtIS
T0 T1 T2 T3 T4 Ta Ta1 Tb
NOP
Don’t CareIndicates breakin time scale
tXP
tCKE (MIN)
Notes: 1. Any valid command not requiring a locked DLL.2. Any valid command requiring a locked DLL.
1Gb: x4, x8, x16 DDR3 SDRAMPower-Down Mode
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Figure 100: Power-Down Entry After READ or READ with Auto Precharge (RDAP)
T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9
Don’t CareTransitioning Data
Ta10 Ta11 Ta12
NOP
Valid
READ/RDAP NOP NOP NOP NOP NOP NOP NOP NOP NOP
CK
CK#
Command
DQ BL8
DQ BC4
DQS, DQS#
Address
CKE
tCPDEDtIS
tPD
Power-down orself refresh entry
Indicates breakin time scale
tRDPDEN
DIn + 3
DIn + 1
DIn + 2
DIn
RL = AL + CL
DIn + 3
DIn + 2
DIn + 1
DIn
DIn + 6
DIn + 7
DIn+ 5
DIn + 4
Figure 101: Power-Down Entry After WRITE
T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 Tb1 Tb2 Tb3 Tb4
NOPWRITE
Valid
NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
CK
CK#
Command
DQ BL8
DQ BC4
DQS, DQS#
Address
CKE
tCPDED
Power-down orself refresh entry1
Don’t CareTransitioning Data
tWRPDEN
DIn + 3
DIn + 1
DIn + 2
DIn
tPD
Indicates breakin time scale
DI n + 3
DI n + 2
DI n + 1
DI n
DI n + 6
DI n + 7
DI n + 5
DI n + 4
tIS
WL = AL + CWL tWR
Note: 1. CKE can go LOW 2tCK earlier if BC4MRS.
1Gb: x4, x8, x16 DDR3 SDRAMPower-Down Mode
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Notes:
1. AnyvalidcommandnotrequiringalockedDLL.
2. AnyvalidcommandrequiringalockedDLL.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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Form #: CSI-D-685 Document 007
Figure 102: Power-Down Entry After WRITE with Auto Precharge (WRAP)
T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 Tb1
Don’t CareTransitioning Data
Tb2 Tb3 Tb4
NOPWRAP
Valid
NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
CK
CK#
Command
DQ BL8
DQ BC4
DQS, DQS#
Address
A10
CKE
tPD
tWRAPDEN
Power-down orself refresh entry2
Start internalprecharge
tCPDEDtIS
Indicates breakin time scale
DI n + 3
DI n + 2
DI n + 1
DIn
DI n + 6
DI n + 7
DI n + 5
DI n + 4
DI n + 3
DI n + 2
DI n + 1
DI n
WR1WL = AL + CWL
Notes: 1. tWR is programmed through MR0[11:9] and represents tWRmin (ns)/tCK rounded up tothe next integer tCK.
2. CKE can go LOW 2tCK earlier if BC4MRS.
Figure 103: REFRESH to Power-Down Entry
CK
CK#
Command REFRESH NOP NOP NOP NOP Valid
CKE
tCK tCH tCL
tCPDED
tREFPDEN
tIS
T0 T1 T2 T3 Ta0 Ta1 Ta2 Tb0
tXP (MIN)
tRFC (MIN)1
Don’t CareIndicates breakin time scale
tCKE (MIN)
tPD
Note: 1. After CKE goes HIGH during tRFC, CKE must remain HIGH until tRFC is satisfied.
1Gb: x4, x8, x16 DDR3 SDRAMPower-Down Mode
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Figure 100: Power-Down Entry After READ or READ with Auto Precharge (RDAP)
T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9
Don’t CareTransitioning Data
Ta10 Ta11 Ta12
NOP
Valid
READ/RDAP NOP NOP NOP NOP NOP NOP NOP NOP NOP
CK
CK#
Command
DQ BL8
DQ BC4
DQS, DQS#
Address
CKE
tCPDEDtIS
tPD
Power-down orself refresh entry
Indicates breakin time scale
tRDPDEN
DIn + 3
DIn + 1
DIn + 2
DIn
RL = AL + CL
DIn + 3
DIn + 2
DIn + 1
DIn
DIn + 6
DIn + 7
DIn+ 5
DIn + 4
Figure 101: Power-Down Entry After WRITE
T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 Tb1 Tb2 Tb3 Tb4
NOPWRITE
Valid
NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
CK
CK#
Command
DQ BL8
DQ BC4
DQS, DQS#
Address
CKE
tCPDED
Power-down orself refresh entry1
Don’t CareTransitioning Data
tWRPDEN
DIn + 3
DIn + 1
DIn + 2
DIn
tPD
Indicates breakin time scale
DI n + 3
DI n + 2
DI n + 1
DI n
DI n + 6
DI n + 7
DI n + 5
DI n + 4
tIS
WL = AL + CWL tWR
Note: 1. CKE can go LOW 2tCK earlier if BC4MRS.
1Gb: x4, x8, x16 DDR3 SDRAMPower-Down Mode
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Figure 62: Power-Down Entry After WRITE
Figure 63: Power-Down Entry After WRITE with Auto Precharge (WRAP)
Note:
1. CKEcangoLOW2tCKearlierifBC4MRS.
Notes:
1. tWRisprogrammedthroughMR0[11:9]andrepresentstWRmin(ns)/tCKroundeduptothenextintegertCK.
2. CKEcangoLOW2tCKearlierifBC4MRS.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
99
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Figure 64: REFRESH to Power-Down Entry
Figure 65: ACTIVATE to Power-Down Entry
Figure 102: Power-Down Entry After WRITE with Auto Precharge (WRAP)
T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 Tb1
Don’t CareTransitioning Data
Tb2 Tb3 Tb4
NOPWRAP
Valid
NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
CK
CK#
Command
DQ BL8
DQ BC4
DQS, DQS#
Address
A10
CKE
tPD
tWRAPDEN
Power-down orself refresh entry2
Start internalprecharge
tCPDEDtIS
Indicates breakin time scale
DI n + 3
DI n + 2
DI n + 1
DIn
DI n + 6
DI n + 7
DI n + 5
DI n + 4
DI n + 3
DI n + 2
DI n + 1
DI n
WR1WL = AL + CWL
Notes: 1. tWR is programmed through MR0[11:9] and represents tWRmin (ns)/tCK rounded up tothe next integer tCK.
2. CKE can go LOW 2tCK earlier if BC4MRS.
Figure 103: REFRESH to Power-Down Entry
CK
CK#
Command REFRESH NOP NOP NOP NOP Valid
CKE
tCK tCH tCL
tCPDED
tREFPDEN
tIS
T0 T1 T2 T3 Ta0 Ta1 Ta2 Tb0
tXP (MIN)
tRFC (MIN)1
Don’t CareIndicates breakin time scale
tCKE (MIN)
tPD
Note: 1. After CKE goes HIGH during tRFC, CKE must remain HIGH until tRFC is satisfied.
1Gb: x4, x8, x16 DDR3 SDRAMPower-Down Mode
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Figure 104: ACTIVATE to Power-Down Entry
CK
CK#
Command
Address
ACTIVE NOP NOP
CKE
tCK tCH tCL
Don’t Care
tCPDED
tACTPDEN
Valid
tIS
T0 T1 T2 T3 T4 T5 T6 T7
tPD
Figure 105: PRECHARGE to Power-Down Entry
CK
CK#
Command
Address
CKE
tCK tCH tCL
Don’t Care
tCPDED
tPREPDEN
tIS
T0 T1 T2 T3 T4 T5 T6 T7
tPD
All/singlebank
PRE NOP NOP
1Gb: x4, x8, x16 DDR3 SDRAMPower-Down Mode
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Note:
1. AfterCKEgoesHIGHduringtRFC,CKEmustremainHIGHuntiltRFCissatisfied.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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100
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Figure 66: PRECHARGE to Power-Down Entry
Figure 67: MRS Command to Power-Down Entry
Figure 104: ACTIVATE to Power-Down Entry
CK
CK#
Command
Address
ACTIVE NOP NOP
CKE
tCK tCH tCL
Don’t Care
tCPDED
tACTPDEN
Valid
tIS
T0 T1 T2 T3 T4 T5 T6 T7
tPD
Figure 105: PRECHARGE to Power-Down Entry
CK
CK#
Command
Address
CKE
tCK tCH tCL
Don’t Care
tCPDED
tPREPDEN
tIS
T0 T1 T2 T3 T4 T5 T6 T7
tPD
All/singlebank
PRE NOP NOP
1Gb: x4, x8, x16 DDR3 SDRAMPower-Down Mode
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Figure 106: MRS Command to Power-Down Entry
CK
CK#
CKE
tCK tCH tCL tCPDED
Address
tIS
T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4
tPD
Don’t CareIndicates breakin time scale
Valid
Command MRS NOPNOP NOP NOP NOP
tMRSPDEN
Figure 107: Power-Down Exit to Refresh to Power-Down Entry
CK
CK#
CKE
tCK tCH tCL
Enter power-downmode
Enter power-downmode
Exit power-downmode
tPD
tCPDED
tIS
tIHtIS
T0 T1 T2 T3 T4 Ta0 Ta1 Tb0
Don’t CareIndicates breakin time scale
Command NOP NOP NOP NOPREFRESH NOPNOP
tXP1
tXPDLL2
Notes: 1. tXP must be satisfied before issuing the command.2. tXPDLL must be satisfied (referenced to the registration of power-down exit) before the
next power-down can be entered.
1Gb: x4, x8, x16 DDR3 SDRAMPower-Down Mode
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MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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Form #: CSI-D-685 Document 007
Figure 68: Power-Down Exit to Refresh to Power-Down Entry
Figure 106: MRS Command to Power-Down Entry
CK
CK#
CKE
tCK tCH tCL tCPDED
Address
tIS
T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4
tPD
Don’t CareIndicates breakin time scale
Valid
Command MRS NOPNOP NOP NOP NOP
tMRSPDEN
Figure 107: Power-Down Exit to Refresh to Power-Down Entry
CK
CK#
CKE
tCK tCH tCL
Enter power-downmode
Enter power-downmode
Exit power-downmode
tPD
tCPDED
tIS
tIHtIS
T0 T1 T2 T3 T4 Ta0 Ta1 Tb0
Don’t CareIndicates breakin time scale
Command NOP NOP NOP NOPREFRESH NOPNOP
tXP1
tXPDLL2
Notes: 1. tXP must be satisfied before issuing the command.2. tXPDLL must be satisfied (referenced to the registration of power-down exit) before the
next power-down can be entered.
1Gb: x4, x8, x16 DDR3 SDRAMPower-Down Mode
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Notes:
1. tXPmustbesatisfiedbeforeissuingthecommand.
2. tXPDLLmustbesatisfied(referencedtotheregistrationofpower-downexit)beforethenextpower-downcanbeentered.
RESET OperationTheRESETsignal (RESET#) isanasynchronousresetsignalthattriggersanytimeitdropsLOW,andtherearenorestrictionsaboutwhenitcangoLOW.AfterRESET#goesLOW,itmustremain LOW for 100ns. During this time, the outputs aredisabled,ODT(RTT) turnsoff (High-Z),andtheDRAMresetsitself. CKE should be driven LOW prior to RESET# beingdrivenHIGH.AfterRESET#goesHIGH, theDRAMmustbere-initializedasthoughanormalpower-upwasexecuted.Allrefreshcounterson theDRAMare reset,anddatastored intheDRAMisassumedunknownafterRESET#hasgoneLOW.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
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1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Figure 69: RESET SequenceFigure 108: RESET Sequence
CKE
RTT
BA[2:0]
All voltagesupplies validand stable
High-Z
DM
DQSHigh-Z
Address
A10
CK
CK#
tCL
Command NOP
T0 Ta0
Don’t Care
tCL
ODT
DQ High-Z
Tb0
tDLLK
MR1 withDLL ENABLE
MRSMRS
BA0 = HBA1 = LBA2 = L
BA0 = LBA1 = LBA2 = L
Code Code
Code Code
Valid
Valid
Valid
Valid
Normaloperation
MR2 MR3
MRSMRS
BA0 = LBA1 = HBA2 = L
BA0 = HBA1 = HBA2 = L
Code Code
Code Code
Tc0 Td0
RESET#
Stable andvalid clock
Valid Valid
DRAM readyfor externalcommands
T1
tZQinit
A10 = H
ZQCL
tIS
Valid
Valid
System RESET(warm boot)
ZQCALMR0 withDLL RESET
T = 10ns (MIN)
T = 100ns (MIN)
Indicates breakin time scale
T = 500μs (MIN) tXPR tMRD tMRD tMRD tMOD
tCK
t CKSRX1
tIOZ = 20ns
tIS
tIS
Static LOW in case RTT_Nom is enabled at time Ta0, otherwise static High or Low
tIS
Note: 1. The minimum time required is the longer of 10ns or 5 clocks.
1Gb: x4, x8, x16 DDR3 SDRAMRESET Operation
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2006 Micron Technology, Inc. All rights reserved.
Note:
1. Theminimumtimerequiredisthelongerof10nsor5clocks.
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On-Die Termination (ODT)On-dietermination(ODT)isafeaturethatenablestheDRAMtoenable/disableandturnon/offterminationresistanceforeachDQ,UDQS,UDQS#,LDQS,LDQS#,UDM,andLDMsignalforthex16configuration.
ODT is designed to improve signal integrity of the memorychannel by enabling the DRAM controller to independentlyturnon/offtheDRAM’sinternalterminationresistanceforanygroupingofDRAMdevices.ODTisnotsupportedduringDLLdisablemode(simplefunctionalrepresentationshownbelow).TheswitchisenabledbytheinternalODTcontrollogic,whichusestheexternalODTballandothercontrolinformation.
On-Die Termination (ODT)On-die termination (ODT) is a feature that enables the DRAM to enable/disable andturn on/off termination resistance for each DQ, DQS, DQS#, and DM for the x4 and x8configurations (and TDQS, TDQS# for the x8 configuration, when enabled). ODT is ap-plied to each DQ, UDQS, UDQS#, LDQS, LDQS#, UDM, and LDM signal for the x16 con-figuration.
ODT is designed to improve signal integrity of the memory channel by enabling theDRAM controller to independently turn on/off the DRAM’s internal termination resist-ance for any grouping of DRAM devices. ODT is not supported during DLL disablemode (simple functional representation shown below). The switch is enabled by the in-ternal ODT control logic, which uses the external ODT ball and other control informa-tion.
Figure 109: On-Die Termination
ODTVDDQ/2
RTT
SwitchDQ, DQS, DQS#, DM, TDQS, TDQS#
To othercircuitrysuch asRCV, . . .
Functional Representation of ODT
The value of RTT (ODT termination resistance value) is determined by the settings ofseveral mode register bits (see Table 87 (page 196)). The ODT ball is ignored while inself refresh mode (must be turned off prior to self refresh entry) or if mode registersMR1 and MR2 are programmed to disable ODT. ODT is comprised of nominal ODT anddynamic ODT modes and either of these can function in synchronous or asynchronousmode (when the DLL is off during precharge power-down or when the DLL is synchro-nizing). Nominal ODT is the base termination and is used in any allowable ODT state.Dynamic ODT is applied only during writes and provides OTF switching from no RTT orRTT,nom to RTT(WR).
The actual effective termination, RTT(EFF), may be different from RTT targeted due tononlinearity of the termination. For RTT(EFF) values and calculations, see ODT Charac-teristics (page 57).
Nominal ODT
ODT (NOM) is the base termination resistance for each applicable ball; it is enabled ordisabled via MR1[9, 6, 2] (see Mode Register 1 (MR1) Definition), and it is turned on oroff via the ODT ball.
1Gb: x4, x8, x16 DDR3 SDRAMOn-Die Termination (ODT)
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 193 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Functional Representation of ODT
The value of RTT (ODT termination resistance value) isdeterminedbythesettingsofseveralmoderegisterbits(seeTable 36 (page 107)). The ODT ball is ignored while in selfrefreshmode(mustbeturnedoffpriortoselfrefreshentry)orifmoderegistersMR1andMR2areprogrammedtodisableODT.ODT is comprisedof nominalODTanddynamicODTmodes and either of these can function in synchronous orasynchronousmode (when the DLL is off during prechargepower-downorwhentheDLLissynchronizing).NominalODTisthebaseterminationandisusedinanyallowableODTstate.DynamicODTisappliedonlyduringwritesandprovidesOTFswitchingfromnoRTTorRTT,nomtoRTT(WR).
Theactualeffectivetermination,RTT(EFF),maybedifferentfromRTTtargetedduetononlinearityofthetermination.ForRTT(EFF)valuesandcalculations,seeODTCharacteristics(page17).
Nominal ODT
ODT (NOM) is the base termination resistance for eachapplicableball;itisenabledordisabledviaMR1[9,6,2](seeModeRegister1(MR1)Definition),anditisturnedonoroffviatheODTball.
Figure 70: On-Die Termination
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1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Table 33: Truth Table – ODT (Nominal)
Note1appliestotheentiretable.
MR1[9, 6, 2] ODT Pin DRAM Termination State DRAM State Notes
0 0 RTT,nom disabled, ODT off Any valid 2
0 1 RTT,nom disabled, ODT on Any valid except self refresh, read 3
000–101 0 RTT,nom enabled, ODT off Any valid 2
000–101 1 RTT,nom enabled, ODT on Any valid except self refresh, read 3
110 and 111 X RTT,nom reserved, ODT on or off Illegal
Notes:
1. AssumesdynamicODTisdisabled(seeDynamicODT(page106)whenenabled).
2. ODTisenabledandactiveduringmostwritesforpropertermination,butitisnotillegalforittobeoffduringwrites.
3. ODTmustbedisabledduringreads.TheRTT,nomvalueisrestrictedduringwrites.DynamicODTisapplicableifenabled.
NominalODT resistanceRTT,nom isdefinedbyMR1[9,6,2],as shown inModeRegister 1 (MR1)Definition. TheRTT,nomtermination value applies to the output pins previouslymentioned. DDR3SDRAM supportsmultiple RTT,nom valuesbasedonRZQ/nwherencanbe2,4,6,8,or12andRZQis240Ω.RTT,nomterminationisallowedanytimeaftertheDRAMis initialized, calibrated, and not performing read access, orwhenitisnotinselfrefreshmode.
Write accesses use RTT,nom if dynamic ODT (RTT(WR)) isdisabled.IfRTT,nomisusedduringwrites,onlyRZQ/2,RZQ/4,and RZQ/6 are allowed (see Table 37 (page 107)). ODTtimings are summarized in Table 34 (page 105), as well aslistedinTable19(page23).
Examples of nominal ODT timing are shown in conjunctionwiththesynchronousmodeofoperationinSynchronousODTMode(page112).
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1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Table 34: ODT Parameters
Symbol Description Begins at Defined toDefinition for All DDR3L Speed Bins
Unit
ODTLon ODT synchronous turn-on delay ODT registered HIGH RTT(ON) ±tAON CWL + AL - 2 tCK
ODTLoff ODT synchronous turn-off delay ODT registered HIGH RTT(OFF) ±tAOF CWL + AL - 2 tCK
tAONPD ODT asynchronous turn-on delay ODT registered HIGH RTT(ON) 2–8.5 ns
tAOFPD ODT asynchronous turn-off delay ODT registered HIGH RTT(OFF) 2–8.5 ns
ODTH4ODT minimum HIGH time after ODT assertion or write (BC4)
ODT registered HIGH or write registration with ODT HIGH
ODT registered LOW 4tCK tCK
ODTH8 ODT minimum HIGH time after write (BL8) Write registration with ODT HIGH ODT registered LOW 6tCK tCK
tAON ODT turn-on relative to ODTLon completion Completion of ODTLon RTT(ON) See Table 19 (page 23) ps
tAOF ODT turn-off relative to ODTLoff completion Completion of ODTLoff RTT(OFF) 0.5tCK ± 0.2tCK tCK
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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106
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Dynamic ODTIn certain application cases, and to further enhance signalintegrity on the data bus, it is desirable that the terminationstrengthoftheDDR3SDRAMcanbechangedwithoutissuinganMRScommand,essentiallychangingtheODTterminationon the fly. With dynamic ODT RTT(WR) enabled, the DRAMswitchesfromnominalODTRTT,nomtodynamicODTRTT(WR)when beginning a WRITE burst and subsequently switchesbacktonominalODTRTT,nomatthecompletionoftheWRITEburst. This requirement is supported by the dynamic ODTfeature,asdescribedbelow.
Dynamic ODT Special Use Case
WhenDDR3devices are architect as a single rankmemoryarray,dynamicODToffersaspecialusecase:theODTballcanbewiredhigh(viaacurrentlimitingresistorpreferred)byhavingRTT,nomdisabledviaMR1andRTT(WR)enabledviaMR2.ThiswillallowtheODTsignalnottohavetoberoutedyettheDRAMcanprovideODTcoverageduringwriteaccesses.
Whenenablingthisspecialusecase,somestandardODTspecconditionsmaybeviolated:ODTissometimessupposetobeheldlow.SuchODTspecviolation(ODTnotLOW)isallowedunderthisspecialusecase.Mostnotably,ifWriteLevelingisused,thiswouldappeartobeaproblemsinceRTT(WR)cannotbeused (shouldbedisabled)andRTT(NOM)shouldbeused.ForWrite levelingduring thisspecialusecase,with theDLLlocked, then RTT(NOM) maybe enabled when entering WriteLevelingmodeanddisabledwhenexitingWriteLevelingmode.More so, RTT(NOM) must be enabled when enabling WriteLeveling, via sameMR1 load, and disabled when disablingWriteLeveling,viasameMR1loadifRTT(NOM)istobeused.
ODTwillturn-onwithinadelayofODTLon+tAON+tMOD+1CK(enablingviaMR1)or turn-offwithinadelayofODTLoff+tAOF+tMOD+1CK.Asseeninthetablebelow,betweentheLoadModeofMR1andthepreviouslyspecifieddelay,thevalueofODTisuncertain.thismeanstheDQODTterminationcould turn-on and then turn-off again during the period ofstateduncertainty.
Table 35: Write Leveling with Dynamic ODT Special Case
Begin RTT,nom Uncertainty End RTT,nom Uncertainty I/Os RTT,nom Final State
MR1 load mode command: Enable Write Leveling and RTT(NOM)
ODTLon + tAON + tMOD + 1CKDQS, DQS# Drive RTT,nom value
DQs No RTT,nom
MR1 load mode command: Disable Write Leveling and RTT(NOM)
ODTLoff + tAOFF + tMOD + 1CKDQS, DQS# No RTT,nom
DQs No RTT,nom
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Functional Description
ThedynamicODTmodeisenabledifeitherMR2[9]orMR2[10]issetto1.DynamicODTisnotsupportedduringDLLdisablemodesoRTT(WR)mustbedisabled.ThedynamicODTfunctionisdescribedbelow:
• TwoRTTvaluesareavailable—RTT,nomandRTT(WR).
• ThevalueforRTT,nomispreselectedviaMR1[9,6,2].
• ThevalueforRTT(WR)ispreselectedviaMR2[10,9].
• DuringDRAMoperationwithoutREADorWRITEcommands,theterminationiscontrolled.
• NominalterminationstrengthRTT,nomisused.
• Terminationon/offtimingiscontrolledviatheODTballandlatenciesODTLonandODTLoff.
• WhenaWRITEcommand(WR,WRAP,WRS4,WRS8,WRAPS4,WRAPS8)isregistered,andifdynamicODT
isenabled,theODTterminationiscontrolled.
• AlatencyofODTLcnwaftertheWRITEcommand:terminationstrengthRTT,nomswitchestoRTT(WR)
• AlatencyofODTLcwn8(forBL8,fixedorOTF)orODTLcwn4(forBC4,fixedorOTF)aftertheWRITEcommand:terminationstrengthRTT(WR)switchesbacktoRTT,nom.
• On/offterminationtimingiscontrolledviatheODTballanddeterminedbyODTLon,ODTLoff,ODTH4,andODTH8.
• DuringthetADCtransitionwindow,thevalueofRTTisundefined.
ODT isconstrainedduringwritesandwhendynamicODT isenabled (seeTable36).ODTtimings listed inTable34 (page105)alsoapplytodynamicODTmode.
Table 36: Dynamic ODT Specific Parameters
Symbol Description Begins at Defined toDefinition for All DDR3L
Speed BinsUnit
ODTLcnw Change from RTT,nom to RTT(WR) Write registration RTT switched from RTT,nom to RTT(WR) WL - 2 tCK
ODTLcwn4 Change from RTT(WR) to RTT,nom (BC4) Write registration RTT switched from RTT(WR) to RTT,nom 4tCK + ODTL off tCK
ODTLcwn8 Change from RTT(WR) to RTT,nom (BL8) Write registration RTT switched from RTT(WR) to RTT,nom 6tCK + ODTL off tCK
tADC RTT change skew ODTLcnw completed RTT transition complete 0.5tCK ± 0.2tCK tCK
Table 37: Mode Registers for RTT,nom
MR1 (RTT,nom)RTT,nom (RZQ) RTT,nom (Ohm)
RTT,nom Mode RestrictionM9 M6 M2
0 0 0 Off Off n/a
0 0 1 RZQ/4 60 Self refresh
0 1 0 RZQ/2 120
0 1 1 RZQ/6 40
1 0 0 RZQ/12 20 Self refresh, write
1 0 1 RZQ/8 30
1 1 0 Reserved Reserved n/a
1 1 1 Reserved Reserved n/a
Note:1.RZQ=240Ω.IfRTT,nomisusedduringWRITEs,onlyRZQ/2,RZQ/4,RZQ/6areallowed.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Table 38: Mode Registers for RTT(WR)
MR2 (RTT(WR))RTT(WR) (RZQ) RTT(WR) (Ohm)
M10 M9
0 0 Dynamic ODT off: WRITE does not affect RTT,nom
0 1 RZQ/4 60
1 0 RZQ/2 120
1 1 Reserved Reserved
Table 39: Timing Diagrams for Dynamic ODT
Figure and Page Title
Figure 71 (page 109) Dynamic ODT: ODT Asserted Before and After the WRITE, BC4
Figure 72 (page 109) Dynamic ODT: Without WRITE Command
Figure 73 (page 110) Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8
Figure 74 (page 111) Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
Figure 75 (page 111) Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
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109
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Fig
ure
110: D
yn
am
ic O
DT:
OD
T A
ssert
ed
Befo
re a
nd
Aft
er
the W
RIT
E, B
C4
T0T1
T2T3
T4T5
T6T7
T8T9
OD
TLo
nO
DTL
cwn
4
OD
TLcn
w
WL
OD
TLo
ff
T10
T11
T12
T13
T14
T15
T17
T16
CKCK#
Com
man
d
Add
ress
R TT
OD
T
DQ
DQ
S, D
QS#
Valid
WRS
4N
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
Do
n’t
Car
eTr
ansi
tio
nin
g
R TT(W
R)R TT
,nom
R TT,n
om
DI
n +
3D
In
+ 2
DI
n +
1D
I n
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
OD
TH4
OD
TH4
t AO
N (
MIN
)t A
DC
(M
IN)
t AD
C (
MIN
)t A
OF
(MIN
)
t AO
N (
MA
X)
t AD
C (
MA
X)
t AD
C (
MA
X)
t AO
F (M
AX
)
No
tes:
1.V
ia M
RS
or
OTF
. AL
= 0
, CW
L =
5. R
TT,n
om
an
d R
TT(W
R) a
re e
nab
led
.2.
OD
TH4
app
lies
to f
irst
reg
iste
rin
g O
DT
HIG
H a
nd
th
en t
o t
he
reg
istr
atio
n o
f th
e W
RIT
E co
mm
and
. In
th
is e
xam
ple
,O
DTH
4 is
sat
isfi
ed if
OD
T g
oes
LO
W a
t T8
(fo
ur
clo
cks
afte
r th
e W
RIT
E co
mm
and
).
Fig
ure
111: D
yn
am
ic O
DT:
Wit
ho
ut
WR
ITE C
om
man
d
T0T1
T2T3
T4T5
T6T7
T8T9
OD
TLo
ff
T10
T11
CKCK#
R TT
Do
n’t
Car
eTr
ansi
tio
nin
g
Com
man
dV
alid
Val
idV
alid
Val
idV
alid
Val
idV
alid
Val
idV
alid
Val
idV
alid
Val
id
Add
ress
DQ
S, D
QS#
DQ
OD
TH4
OD
TLo
n
t AO
N (
MA
X)
t AO
N (
MIN
)
t AO
F (M
IN)
t AO
F (M
AX
)
OD
T
R TT,n
om
No
tes:
1.A
L =
0, C
WL
= 5
. RTT
,no
m is
en
able
d a
nd
RTT
(WR
) is
eith
er e
nab
led
or
dis
able
d.
2.O
DTH
4 is
def
ined
fro
m O
DT
reg
iste
red
HIG
H t
o O
DT
reg
iste
red
LO
W; i
n t
his
exa
mp
le, O
DTH
4 is
sat
isfi
ed. O
DT
reg
-is
tere
d L
OW
at
T5 is
als
o le
gal
.
1Gb: x4, x8, x16 DDR3 SDRAMDynamic ODT
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 198 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Fig
ure
110: D
yn
am
ic O
DT:
OD
T A
ssert
ed
Befo
re a
nd
Aft
er
the W
RIT
E, B
C4
T0T1
T2T3
T4T5
T6T7
T8T9
OD
TLo
nO
DTL
cwn
4
OD
TLcn
w
WL
OD
TLo
ff
T10
T11
T12
T13
T14
T15
T17
T16
CKCK#
Com
man
d
Add
ress
R TT
OD
T
DQ
DQ
S, D
QS#
Valid
WRS
4N
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
Do
n’t
Car
eTr
ansi
tio
nin
g
R TT(W
R)R TT
,nom
R TT,n
om
DI
n +
3D
In
+ 2
DI
n +
1D
I n
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
OD
TH4
OD
TH4
t AO
N (
MIN
)t A
DC
(M
IN)
t AD
C (
MIN
)t A
OF
(MIN
)
t AO
N (
MA
X)
t AD
C (
MA
X)
t AD
C (
MA
X)
t AO
F (M
AX
)
No
tes:
1.V
ia M
RS
or
OTF
. AL
= 0
, CW
L =
5. R
TT,n
om
an
d R
TT(W
R) a
re e
nab
led
.2.
OD
TH4
app
lies
to f
irst
reg
iste
rin
g O
DT
HIG
H a
nd
th
en t
o t
he
reg
istr
atio
n o
f th
e W
RIT
E co
mm
and
. In
th
is e
xam
ple
,O
DTH
4 is
sat
isfi
ed if
OD
T g
oes
LO
W a
t T8
(fo
ur
clo
cks
afte
r th
e W
RIT
E co
mm
and
).
Fig
ure
111: D
yn
am
ic O
DT:
Wit
ho
ut
WR
ITE C
om
man
d
T0T1
T2T3
T4T5
T6T7
T8T9
OD
TLo
ff
T10
T11
CKCK#
R TT
Do
n’t
Car
eTr
ansi
tio
nin
g
Com
man
dV
alid
Val
idV
alid
Val
idV
alid
Val
idV
alid
Val
idV
alid
Val
idV
alid
Val
id
Add
ress
DQ
S, D
QS#
DQ
OD
TH4
OD
TLo
n
t AO
N (
MA
X)
t AO
N (
MIN
)
t AO
F (M
IN)
t AO
F (M
AX
)
OD
T
R TT,n
om
No
tes:
1.A
L =
0, C
WL
= 5
. RTT
,no
m is
en
able
d a
nd
RTT
(WR
) is
eith
er e
nab
led
or
dis
able
d.
2.O
DTH
4 is
def
ined
fro
m O
DT
reg
iste
red
HIG
H t
o O
DT
reg
iste
red
LO
W; i
n t
his
exa
mp
le, O
DTH
4 is
sat
isfi
ed. O
DT
reg
-is
tere
d L
OW
at
T5 is
als
o le
gal
.
1Gb: x4, x8, x16 DDR3 SDRAMDynamic ODT
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 198 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Figu
re 7
1: D
ynam
ic O
DT: O
DT A
sser
ted
Befo
re a
nd A
fter t
he W
RITE
, BC4
Notes:
1.ViaMRSorO
TF.A
L=0,CWL=5.R
TT,nom
and
RTT
(WR)areenabled.
2.ODTH
4appliestofirstregisteringODTHIGHand
thento
theregistrationofth
eWRITEcommand.Inth
isexample,ODTH
4issatisfiedifODT
goesLOWatT
8(fourclocksaftertheW
RITEcommand).
Figu
re 7
2: D
ynam
ic O
DT: W
ithou
t WRI
TE C
omm
and
Notes:
1.AL=0,CWL=5.R
TT,nom
isenabledand
RTT
(WR)iseitherenabledord
isabled.
2.ODTH
4isdefinedfro
mODTregisteredHIGHto
ODTregisteredLOW;inthisexample,ODTH
4issatisfied.ODTregisteredLOWatT
5isalsolegal.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
110
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Fig
ure
112: D
yn
am
ic O
DT:
OD
T Pin
Ass
ert
ed
To
geth
er
wit
h W
RIT
E C
om
man
d f
or
6 C
lock
Cycl
es,
BL8
T0T1
T2T3
T4T5
T6T7
T8T9
OD
TLcw
n8
OD
TLo
n
OD
TLcn
w
WL
t AO
F (M
AX
)
T10
T11
CK
CK
#
Ad
dre
ss
R TT
OD
T
DQ
DQ
S, D
QS#
DI
b +
3D
Ib
+ 2
DI
b +
1D
I bD
Ib
+ 7
DI
b +
6D
Ib
+ 5
DI
b +
4
Val
id
Do
n’t
Car
eTr
ansi
tio
nin
g
Co
mm
and
WR
S8N
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
R TT(
WR
)
OD
TH8
OD
TLo
ff
t AD
C (
MA
X)
t AO
N (
MIN
)
t AO
F (M
IN)
No
tes:
1.V
ia M
RS
or
OTF
; AL
= 0
, CW
L =
5. I
f R
TT,n
om
can
be
eith
er e
nab
led
or
dis
able
d, O
DT
can
be
HIG
H. R
TT(W
R) i
s en
able
d.
2.In
th
is e
xam
ple
, OD
TH8
= 6
is s
atis
fied
exa
ctly
.
1Gb: x4, x8, x16 DDR3 SDRAMDynamic ODT
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 199 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Figu
re 7
3: D
ynam
ic O
DT: O
DT P
in A
sser
ted
Toge
ther
with
WRI
TE C
omm
and
for 6
Clo
ck C
ycle
s, B
L8
Notes:
1.ViaMRSorO
TF;A
L=0,CWL=5.IfR
TT,nom
canbeeitherenabledord
isabled,ODTcanbeHIGH.R
TT(W
R)isenabled.
2.Inth
isexample,ODTH
8=6issatisfiedexactly.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
111
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Figure 74: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
Figure 75: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
Figure 113: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
ODTLon
ODTLcnw
WL
T10 T11
CKCK#
ODTLcwn4
DQS, DQS#
Address Valid
Don’t CareTransitioning
ODTLoff
Command WRS4NOP NOPNOP NOP NOP NOP NOP NOP NOP NOP NOP
DQ DIn + 3
DIn + 2
DIn + 1
DIn
tADC (MIN) tAOF (MIN)
tAOF (MAX)tADC (MAX)
tADC (MAX)
tAON (MIN)
ODTH4
ODT
RTT RTT(WR) RTT,nom
Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. RTT,nom and RTT(WR) are enabled.2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example,
ODTH4 is satisfied. ODT registered LOW at T5 is also legal.
Figure 114: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
ODTLon
ODTLcnw
WL
T10 T11
CKCK#
ODTLcwn4
DQS, DQS#
Address Valid
Command WRS4NOP NOPNOP NOP NOP NOP NOP NOP NOP NOP NOP
Don’t CareTransitioning
DQ DIn
DIn + 3
DIn + 2
DIn + 1
ODTH4
tADC (MAX)
tAON (MIN)
tAOF (MIN)
tAOF (MAX)
ODTLoff
RTT RTT(WR)
ODT
Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. RTT,nom can be either enabled or disabled. If disabled,ODT can remain HIGH. RTT(WR) is enabled.
2. In this example ODTH4 = 4 is satisfied exactly.
1Gb: x4, x8, x16 DDR3 SDRAMDynamic ODT
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 200 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Figure 113: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
ODTLon
ODTLcnw
WL
T10 T11
CKCK#
ODTLcwn4
DQS, DQS#
Address Valid
Don’t CareTransitioning
ODTLoff
Command WRS4NOP NOPNOP NOP NOP NOP NOP NOP NOP NOP NOP
DQ DIn + 3
DIn + 2
DIn + 1
DIn
tADC (MIN) tAOF (MIN)
tAOF (MAX)tADC (MAX)
tADC (MAX)
tAON (MIN)
ODTH4
ODT
RTT RTT(WR) RTT,nom
Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. RTT,nom and RTT(WR) are enabled.2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example,
ODTH4 is satisfied. ODT registered LOW at T5 is also legal.
Figure 114: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
ODTLon
ODTLcnw
WL
T10 T11
CKCK#
ODTLcwn4
DQS, DQS#
Address Valid
Command WRS4NOP NOPNOP NOP NOP NOP NOP NOP NOP NOP NOP
Don’t CareTransitioning
DQ DIn
DIn + 3
DIn + 2
DIn + 1
ODTH4
tADC (MAX)
tAON (MIN)
tAOF (MIN)
tAOF (MAX)
ODTLoff
RTT RTT(WR)
ODT
Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. RTT,nom can be either enabled or disabled. If disabled,ODT can remain HIGH. RTT(WR) is enabled.
2. In this example ODTH4 = 4 is satisfied exactly.
1Gb: x4, x8, x16 DDR3 SDRAMDynamic ODT
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 200 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Notes:
1. ViaMRSorOTF.AL=0,CWL=5.RTT,nomandRTT(WR)areenabled.
2. ODTH4isdefinedfromODTregisteredHIGHtoODTregisteredLOW,sointhisexample,ODTH4issatisfied.ODTregisteredLOWatT5isalsolegal.
Notes:
1. ViaMRSorOTF.AL=0,CWL=5.RTT,nomcanbeeitherenabledordisabled.Ifdisabled,ODTcanremainHIGH.RTT(WR)isenabled.
2. InthisexampleODTH4=4issatisfiedexactly.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
112
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Synchronous ODT ModeSynchronous ODT mode is selected whenever the DLL isturned on and locked and when either RTT,nom or RTT(WR)is enabled. Based on the power-down definition, thesemodesare:
• AnybankactivewithCKEHIGH
• RefreshmodewithCKEHIGH
• IdlemodewithCKEHIGH
• Activepower-downmode(regardlessofMR0[12])
• Prechargepower-downmodeifDLLisenabledbyMR0[12]duringprechargepowerdown
ODT Latency and Posted ODT
InsynchronousODTmode,RTTturnsonODTLonclockcyclesafterODTissampledHIGHbyarisingclockedgeandturnsoffODTLoffclockcyclesafterODTisregisteredLOWbyarisingclockedge.Theactualon/offtimesvariesbytAONandtAOFaroundeachclockedge(seeTable40(page112)).TheODTlatencyistiedtotheWRITElatency(WL)byODTLon=WL-2andODTLoff=WL-2.
SincewritelatencyismadeupofCASWRITElatency(CWL)andadditivelatency(AL),theALprogrammedintothemode
register(MR1[4,3])alsoappliestotheODTsignal.Thedevice’sinternalODTsignalisdelayedanumberofclockcyclesdefinedbytheALrelativetotheexternalODTsignal.Thus,ODTLon=CWL+AL-2andODTLoff=CWL+AL-2.
Timing Parameters
SynchronousODTmodeusesthefollowingtimingparameters:ODTLon, ODTLoff, ODTH4, ODTH8, tAON, and tAOF. TheminimumRTTturn-ontime(tAON[MIN]) isthepointatwhichthedevice leavesHigh-ZandODTresistancebegins to turnon.MaximumRTT turn-on time (tAON [MAX]) is thepoint atwhichODTresistance is fullyon.BotharemeasuredrelativetoODTLon.TheminimumRTTturn-offtime(tAOF[MIN])isthepointatwhichthedevicestartstoturnoffODTresistance.ThemaximumRTTturnofftime(tAOF[MAX])isthepointatwhichODThasreachedHigh-Z.BotharemeasuredfromODTLoff.
WhenODT isasserted, itmust remainHIGHuntilODTH4 issatisfied.IfaWRITEcommandisregisteredbytheDRAMwithODTHIGH,thenODTmustremainHIGHuntilODTH4(BC4)orODTH8(BL8)aftertheWRITEcommand(seeFigure77(page113)).ODTH4andODTH8aremeasuredfromODTregisteredHIGH to ODT registered LOW or from the registration of aWRITEcommanduntilODTisregisteredLOW.
Table 40: Synchronous ODT Parameters
Symbol Description Begins at Defined toDefinition for All
DDR3L Speed BinsUnit
ODTLon ODT synchronous turn-on delay ODT registered HIGH RTT(ON) ±tAON CWL + AL - 2 tCK
ODTLoff ODT synchronous turn-off delay ODT registered HIGH RTT(OFF) ±tAOF CWL +AL - 2 tCK
ODTH4ODT minimum HIGH time after ODT assertion or WRITE (BC4)
ODT registered HIGH or write registration with ODT HIGH
ODT registered LOW 4tCK tCK
ODTH8 ODT minimum HIGH time after WRITE (BL8) Write registration with ODT HIGH ODT registered LOW 6tCK tCK
tAON ODT turn-on relative to ODTLon completion Completion of ODTLon RTT(ON)See Electrical Characteristics and
AC Operating Conditions tableps
tAOF ODT turn-off relative to ODTLoff completion Completion of ODTLoff RTT(OFF) 0.5tCK ± 0.2tCK tCK
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
113
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Tab
le 9
0:
Syn
chro
no
us
OD
T Para
mete
rs
Sym
bo
lD
esc
rip
tio
nB
eg
ins
at
Defi
ned
to
Defi
nit
ion
fo
r A
llD
DR
3 S
peed
Bin
sU
nit
OD
TLo
nO
DT
syn
chro
no
us
turn
-on
del
ayO
DT
reg
iste
red
HIG
HR
TT(O
N) ±
t AO
NC
WL
+ A
L -
2t C
K
OD
TLo
ffO
DT
syn
chro
no
us
turn
-off
del
ayO
DT
reg
iste
red
HIG
HR
TT(O
FF) ±
t AO
FC
WL
+A
L -
2t C
K
OD
TH4
OD
T m
inim
um
HIG
H t
ime
afte
r O
DT
asse
rtio
n o
r W
RIT
E (B
C4)
OD
T re
gis
tere
d H
IGH
or
wri
te r
egis
-tr
atio
n w
ith
OD
T H
IGH
OD
T re
gis
tere
d L
OW
4t CK
t CK
OD
TH8
OD
T m
inim
um
HIG
H t
ime
afte
r W
RIT
E(B
L8)
Wri
te r
egis
trat
ion
wit
h O
DT
HIG
HO
DT
reg
iste
red
LO
W6t C
Kt C
K
t AO
NO
DT
turn
-on
rel
ativ
e to
OD
TLo
nco
mp
leti
on
Co
mp
leti
on
of
OD
TLo
nR
TT(O
N)
See
Tab
le 5
6(p
age
79)
ps
t AO
FO
DT
turn
-off
rel
ativ
e to
OD
TLo
ffco
mp
leti
on
Co
mp
leti
on
of
OD
TLo
ffR
TT(O
FF)
0.5t C
K ±
0.2
t CK
t CK
Fig
ure
11
5:
Syn
chro
no
us
OD
T
T0T1
T2T3
T4T5
T6T7
T8T9
CW
L -
2A
L =
3A
L =
3
t AO
N (
MA
X)
t AO
F (M
AX
)
T10
T11
T12
T13
T14
T15
CKCK#
R TT
OD
T
Do
n’t
Car
eTr
ansi
tio
nin
g
R TT,n
om
CKE
t AO
F (M
IN)
OD
TLo
ff =
CW
L +
AL
- 2
OD
TLo
n =
CW
L +
AL
- 2
OD
TH4
(MIN
)
t AO
N (
MIN
)
No
te:
1.A
L =
3; C
WL
= 5
; OD
TLo
n =
WL
= 6
.0; O
DTL
off
= W
L -
2 =
6. R
TT,n
om
is e
nab
led
.
1Gb: x4, x8, x16 DDR3 SDRAMSynchronous ODT Mode
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 202 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Fig
ure
11
6:
Syn
chro
no
us
OD
T (B
C4
)
T0T1
T2T3
T4T5
T6T7
T8T9
t AO
F (M
AX
)
t AO
F (M
IN)
t AO
N (
MA
X)
t AO
F (M
AX
)
T10
T11
T12
T13
T14
T15
T17
T16
CKCK#
R TT
CKE
NO
PW
RS4
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
Com
man
d
Do
n’t
Car
eTr
ansi
tio
nin
g
t AO
N (
MIN
)
R TT,n
om
OD
TLo
ff =
WL
- 2
OD
TH4
(MIN
) O
DTH
4
OD
TLo
ff =
WL
- 2
OD
TLo
n =
WL
- 2
t AO
N (
MIN
)t A
ON
(M
AX
)
OD
TH4
OD
TLo
n =
WL
- 2
t AO
F (M
IN)
OD
T
R TT,n
om
No
tes:
1.W
L =
7. R
TT,n
om
is e
nab
led
. RTT
(WR
) is
dis
able
d.
2.O
DT
mu
st b
e h
eld
HIG
H f
or
at le
ast
OD
TH4
afte
r as
sert
ion
(T1
).3.
OD
T m
ust
be
kep
t H
IGH
OD
TH4
(BC
4) o
r O
DTH
8 (B
L8)
afte
r th
e W
RIT
E co
mm
and
(T7
).4.
OD
TH is
mea
sure
d f
rom
OD
T fi
rst
reg
iste
red
HIG
H t
o O
DT
firs
t re
gis
tere
d L
OW
or
fro
m t
he
reg
istr
atio
n o
f th
eW
RIT
E co
mm
and
wit
h O
DT
HIG
H t
o O
DT
reg
iste
red
LO
W.
5.A
lth
ou
gh
OD
TH4
is s
atis
fied
fro
m O
DT
reg
iste
red
HIG
H a
t T6
, OD
T m
ust
no
t g
o L
OW
bef
ore
T11
as
OD
TH4
mu
stal
so b
e sa
tisf
ied
fro
m t
he
reg
istr
atio
n o
f th
e W
RIT
E co
mm
and
at
T7.
1Gb: x4, x8, x16 DDR3 SDRAMSynchronous ODT Mode
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 203 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Figu
re 7
6: S
ynch
rono
us O
DT
Figu
re 7
7: S
ynch
rono
us O
DT (B
C4)
Note:
1.AL=3;CWL=5;ODTLon=W
L=6.0;ODTLoff=
WL-2=6.R
TT,nom
isenabled.
Notes:
1.WL=7.RTT,nom
isenabled.R
TT(W
R)isdisabled.
2.ODTmustb
eheldHIGHfora
tleastODTH
4aftera
ssertion(T1).
3.ODTmustb
ekeptHIGHODTH
4(BC4)orO
DTH
8(BL8)aftertheW
RITEcommand(T7).
4.ODTH
ism
easuredfro
mODTfirstregisteredHIGHto
ODTfirstregisteredLOWorfromth
eregistrationofth
eWRITE
commandwithODTHIGHto
ODTregisteredLOW.
5.AlthoughODTH
4issatisfiedfro
mODTregisteredHIGHatT
6,ODTmustn
otgoLO
WbeforeT1
1asODTH
4mustalsobe
satisfiedfro
mth
eregistrationofth
eWRITEcommandatT7.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
114
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
ODT Off During READs
Because thedevicecannot terminateanddriveat thesametime,RTTmustbedisabledatleastone-halfclockcyclebeforethe READ preamble by driving the ODT ball LOW (if eitherRTT,nomorRTT(WR) isenabled).RTTmaynotbeenableduntiltheendofthepostamble,asshowninthefollowingexample.
Note:ODTmaybedisabledearlierandenabledlaterthanshowninFigure78(page115).
Asynchronous ODT ModeAsynchronousODTmodeisavailablewhentheDRAMrunsinDLLonmodeandwheneitherRTT,nomorRTT(WR)isenabled;however, the DLL is temporarily turned off in prechargedpower-downstandby(viaMR0[12]).Additionally,ODToperatesasynchronously when the DLL is synchronizing after beingreset. See Power-Down Mode (page 94) for definition andguidanceoverpower-downdetails.
InasynchronousODTtimingmode,theinternalODTcommandisnotdelayedbyALrelativetotheexternalODTcommand.InasynchronousODTmode,ODTcontrolsRTTbyanalogtime.ThetimingparameterstAONPDandtAOFPDreplaceODTLon/tAON and ODTLoff/tAOF, respectively, when ODT operatesasynchronously.
TheminimumRTT turn-on time (tAONPD [MIN]) is the pointat which the device termination circuit leaves High-Z andODTresistancebeginstoturnon.MaximumRTTturnontime(tAONPD[MAX]) is thepointatwhichODTresistance is fullyon. tAONPD (MIN) and tAONPD (MAX) are measured fromODTbeingsampledHIGH.
Theminimum RTT turn-off time (tAOFPD [MIN]) is the pointatwhich thedevice terminationcircuitstarts to turnoffODTresistance.MaximumRTTturn-offtime(tAOFPD[MAX])isthepointatwhichODThas reachedHigh-Z. tAOFPD (MIN)andtAOFPD(MAX)aremeasuredfromODTbeingsampledLOW.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
115
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Fig
ure
11
8:
Asy
nch
ron
ou
s O
DT
Tim
ing
wit
h F
ast
OD
T Tr
an
siti
on
T0T1
T2T3
T4T5
T6T7
T8T9
t AO
NPD
(M
AX
)t A
OFP
D (
MA
X)
T10
T11
T12
T13
T14
T15
T17
T16
CKCK#
R TT
OD
T
R TT,n
om
Do
n’t
Car
eTr
ansi
tio
nin
g
CKE
t IHt IS
t IHt IS
t AO
FPD
(M
IN)
t AO
NPD
(M
IN)
No
te:
1.A
L is
ign
ore
d.
Tab
le 9
1:
Asy
nch
ron
ou
s O
DT
Tim
ing
Para
mete
rs f
or
All
Sp
eed
Bin
s
Sym
bo
lD
esc
rip
tio
nM
inM
ax
Un
itt A
ON
PDA
syn
chro
no
us
RTT
tu
rn-o
n d
elay
(p
ow
er-d
ow
n w
ith
DLL
off
)2
8.5
ns
t AO
FPD
Asy
nch
ron
ou
s R
TT t
urn
-off
del
ay (
po
wer
-do
wn
wit
h D
LL o
ff)
28.
5n
s
1Gb: x4, x8, x16 DDR3 SDRAMAsynchronous ODT Mode
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 207 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Fig
ure
11
7:
OD
T D
uri
ng
REA
Ds
T0
T1T2
T3T4
T5T6
T7T8
T9T1
0T1
1T1
2T1
3T1
4T1
5T1
7T1
6
CKCK#
Valid
Add
ress
DI
b +
3D
Ib
+ 2
DI
b +
1D
I bD
Ib
+ 7
DI
b +
6D
Ib
+ 5
DI
b +
4D
Q
DQ
S, D
QS#
Do
n’t
Car
eTr
ansi
tio
nin
g
Com
man
dN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
REA
D
OD
TLo
n =
CW
L +
AL
- 2
OD
T
t AO
N (
MA
X)
RL
= A
L +
CL
OD
TLo
ff =
CW
L +
AL
- 2
t AO
F (M
IN)
R TTR TT
,nom
R TT,n
omt A
OF
(MA
X)
No
te:
1.O
DT
mu
st b
e d
isab
led
ext
ern
ally
du
rin
g R
EAD
s b
y d
rivi
ng
OD
T LO
W. F
or
exam
ple
, CL
= 6
; AL
= C
L -
1 =
5; R
L =
AL
+ C
L =
11;
CW
L =
5; O
DTL
on
= C
WL
+ A
L -
2 =
8; O
DTL
off
= C
WL
+ A
L -
2 =
8. R
TT,n
om
is e
nab
led
. RTT
(WR
) is
a “D
on
’tC
are.
”
1Gb: x4, x8, x16 DDR3 SDRAMSynchronous ODT Mode
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 205 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Figu
re 7
8: O
DT D
urin
g RE
ADs
Figu
re 7
9: A
sync
hron
ous
ODT
Tim
ing
with
Fas
t ODT
Tra
nsiti
on
Note:
1.ODTmustb
edisabledexternallyduringREA
DsbydrivingODTLO
W.Forexample,CL=6;AL=
CL-1=5;RL=AL+CL=11
;CWL=5;ODTLon=CWL+AL-2=8;ODTLoff=
CWL+AL-2
=8.R
TT,nom
isenabled.R
TT(W
R)isa“Don’tCare.”
Note:
1.ALisignored.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
116
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Table 41: Asynchronous ODT Timing Parameters for All Speed Bins
Symbol Description Min Max Unit
tAONPD Asynchronous RTT turn-on delay (power-down with DLL off)2 8.5 ns
tAOFPD Asynchronous RTT turn-off delay (power-down with DLL off)
Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry)
There is a transition period aroundpower-down entry (PDE)where the DRAM’s ODT may exhibit either synchronous orasynchronousbehavior.ThistransitionperiodoccursiftheDLLis selected to be off when in precharge power-downmodebythesettingMR0[12]=0.Power-downentrybeginstANPDpriortoCKEfirstbeingregisteredLOW,andendswhenCKEisfirstregisteredLOW.tANPDisequaltothegreaterofODTLoff+1tCKorODTLon+1tCK.IfaREFRESHcommandhasbeenissued, and it is in progresswhenCKE goes LOW, power-downentryendstRFCaftertheREFRESHcommand,ratherthan when CKE is first registered LOW. Power-down entrythen becomes the greater of tANPD and tRFC - REFRESHcommandtoCKEregisteredLOW.
ODT assertion during power-down entry results in an RTTchangeasearlyasthelesseroftAONPD(MIN)andODTLon×tCK+tAON(MIN),oraslateasthegreateroftAONPD(MAX)andODTLon× tCK+ tAON(MAX).ODTde-assertionduringpower-downentrycanresultinanRTTchangeasearlyasthelesseroftAOFPD(MIN)andODTLoff×tCK+tAOF(MIN),oraslateasthegreateroftAOFPD(MAX)andODTLoff×tCK+tAOF(MAX).Table42(page117)summarizestheseparameters.
If AL has a large value, the uncertainty of the state of RTTbecomesquite large.This isbecauseODTLonandODTLoffarederivedfromtheWL;andWLisequaltoCWL+AL.Figure80(page118)showsthreedifferentcases:
• ODT_A:SynchronousbehaviorbeforetANPD.
• ODT_B:ODTstatechangesduringthetransitionperiodwithtAONPD(MIN)<ODTLon×tCK+tAON(MIN)andtAONPD(MAX)>ODTLon×tCK+tAON(MAX).
• ODT_C:ODTstatechangesafterthetransitionperiodwithasynchronousbehavior.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
117
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Table 42: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period
Description Min Max
Power-down entry transition period (power-down entry) Greater of: tANPD or tRFC - refresh to CKE LOW
Power-down exit transition period (power-down exit) tANPD + tXPDLL
ODT to RTT turn-on delay (ODTLon = WL - 2)Lesser of: tAONPD (MIN) (2ns) or
ODTLon × tCK + tAON (MIN)Greater of: tAONPD (MAX) (8.5ns) or
ODTLon × tCK + tAON (MAX)
ODT to RTT turn-off delay (ODTLoff = WL - 2)Lesser of: tAOFPD (MIN) (2ns) or
ODTLoff × tCK + tAOF (MIN)Greater of: tAOFPD (MAX) (8.5ns) or
ODTLoff × tCK + tAOF (MAX)
tANPD WL - 1 (greater of ODTLoff + 1 or ODTLon + 1)
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
118
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Tab
le 9
2: O
DT
Para
mete
rs f
or
Po
wer-
Do
wn
(D
LL O
ff)
En
try a
nd
Exit
Tra
nsi
tio
n P
eri
od
Desc
rip
tio
nM
inM
ax
Pow
er-d
ow
n e
ntr
y tr
ansi
tio
n p
erio
d(p
ow
er-d
ow
n e
ntr
y)G
reat
er o
f: t A
NPD
or
t RFC
- r
efre
sh t
o C
KE
LOW
Pow
er-d
ow
n e
xit
tran
siti
on
per
iod
(po
wer
-do
wn
exi
t)
t AN
PD +
t XPD
LL
OD
T to
RTT
tu
rn-o
n d
elay
(OD
TLo
n =
WL
- 2)
Less
er o
f: t A
ON
PD (
MIN
) (2
ns)
or
OD
TLo
n ×
t CK
+ t A
ON
(M
IN)
Gre
ater
of:
t AO
NPD
(M
AX
) (8
.5n
s) o
rO
DTL
on
× t C
K +
t AO
N (
MA
X)
OD
T to
RTT
tu
rn-o
ff d
elay
(OD
TLo
ff =
WL
- 2)
Less
er o
f: t A
OFP
D (
MIN
) (2
ns)
or
OD
TLo
ff ×
t CK
+ t A
OF
(MIN
)G
reat
er o
f: t A
OFP
D (
MA
X)
(8.5
ns)
or
OD
TLo
ff ×
t CK
+ t A
OF
(MA
X)
t AN
PDW
L -
1 (g
reat
er o
f O
DTL
off
+ 1
or
OD
TLo
n +
1)
Fig
ure
119: Syn
chro
no
us
to A
syn
chro
no
us
Tran
siti
on
Du
rin
g P
rech
arg
e P
ow
er-
Do
wn
(D
LL O
ff)
En
try
T0T1
T2T3
T4T5
T6T7
T8T9
t AO
FPD
(M
AX
)
OD
TLo
ff
T10
T11
T12
T13
Ta0
Ta1
Ta3
Ta2
CKCK#
DRA
M R
TT B
as
ynch
rono
us
or s
ynch
rono
us
R TT,n
om
DRA
M R
TT C
asyn
chro
nous
R TT,n
om
Do
n’t
Car
eTr
ansi
tio
nin
g
CKE
NO
PN
OP
NO
PN
OP
NO
PCo
mm
and
NO
PRE
FN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
PDE
tran
siti
on
per
iod
Ind
icat
es b
reak
in t
ime
scal
e
OD
TLo
ff +
tA
OFP
D (
MIN
)
t AO
FPD
(M
AX
)
t AO
FPD
(M
IN)
OD
TLo
ff +
t AO
FPD
(M
AX
)
t AO
FPD
(M
IN)
t AN
PD
t AO
F (M
IN)
t AO
F (M
AX
)
DRA
M R
TT A
sy
nchr
onou
sR TT
,nom
OD
T A
sy
nchr
onou
s
OD
T C
asyn
chro
nous
OD
T B
asyn
chro
nous
or
syn
chro
nous
t RFC
(M
IN)
No
te:
1.A
L =
0; C
WL
= 5
; OD
TL(o
ff)
= W
L -
2 =
3.
1Gb: x4, x8, x16 DDR3 SDRAMAsynchronous ODT Mode
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 209 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Figu
re 8
0: S
ynch
rono
us to
Asy
nchr
onou
s Tr
ansi
tion
Durin
g Pr
echa
rge
Pow
er-D
own
(DLL
Off)
Ent
ry
Note:
1.AL=0;CWL=5;ODTL(off)=W
L-2=3.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
119
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)The DRAM’s ODT can exhibit either asynchronous orsynchronous behavior during power-down exit (PDX). ThistransitionperiodoccursiftheDLLisselectedtobeoffwheninprechargepower-downmodebysettingMR0[12]to0.Power-down exit begins tANPD prior to CKE first being registeredHIGH, and ends tXPDLL after CKE is first registered HIGH.tANPDisequaltothegreaterofODTLoff+1tCKorODTLon+1tCK.ThetransitionperiodistANPD+tXPDLL.
ODT assertion during power-down exit results in an RTTchangeasearlyasthelesseroftAONPD(MIN)andODTLon×tCK+tAON(MIN),oraslateasthegreateroftAONPD(MAX)andODTLon× tCK+ tAON(MAX).ODTde-assertionduringpower-downexitmayresultinanRTTchangeasearlyasthelesseroftAOFPD(MIN)andODTLoff×tCK+tAOF(MIN),oraslateasthegreateroftAOFPD(MAX)andODTLoff×tCK+tAOF(MAX).Table42(page117)summarizestheseparameters.
IfALhasalargevalue,theuncertaintyoftheRTTstatebecomesquitelarge.ThisisbecauseODTLonandODTLoffarederivedfromWL,andWLisequaltoCWL+AL.Figure81(page120)showsthreedifferentcases:
• ODTC:AsynchronousbehaviorbeforetANPD.
• ODTB:ODTstatechangesduringthetransitionperiod,withtAOFPD(MIN)<ODTLoff×tCK+tAOF(MIN),andODTLoff×tCK+tAOF(MAX)>tAOFPD(MAX).
• ODTA:ODTstatechangesafterthetransitionperiodwithsynchronousresponse.
Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse)
Ifthetimeintheprechargepower-downoridlestatesisveryshort (short CKE LOW pulse), the power-down entry andpower-down exit transition periods overlap. When overlapoccurs, the responseof theDRAM’sRTT toachange in theODT state can be synchronous or asynchronous from thestartofthepower-downentrytransitionperiodtotheendofthepower-downexittransitionperiod,eveniftheentryperiodendslaterthantheexitperiod.
If the time in the idle state is very short (short CKE HIGHpulse),thepower-downexitandpower-downentrytransitionperiodsoverlap.Whenthisoverlapoccurs,theresponseoftheDRAM’sRTTtoachangeintheODTstatemaybesynchronousorasynchronousfromthestartofpower-downexittransitionperiodtotheendofthepowerdownentrytransitionperiod.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
120
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Fig
ure
12
0:
Asy
nch
ron
ou
s to
Syn
chro
no
us
Tran
siti
on
Du
rin
g P
rech
arg
e P
ow
er-
Do
wn
(D
LL O
ff)
Exit
T0T1
T2Ta
0Ta
1Ta
2Ta
3Ta
4Ta
5Ta
6Tb
0Tb
1Tb
2Tc
0Tc
1Td
0Td
1Tc
2
CKCK#
Do
n’t
Car
eTr
ansi
tio
nin
g
OD
T C
sync
hron
ous
NO
PN
OP
NO
PCO
MM
AN
DN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
R TT B
asyn
chro
nous
or s
ynch
rono
us
DRA
M R
TT A
asyn
chro
nous
DRA
M R
TT C
sync
hron
ous
R TT,n
om
NO
PN
OP
OD
T B
asyn
chro
nous
or s
ynch
rono
us
CKE
t AO
F (M
IN)
R TT,n
om
Ind
icat
es b
reak
in t
ime
scal
e
OD
TLo
ff +
tA
OF
(MIN
)
t AO
FPD
(M
AX
)
OD
TLo
ff +
tA
OF
(MA
X)
t XPD
LL
t AO
F (M
AX
)O
DTL
off
OD
T A
asyn
chro
nous
PDX
tra
nsi
tio
n p
erio
d
t AO
FPD
(M
IN)
t AO
FPD
(M
AX
)
R TT,n
om
t AN
PD
t AO
FPD
(M
IN)
No
te:
1.C
L =
6; A
L =
CL
- 1;
CW
L =
5; O
DTL
off
= W
L -
2 =
8.
1Gb: x4, x8, x16 DDR3 SDRAMAsynchronous to Synchronous ODT Mode Transition (Power-
Down Exit)
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 211 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Figu
re 8
1: A
sync
hron
ous
to S
ynch
rono
us T
rans
ition
Dur
ing
Prec
harg
e Po
wer
-Dow
n (D
LL O
ff) E
xit
Note:
1.CL=6;AL=CL-1;CWL=5;ODTLoff=
WL-2=8.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
121
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Fig
ure
12
1:
Tran
siti
on
Peri
od
fo
r Sh
ort
CK
E L
OW
Cycl
es
wit
h E
ntr
y a
nd
Exit
Peri
od
Overl
ap
pin
g
T0T1
T2T3
T4T5
T6T7
T8T9
Ta0
Ta1
Ta2
Ta3
Ta4
CKCK#
CKE
Com
man
d
Do
n’t
Car
eTr
ansi
tio
nin
g
t XPD
LL
t RFC
(M
IN)
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
REF
NO
PN
OP
NO
PN
OP
PDE
tran
siti
on
per
iod
PDX
tra
nsi
tio
n p
erio
d
Ind
icat
es b
reak
in t
ime
scal
e
t AN
PD
Sho
rt C
KE
low
tra
nsi
tio
n p
erio
d (
RTT
ch
ang
e as
ynch
ron
ou
s o
r sy
nch
ron
ou
s)
t AN
PD
No
te:
1.A
L =
0, W
L =
5, t A
NPD
= 4
.
Fig
ure
12
2:
Tran
siti
on
Peri
od
fo
r Sh
ort
CK
E H
IGH
Cycl
es
wit
h E
ntr
y a
nd
Exit
Peri
od
Overl
ap
pin
g
T0T1
T2T3
T4T5
T6T7
T8T9
CKCK#
Com
man
d
Do
n’t
Car
eTr
ansi
tio
nin
g
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
t AN
PDt X
PDLL
Ind
icat
es b
reak
in t
ime
scal
e
Ta0
Ta1
Ta2
Ta3
Ta4
CKE
t AN
PD
Sho
rt C
KE
HIG
H t
ran
siti
on
per
iod
(R
TT c
han
ge
asyn
chro
no
us
or
syn
cho
no
us)
No
te:
1.A
L =
0, W
L =
5, t A
NPD
= 4
.
1Gb: x4, x8, x16 DDR3 SDRAMAsynchronous to Synchronous ODT Mode Transition (Power-
Down Exit)
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 213 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Fig
ure
12
1:
Tran
siti
on
Peri
od
fo
r Sh
ort
CK
E L
OW
Cycl
es
wit
h E
ntr
y a
nd
Exit
Peri
od
Overl
ap
pin
g
T0T1
T2T3
T4T5
T6T7
T8T9
Ta0
Ta1
Ta2
Ta3
Ta4
CKCK#
CKE
Com
man
d
Do
n’t
Car
eTr
ansi
tio
nin
g
t XPD
LL
t RFC
(M
IN)
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
REF
NO
PN
OP
NO
PN
OP
PDE
tran
siti
on
per
iod
PDX
tra
nsi
tio
n p
erio
d
Ind
icat
es b
reak
in t
ime
scal
e
t AN
PD
Sho
rt C
KE
low
tra
nsi
tio
n p
erio
d (
RTT
ch
ang
e as
ynch
ron
ou
s o
r sy
nch
ron
ou
s)
t AN
PD
No
te:
1.A
L =
0, W
L =
5, t A
NPD
= 4
.
Fig
ure
12
2:
Tran
siti
on
Peri
od
fo
r Sh
ort
CK
E H
IGH
Cycl
es
wit
h E
ntr
y a
nd
Exit
Peri
od
Overl
ap
pin
g
T0T1
T2T3
T4T5
T6T7
T8T9
CKCK#
Com
man
d
Do
n’t
Car
eTr
ansi
tio
nin
g
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
NO
PN
OP
t AN
PDt X
PDLL
Ind
icat
es b
reak
in t
ime
scal
e
Ta0
Ta1
Ta2
Ta3
Ta4
CKE
t AN
PD
Sho
rt C
KE
HIG
H t
ran
siti
on
per
iod
(R
TT c
han
ge
asyn
chro
no
us
or
syn
cho
no
us)
No
te:
1.A
L =
0, W
L =
5, t A
NPD
= 4
.
1Gb: x4, x8, x16 DDR3 SDRAMAsynchronous to Synchronous ODT Mode Transition (Power-
Down Exit)
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 213 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Figu
re 8
2: T
rans
ition
Per
iod
for S
hort
CKE
LOW
Cyc
les
with
Ent
ry a
nd E
xit P
erio
d Ov
erla
ppin
g
Figu
re 8
3: T
rans
ition
Per
iod
for S
hort
CKE
HIGH
Cyc
les
with
Ent
ry a
nd E
xit P
erio
d Ov
erla
ppin
g
Note:
1.AL=0,W
L=5,t A
NPD=4.
Note:
1.AL=0,W
L=5,t A
NPD=4.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
122
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Figure 84: 96-Ball FBGA – x16 (JT)Figure 13: 96-Ball FBGA – x16 (JT)
Seating plane
0.12 A
123789
A
B
C
D
E
F
G
H
J
K
L
M
N
Ball A1 ID Ball A1 ID
A
0.25 MIN
1.1 ±0.10.8 TYP
6.4 CTR
8 ±0.1
0.8 TYP
12 CTR
14 ±0.1
96X Ø0.45Dimensions applyto solder balls post-reflow on Ø0.35SMD ball pads.
0.155
P
R
T
1.8 CTRNonconductive
overmold
Notes: 1. All dimensions are in millimeters.2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu)
1Gb: x4, x8, x16 DDR3 SDRAMPackage Dimensions
PDF: 09005aef826aa9061Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN 29 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Notes:
1. Alldimensionsareinmillimeters.
2. Solderballmaterial:SAC305(96.5%Sn,3%Ag,0.5%Cu)
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
123
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Table 43: Ordering Information
Part Number Data Rate (Mbps) Device Grade
MYX4DDR364M16JTBG-15EIT 1333 Industrial
MYX4DDR364M16JTBG-15E 1333 Commercial
MYX4DDR364M16JTBG-15EET 1333 Enhanced
PleasecontactaMicrosssalesrepresentativeforIBISorthermalmodelsatsales@micross.com.
MYX4DDR364M16JT*Revision 1.3 - 10/31/14
*Advanced information. Subject to change without notice.
124
1Gb SDRAM-DDR3MYX4DDR364M16JT*
Form #: CSI-D-685 Document 007
Document Title
1GByte, 128M x 16, DDR3 SDRAM, 8mm x 14mm - 96-ball FBGA Package
Revision History
Revision # History Release Date Status
1.0 Initial Release September 2014 Preliminary
1.1 Page 1: Added automotive option under “Operating temperature” in Options/Marking blue box. October 3, 2014 Preliminary
Page 124: Added enhanced parts to Table 44: Ordering Information.
Page 1: Changed “FPGA” to “FBGA” in blue box
Page 1: Changed “Marking” to “Code” in blue box
Page 1: Removed “-x16” after “(Sn63 / Pb37) in blue box
1.2 Changed speed grades -15 and -18 -to -15E and -187E October 22, 2014 Preliminary
1.3 Removed speed grade -187E October 31, 2014 Preliminary