Post on 24-May-2020
Slide 1
18 - 322 Fall 2003 Lecture 23Memory I:
Overview of Semiconductor Memories
• Random Access Memories • ROMs;
– ROM– Decoders– PLA’s– EEPROM
Slide 2
Static Random Access
• Memory Classification• CMOS Static Memory
– Six transistor memory cell– Memory architecture– Decoders– Read/write cirtcuitry
• RMOS Static Memory– Four transistor memory cell– Technology– Memory cell layout
Slide 3
Memory ClassificationMemories
Semiconductor Memories
Random Access Memories RAM
Other Memories
Static (SRAM)
Read Only (ROM)
Dynamic (DRAM)
Programmable (PROM)
Erasable EPROMElectrically(EEPROM)
Flash Memories
R/W Memories
Other Memories
Slide 4
Memory ClassificationSemiconductor Memories
Read Only (ROM) L 23
Static (SRAM) L 23/24
Dynamic (DRAM) L 24
Slide 5
Random Access Memories
NA
M
2N
COLUMN DECODER
RO
W D
ECO
DER
1 221A 1
A 22A 3
1 2B B B 3 MB
Slide 6
Read Only Memory (ROM)
R
R
R
R
0
1
2
3
X X X X X X X0 1 2 3 4 5 6
Slide 7
Read Only Memory (ROM)
R0
R1
R2
R3
X X X X X X0 1 2 3 4 5 6X
Slide 8
Read Only Memory (ROM)
R
R
R
R
0
1
2
3
X X X X X X0 1 2 3 4 5
0 0
0 1
1 0
1 1
Slide 9
A 0 A 1
R
R
R
R
0
1
2
3
Row Decoder
A 0 A 1 R R R R0 1 2 3
Slide 10
Column Decoder
B 0
B 1
B 2
Data
Slide 11
Column Decoder
Data
CO
LUM
N D
ECO
DER
B 0B 1B 2
BM
Slide 12
Read Only Memory (ROM)
Slide 13
Read Only Memory (ROM)Active
Slide 14
Read Only Memory (ROM)Poly
Slide 15
Read Only Memory (ROM)Metal
Slide 16
Read Only Memory (ROM)
R0
R1R2
R3R4
R5
X0 X1 X2 X3 X4 X5 X6 X7
Slide 17
Read Only Memory (ROM)
Slide 18
Read Only Memory (ROM)
Slide 19
Read Only Memory (ROM)
Slide 20
Read Only Memory (ROM)
Slide 21
Read Only Memory (ROM)
Slide 22
Programmable Logic Array (PLA)
inputoutput
inputoutput
AND OR
inputs outputs
NOR NOR
outputsinvert invert
inputs
Slide 23
ProgrammableLogic Array
(PLA)
Slide 24
PLABAND
A B
A + B = A B
A + B = AB
A
Slide 25
PLAOR
X
VDD VDD
Y
X+Y
Slide 26
PLA
A B
A + B = A B
A + B = AB
A
B
ANDVDD VDD
AB + A B A + B
Slide 27
PLAActive
Slide 28
PLAPoly
Slide 29
PLAMetal
Slide 30
PLA
Slide 31
PLA
Slide 32
PLA
Slide 33
Electrically Programmable
Control Gate
S D
GFloating Gate
"n" "n""p"
Source Drain
Erase --> Apply UV--> Low Vt --> Transistor ON when Selected
Program --> CG = High, Drain = High, Source = Low--> High Vt --> Transistor OFF when Selected
Slide 34
Electrically Programmable
Control Gate
Floating Gate
Source Drain
"p""n" "n"
Erase --> CG = High, Drain = Low, Source = Low--> High Vt --> Transistor OFF when Selected
Program --> CG = Low, Drain = High, Source = Low--> Low Vt --> Transistor ON when Selected
Slide 35
Electrically Programmable
R
R
R
R
0
1
2
3
X X X0 1 2
Slide 36
Flash EEPROM
• Same as EEPROMs
• Erased in Single Cycle
• Relatively low number of erase/program cycles
Slide 37
Static Random Access Memories
• Memory Classification• CMOS static memory
– Six transistor memory cell– Memory architecture– Decoders– Read/Write circuitry
Slide 38
Memory ClassificationMemories
Semiconductor Memories
Random Access Memories RAM
Other Memories
Static (SRAM)
Read Only (ROM)
Dynamic (DRAM)
Programmable (PROM)
Erasable EPROMElectricallyFlash Memories
R/W Memories
Other Memories
Slide 39
CMOS static memorySix transistor memory cell
Slide 40
CMOS static memorySix transistor memory cell
BitBit
BitBit
VDD VDD
GND GND
WW
BitBit
BitBit
VDD VDD
GND GND
WW
Slide 41
CMOS static memoryMemory architecture
BitBitROW
DECODER
R0
R0
R1
R1
ROW
DECODER
R2
R2
R3
R3
A0
A1
A0
A1
R/W CIRCUITRY (SENS AMPLIFIERS)
COLUMN DECODERS
BitBit BitBit BitBit
BitBit BitBit BitBit BitBit
R/W CIRCUITRY (SENS AMPLIFIERS)
COLUMN DECODERS
A2
A3
A2
A3
Slide 42
CMOS static memoryDecoders
A 0 A 1
R
R
R
R
0
1
2
3
Data
A 0
A 1
A 2
Slide 43
CMOS static memoryRead/Write circuitry
Data in
From column decoder
Diff. Amplifier
Bit Bit
OUT
W/R
GND
Slide 44
CMOS static memoryRead
Data in
From column decoder
Diff. Amplifier
Bit Bit
OUT
W/R
GND
Slide 45
CMOS static memoryWrite
From column decoder
Diff. Amplifier
Bit Bit
OUT
Data in
W/R
GND