Post on 31-Mar-2015
1 B. Bruidegom
Computer Architecture
Top down approach
B. Bruidegom AMSTEL-instituut
2 B. Bruidegom
Basic Components
• Program Counter (PC)
• Instruction Memory
• Registers
• Arithmetic Logic Unit (ALU)
• Data Memory
3 B. Bruidegom
Simplified View of a Harvard Architecture
Instruction Memory
Registers (16) DataMemory
ALU
PCInstruction
Data
AddressAddress
Register #
Register #
Register #
Data
4 B. Bruidegom
16 bit Data-path
Instruction Memory
Registers (16) DataMemory
ALU
PCInstruction
Data
AddressAddress
Register #
Register #
Register #
Data
5 B. Bruidegom
Simplified View of a Harvard Architecture
Instruction Memory
Registers DataMemory
ALU
PCInstruction
Data
AddressAddress
Register #
Register #
Register #
Data
Two types of functional units:• elements that operate on data values (combinational)• elements that contain state (sequential)
6 B. Bruidegom
Simplified View of a Harvard Architecture
Instruction Memory
Registers DataMemory
ALU
PCInstruction
Data
AddressAddress
Register #
Register #
Register #
Data
Two types of functional units:• elements that operate on data values (combinational)• elements that contain state (sequential)
7 B. Bruidegom
Simplified View of a Harvard Architecture
Instruction Memory
Registers DataMemory
ALU
PCInstruction
Data
AddressAddress
Register #
Register #
Register #
Data
Two types of functional units:• elements that operate on data values (combinational)• elements that contain state (sequential)
•Edge triggered•Level Triggered CLOCK
Edge
8 B. Bruidegom
Voorbeeld van een instructie: ADD
Instruction Memory
Registers DataMemory
ALU
PCInstruction
Data
AddressAddress
1st register #
2nd register #
Dest. reg. #
Data
ADD $r0, $r1, $r2$r0 = $r1 + $r2
Assembly Language
9 B. Bruidegom
Voorbeeld van een immediate instructie: ADDI
Instruction Memory
Registers DataMemory
ALU
PCInstruction
Data
AddressAddress
1st register #
2nd register #
Dest. reg. #
Data
ADDI $r0, $r1, 100$r0 = $r1 + 100
100
10 B. Bruidegom
De load-instructie LW: Register Memory
Instruction Memory
Registers DataMemory
ALU
PCInstruction
Data
AddressAddress
1st register #
2nd register #
Dest. reg. #
Data
LW $r0, 100($r1)$r0 = Memory[$r1 + 100]
100
11 B. Bruidegom
Branch-instruction: Branch Equal BEQ
Instruction Memory
Registers DataMemory
ALU
PCInstruction
Data
AddressAddress
1st register #
2nd register #
Dest. reg. #
Data
BEQ $r0, $r1, 100IF($r0 == $r1) GOTO 100
100
z
12 B. Bruidegom
Vijf fases van een instructie
Instruction Memory
Registers (16) DataMemory
ALU
PC
Instruction
Data in
AddressAddress
1st register #
2d register #
Dest. reg. #
Data in
1: Instruction fetch 2: Instruction decode 3: Execution
5: Write back
Figuur 10 Vijf fases van een instructie
Data out
4: Memory access
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Welke instructie gebruikt welke fase?
Instructiontype
Instruction fetch
Instruction decode
Execute Memory access
Write back
LI x x x
ADD x x x x
ADDI
LW
SW
BEQ
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16 bit Harvard Processor
15 B. Bruidegom
Voorbeeld van een immediate instructie: Load Immediate
Instruction Memory
Registers DataMemory
ALU
PCInstruction
Data
AddressAddress
1st register #
2nd register #
Dest. reg. #
Data
LI $r1, 0x1FD$r1 = 0x1FD
1FD
16 B. Bruidegom
16 bit Harvard Processor
LI $1, 0x1FD
MemWrite: 0MemRead: 0Branch: 02Reg: 0
17 B. Bruidegom
16 bit Harvard Processor
LI $1, 0x1FD
RegWrite: 1ALUOp: 001
18 B. Bruidegom
16 bit Harvard Processor
LI $1, 0x1FD
Rd: 0001Rt: 0000Rs: 0000
19 B. Bruidegom
16 bit Harvard Processor
LI $1, 0x1FD
Immediate:0x01FD=509=0000 0001 1111 1101
20 B. Bruidegom
ALU tabel
B
ALU2 ALU1 ALU0 operatie
0 0 0 complement van B
0 0 1 B B wordt doorgegeven
0 1 0 A - B rekenkundige -
0 1 1 A plus B rekenkundige +
1 0 0 A B bitwise XOR
1 0 1 A + B bitwise OR
1 1 0 A . B bitwise AND
1 1 1 1111 -1
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Instruction format
22 B. Bruidegom
Instruction format
MemWrite
MemToReg
Br 2Reg
RegWrit
e
ALU Opcode
OpArs
OpBrt
Destrd
Immediate
nr of bits
1 1 1 1 1 3 8 4 4 4 16
NOT 0 0 0 1 1 000 0x18 0 rt rd 0
MOVE 0 0 0 1 1 001 0x19 0 rt rd 0
LDI 0 0 0 0 1 001 0x09 0 0 rd immediate
ADD 0 0 0 1 1 011 0x1B rs rt rd 0
SUB
ADDI
ANDI
BEQ
LW
SW
23 B. Bruidegom
Instruction set 16 bit Harvard machine
Mnemonic Meaning Example Meaning
MOVE rd, rt Copy register MOVE $1, $2 r1 r2
NOT rd, rt One complement NOT $1, $2 r1 ~r2
SUB rd, rs, rt Subtract SUB $4, $2, $3 r4 r2 - r3
ADD rd, rs, rt Add ADD $4, $2, $3 r4 r2 + r3
XOR rd, rs, rt Bitwise exclusive or XOR $4, $2, $3 r4 r2 r3
OR rd, rs, rt Bitwise or ADD $4, $2, $3 r4 r2 | r3
AND rd, rs, rt Bitwise and ADD $4, $2, $3 r4 r2 & r3
LI rd, imm Load Immediate LDI $1, 0x34 r1 0x34
NOTI rd, imm Not Immediate NOTI $1, 0x34 r1 ~0x34
SUBI rd, rs, imm Sub Immediate SUBI $1, $2, 0x34 r1 r2 - 0x34
ADDI rd, rs, imm Add Immediate ADDI $1, $2, 0x34 r1 r2 + 0x34
XORI rd, rs, imm XOR Immediate XORI $1, $2, 0x34 r1 r2 0x34
ORI rd, rs, imm Or Immediate ADDI $1, $2, 0x34 r1 r2 | 0x34
ANDI rd, rs, imm And Immediate ADDI $1, $2, 0x34 r1 r2 & 0x34
BRA offset Branch Always to “label” BRA label PC PC + offset
BZ rt, offset Branch if rt = 0 BZ $6, end If (r6 = 0) goto ‘end’
BEQ rs, rt, offset Branch if rs = rt BEQ $6, $8, loop If (r6 = r8) goto ‘loop’
LW rd, rs ,index Load Word from Memory LW $2, 0x8($1) R2 Address (8 + r1)
SW rs, rt, index Store Word to Memory SW $2, 0x8($1) Address (8 + r1) r2