Effects on PC-Board and System Level

Effects on Integrated Circuit Level

Effects on Device Level

Microwave Interference Effects on Device, Integrated Circuits and PC-Board System

A Presentation on Recent Progress

N. Goldsman, Y. Bai, A. Akturk, T. Chitnis, B. Jacob, J. Baker, A. Iliadis, J. Melngailis10/10/01

Chip-to-Chip Connection on PC Board:

Bond Pad

Bond WireTransmission Line

Pins

Standard Planar Technology Implementation:IC Chips on PC Board

Input Output

Die (Integrated Circuits)PC Board

Bond Pad

Bond Wire

Transmission Line

Pins

Input Output

ICs ICs

Chip-to-Chip Connection

IC Chip with Bond Pads

Bond Pad

Electro-Static Discharge(ESD)

Die(Integrated Circuits)

Si Substrate

Metal

InsulatorOxide

Close Shot of Bond Pad

Bonding Wire

Bond Pad

Bond Wire

Analog Reference Pad

Bi-Directional Pad with Buffer

Ground Pad

Input Pad with Buffer

I/O Pad

Padless Corner Pad

Padless Spacer Pad

Pad No Connect Pad

Output Pad with Buffer

Power Pad

Classification of Bond Pads

ESD Pad

Example I/O ESD Pad:

--- Eliminate Harmful Static Charge

ESD Transistor PMOS

Pad Logic

ESD Transistor NMOS

Bond Pad

Layout Schematic

Bond Pad Parasitics - Capacitance

Si Substrate

Metal

InsulatorOxide

padC

Metal Layer

Substrate

Plate Capacitor

0

20

40

60

80

100

120

140

160

1.5u 0.5u 0.35u 0.25u

Process

Pad

Cap

acit

ance

(pF

)

Pad Parasitic Capacitance vs. Process

(Ref: MOSIS)

Effects of Bond Pad Parasitics on Circuit Performance --- Matching

IC Package

Die

PinBond Wire

Bond Pad

Bond Pad

Bond Wire

Pin

Package Parasitics

Bond Pad(Several Hundred femto-Farad)

Bond Wire & Pin(Several nano-Henry)

Effects of Bond Pad Parasitics on Circuit Performance --- Matching

Chip-to-Chip Connection on PC Board

Bond PadBond Wire

Transmission Line

Pins

Effects of Bond Pad Parasitics on Circuit Performance --- Matching

Input Output

Transmission Line

Input OutputIC 1 IC 2

IC 1 IC 2

Transmission Line

IC 1 IC 2

Effects of Bond Pad Parasitics on Circuit Performance --- Matching

Match impedance on board with bond pads, bond wire and pins:

Input Output

Tune to Z0 Tune to Z0 Tune to Z0 Z0

If Impedances are not matched, signals will get reflected.

Why to Match? • Maximize Power Transformation• Eliminate Reflection

CMOS Low Noise AmplifierIC1 Input Circuit

• Inductor L1 and capacitors C1 and C2 are on – chip components for input matching.

• Inductor L2 is the downbond inductor and is also used in input matching.

• In addition to the shown components the pad capacitance and package model were taken into consideration.

Matching

• Looking into the MOSFET M1, input impedance

• The real part is made to be 50 Ohms.

• Inductors L1 and C1 give additional degrees of freedom to have the input resonate at 2.4 GHz

• Values are tuned to include effects of pad and package parasitics

• Models provided by the foundry were used for on-chip inductors and capacitors.

21

2 LC

g

sCsLZ

gs

m

gsin Real part

Transistor sizing

• Sizing is an important factor in the Power consumed vs. Noise Figure trade off. The expression below is derived by constraining the power consumed and then optimizing the Noise Figure.

• Substituting appropriate values gives a transistor size of W = 200 microns.

soxopt RLC

W3

1

= Operating frequencyL = Device LengthRs = Source Resistance

CMOS LNA Layout

Input_L1

Input_C1

Output_C2MOSFETs

Simulation Results

•Simulation results

–Operating at 2.4 GHz

–Power gain = 21 dB

–Noise Figure = 2.7 dB

–Supply voltage = 2.5V

–Idc = 7.5 mA

This is a test chip.Results are obtained for an output termination of 50 Ohms

Effects of Bond Pad Parasitics on Circuit Performance --- Matching

Example Circuit: RF Power Amplifier

Bond Pad, Bond Wire, and Pin

Bond Pad, Bond Wire, and Pin

Bond pad, bond wire, and pin add together which shift the resonant frequency, decrease the power gain, and narrow the bandwidth of the amplifier.

PA without bond pads or package parasitics

PA with bond pads and package parasitics

Device Switching Details Performance Improves by

the reduction of the capacitive load the utilization of the halo implants

General Device Hierarchy

=>

=>

=>

Governing Equations

/ <= \

=>

<=

Supplementary device equations

Device Equations are solved for each mesh point

=>SupplementaryLumped circuit

equation

Potential Distribution:

The applied voltage at the gate is shared between the oxide and the surface after the built-in voltages are deducted. More electrons are attracted to the channel as VGS gets higher. This also drags the surface potential to a higher levelAs the gate voltage increases, the surface potential does not increase linearly, causing the vertical electrical field to take higher values. This might eventually lead to a breakdown, around 3MV/cm

Carrier Distribution:

To turn the device on, the minority carriers are attracted to the oxide interface, ultimately they invert the surface and form a conductive channel, by the application of a positive VGS for electrons and negative for holesWhen the device is turned on, the accumulation of the carriers at the interface forms the conductive path

Example Solutions of the Previous Equations

VGS=1V EOX_MAX=3MV/cm VGS=5V EOX_MAX=15MV/cm

Potential Distribution for VGS=1V and VGS=5V VDS=1.5V and VSB=0V

Electron Concentration of NMOS throughout the substrate, specifically around the interface, when the channel is on and

offOff On

The bump shows the attracted carriers

Hole Concentration of PMOS throughout the substrate, specifically around the interface, when the channel is on and

offOn Off

The bump shows the attracted carriers