Jan 4-8, 2008 VLSI Design Conference 1 Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation Yuanlin Lu Intel Corporation,
Jan. 2007VLSI Design '071 Statistical Leakage and Timing Optimization for Submicron Process Variation Yuanlin Lu and Vishwani D. Agrawal ECE Dept. Auburn.
