4 Bit Fast Adder Design Topology and Layout With Self Resetting Logic for Low Power VLSI Circuits 197 205
33.IJAEST-Vol-No-5-Issue-No-2- Energy-Efficient-Domino-VLSI-Circuits-and-their-Performance-with-PVT-
EE141 © Forrest Brewer and © Digital Integrated Circuits 2nd Combinational Circuits 1 Designing Static CMOS Logic Circuits.