SEE Mitigation Strategies for Digital Circuit Design Applicable to ASIC and FPGAs Prof. Fernanda Lima Kastensmidt, Ph.D. Instituto de Informatica Universidade.
Maste Thesis Ap Thiago Assis
The Latchup Monitor System, ESA Meeting, December 9 th 2014 R. Secondo, A Masi, R. Losito, P. Peronnard, R. D’Aguanno, R. Ferraro The Latchup Monitor System,
Avionics Architecture December 2008. 30 November 2009ULG - Avionics Overview2 Avionics Hardware & Software Processor, Buses, Equipments Command & Control.
MDT-ASD PRR C. Posch30-Aug-01 1 Radiation Hardness Assurance Total Ionizing Dose (TID) Change of device (transistor) properties, permanent Single.
12004 MAPLD: 141Buchner Single Event Effects Testing of the Atmel IEEE1355 Protocol Chip Stephen Buchner 1, Mark Walter 2, Moses McCall 3 and Christian.
Petrick_P2261 Virtex-II Pro SEE Test Methods and Results David Petrick 1, Wesley Powell 1, James Howard 2 1 NASA Goddard Space Flight Center, Greenbelt,
