Workshop on HPC in India Programming Models, Languages, and Compilation for Accelerator-Based Architectures R. Govindarajan SERC, IISc [email protected].
VTU – IISc Workshop (C)RG@SERC,IISc Compiler, Architecture and HPC Research in Heterogeneous Multi-Core Era R. Govindarajan CSA & SERC, IISc govind@[csa,serc].iisc.ernet.in.
![VTU – IISc Workshop (C)RG@SERC,IISc Compiler, Architecture and HPC Research in Heterogeneous Multi-Core Era R. Govindarajan CSA & SERC, IISc govind@[csa,serc].iisc.ernet.in.](https://static.fdocuments.in/doc/330x215/56649eeb5503460f94bfc78b/vtu-iisc-workshop-crgserciisc-compiler-architecture-and-hpc-research.jpg)
