Dynamic Thread Mapping for High- Performance, Power-Efficient Heterogeneous Many-core Systems Guangshuo Liu Jinpyo Park Diana Marculescu Presented By Ravi.
Core Architecture Optimization for Heterogeneous Chip Multiprocessors Rakesh Kumar, Deam M Tullsen, UCSD Norman P Jouppi, HP Labs, Palo Alto, CA PACT’06.
Core Architecture Optimization for Heterogeneous Chip Multiprocessors
Dynamic Thread Mapping for High-Performance, Power-Efficient Heterogeneous Many-core Systems
